1.
	a. 256 mb 2^28
	b. 512 kb 2^19
	c. 2^4=16
	d. 2^5

2.
	a.	tag	line	offset
		[8bit]	[5bit]	[3bit]
	b.
		i.	0001 0001 [0001 1]011	3
		ii.	1100 0011 [0011 0]100	6
		iii.	1101 0000 [0001 1]101	3
		iv.	1010 1010 [1010 1]010	21
	c. 256	[offset]*line

3.
	a.
		444444 = [0100 0100][0100 0100 0100 01][00]
		999999 = [1001 1001][1001 1001 1001 10][01]
		CCCCCC = [1100 1100][1100 1100 1100 11][00]
	b.
		444444 = [0100 0100 0100 0100 0100 01][00]
		999999 = [1001 1001 1001 1001 1001 10][01]
		CCCCCC = [1100 1100 1100 1100 1100 11][00]

4. Consider a CPU with the following specifications:
	* It can access 256 words of memory, each word being 8 bits wide.	The CPU does this by outputting a 8-bit address on its output pins A[7…0] and reading in the 8-bit value from memory on its inputs D[7…0]
	* The CPU contains an 8-bit address register (AR), program counter (PC), accumulator (AC), data register (DR), and a 4-bit instruction register (IR).
	* The CPU must realize the following instruction set. Note that β is an 8-bit value stored in the location immediately following the instruction

	a. 
		LD {
			mov DR, M[beta]
			mov AC, DR
			mov PC, PC+1
		}
		STI {
			mov AC, DR
			mov DR, M[beta]
			mov PC, PC+1
		}
		ADD {
			mov DR, M[beta]
			mov 
			mov PC, PC+1
		}
		JMP {
			mov PC, beta
		}
		SKIP {
			mov PC, PC+1
		}
		RST {
			mov PC, 0
			mov AC, 0
		}
	b. 
		[AR]->
		[PC]->
		[AC]->
		[DR]->

		[IR]->