From 2b78082f0e0c4dae86463aed269aa121fdd2d449 Mon Sep 17 00:00:00 2001 From: sparky4 Date: Thu, 15 Oct 2015 20:24:51 -0500 Subject: [PATCH] added tweak16 for experiments --- 16/tweak16/09TO10.CPP | 147 +++++ 16/tweak16/132X25S.TWK | Bin 0 -> 144 bytes 16/tweak16/132X43S.TWK | Bin 0 -> 144 bytes 16/tweak16/132X50S.TWK | Bin 0 -> 144 bytes 16/tweak16/132X60S.TWK | Bin 0 -> 116 bytes 16/tweak16/16.2 | Bin 0 -> 100 bytes 16/tweak16/16.256 | Bin 0 -> 100 bytes 16/tweak16/162.C | 29 + 16/tweak16/162.EXE | Bin 0 -> 132 bytes 16/tweak16/192X144.256 | Bin 0 -> 100 bytes 16/tweak16/256X192.256 | Bin 0 -> 100 bytes 16/tweak16/256X224.256 | Bin 0 -> 100 bytes 16/tweak16/256X240.256 | Bin 0 -> 100 bytes 16/tweak16/256X256.256 | Bin 0 -> 100 bytes 16/tweak16/256X256C.256 | Bin 0 -> 100 bytes 16/tweak16/320X200.256 | Bin 0 -> 100 bytes 16/tweak16/320X240.256 | Bin 0 -> 100 bytes 16/tweak16/320X240.C | 29 + 16/tweak16/320X240.EXE | Bin 0 -> 132 bytes 16/tweak16/320X400.256 | Bin 0 -> 100 bytes 16/tweak16/360X270.256 | Bin 0 -> 100 bytes 16/tweak16/360X360.256 | Bin 0 -> 100 bytes 16/tweak16/360X400.256 | Bin 0 -> 100 bytes 16/tweak16/360X480.256 | Bin 0 -> 100 bytes 16/tweak16/376X564.256 | Bin 0 -> 100 bytes 16/tweak16/400X300.256 | Bin 0 -> 104 bytes 16/tweak16/400X300S.256 | Bin 0 -> 144 bytes 16/tweak16/400X600.256 | Bin 0 -> 104 bytes 16/tweak16/400X600S.256 | Bin 0 -> 144 bytes 16/tweak16/40X12.TWK | Bin 0 -> 104 bytes 16/tweak16/432X600S.256 | Bin 0 -> 144 bytes 16/tweak16/640X400S.256 | Bin 0 -> 108 bytes 16/tweak16/800X600.16 | Bin 0 -> 100 bytes 16/tweak16/800X600S.16 | Bin 0 -> 104 bytes 16/tweak16/80X43.TWK | Bin 0 -> 144 bytes 16/tweak16/80X50.TWK | Bin 0 -> 144 bytes 16/tweak16/C&T.DAT | 47 ++ 16/tweak16/DETECT.CPP | 135 ++++ 16/tweak16/DETECT.HPP | 29 + 16/tweak16/EXAMPLE1.C | 87 +++ 16/tweak16/EXAMPLE1.EXE | Bin 0 -> 14032 bytes 16/tweak16/EXAMPLE2.C | 81 +++ 16/tweak16/EXAMPLE2.EXE | Bin 0 -> 14160 bytes 16/tweak16/MAKEFILE | 50 ++ 16/tweak16/MISC.HPP | 39 ++ 16/tweak16/MISC/CHIPTECH.TXT | 1135 ++++++++++++++++++++++++++++++++++ 16/tweak16/MISC/READ.ME | 66 ++ 16/tweak16/MISC/SETMODEX.ASM | 87 +++ 16/tweak16/MISC/VGA.TXT | 551 +++++++++++++++++ 16/tweak16/MISC/VGABIOS.TXT | 707 +++++++++++++++++++++ 16/tweak16/MODES.DOC | 99 +++ 16/tweak16/NAMEDREG.CPP | 52 ++ 16/tweak16/REGEDIT.CPP | 70 +++ 16/tweak16/REGEDIT.HPP | 22 + 16/tweak16/REGISTER.CPP | 129 ++++ 16/tweak16/REGISTER.HPP | 91 +++ 16/tweak16/REGTABLE.CPP | 123 ++++ 16/tweak16/REGTABLE.HPP | 36 ++ 16/tweak16/SCREEN.CPP | 138 +++++ 16/tweak16/SCREEN.HPP | 50 ++ 16/tweak16/TESTPAT.CPP | 440 +++++++++++++ 16/tweak16/TESTPAT.HPP | 38 ++ 16/tweak16/TWEAK.CPP | 389 ++++++++++++ 16/tweak16/TWEAK.DAT | 30 + 16/tweak16/TWEAK.DOC | 1054 +++++++++++++++++++++++++++++++ 16/tweak16/TWEAK.EXE | Bin 0 -> 66496 bytes 16/tweak16/TWEAK2C.CPP | 58 ++ 16/tweak16/TWEAK2C.EXE | Bin 0 -> 24448 bytes 16/tweak16/TWEAKOLD.DAT | 44 ++ 16/tweak16/TWKUSER.C | 134 ++++ 16/tweak16/TWKUSER.H | 45 ++ 16/tweak16/VGALIB.CPP | 386 ++++++++++++ 16/tweak16/VGALIB.HPP | 97 +++ 16/tweak16/XINTRO/LIB.EXE | Bin 0 -> 9446 bytes 16/tweak16/XINTRO/LIB.SMP | Bin 0 -> 599 bytes 16/tweak16/XINTRO/M13ORG.ASC | 55 ++ 16/tweak16/XINTRO/M13ORG.GIF | Bin 0 -> 8860 bytes 16/tweak16/XINTRO/MXORG.ASC | 49 ++ 16/tweak16/XINTRO/MXORG.GIF | Bin 0 -> 10178 bytes 16/tweak16/XINTRO/RUN.BAT | 3 + 16/tweak16/XINTRO/XINTRO.TXT | 569 +++++++++++++++++ 16/tweak16/XINTRO/XINTRO.zip | Bin 0 -> 40240 bytes 16/tweak16/XINTRO/lib.c | 352 +++++++++++ 16/tweak16/XINTRO/x.bat | 2 + 84 files changed, 7774 insertions(+) create mode 100755 16/tweak16/09TO10.CPP create mode 100755 16/tweak16/132X25S.TWK create mode 100755 16/tweak16/132X43S.TWK create mode 100755 16/tweak16/132X50S.TWK create mode 100755 16/tweak16/132X60S.TWK create mode 100755 16/tweak16/16.2 create mode 100755 16/tweak16/16.256 create mode 100755 16/tweak16/162.C create mode 100755 16/tweak16/162.EXE create mode 100755 16/tweak16/192X144.256 create mode 100755 16/tweak16/256X192.256 create mode 100755 16/tweak16/256X224.256 create mode 100755 16/tweak16/256X240.256 create mode 100755 16/tweak16/256X256.256 create mode 100755 16/tweak16/256X256C.256 create mode 100755 16/tweak16/320X200.256 create mode 100755 16/tweak16/320X240.256 create mode 100755 16/tweak16/320X240.C create mode 100755 16/tweak16/320X240.EXE create mode 100755 16/tweak16/320X400.256 create mode 100755 16/tweak16/360X270.256 create mode 100755 16/tweak16/360X360.256 create mode 100755 16/tweak16/360X400.256 create mode 100755 16/tweak16/360X480.256 create mode 100755 16/tweak16/376X564.256 create mode 100755 16/tweak16/400X300.256 create mode 100755 16/tweak16/400X300S.256 create mode 100755 16/tweak16/400X600.256 create mode 100755 16/tweak16/400X600S.256 create mode 100755 16/tweak16/40X12.TWK create mode 100755 16/tweak16/432X600S.256 create mode 100755 16/tweak16/640X400S.256 create mode 100755 16/tweak16/800X600.16 create mode 100755 16/tweak16/800X600S.16 create mode 100755 16/tweak16/80X43.TWK create mode 100755 16/tweak16/80X50.TWK create mode 100755 16/tweak16/C&T.DAT create mode 100755 16/tweak16/DETECT.CPP create mode 100755 16/tweak16/DETECT.HPP create mode 100755 16/tweak16/EXAMPLE1.C create mode 100755 16/tweak16/EXAMPLE1.EXE create mode 100755 16/tweak16/EXAMPLE2.C create mode 100755 16/tweak16/EXAMPLE2.EXE create mode 100755 16/tweak16/MAKEFILE create mode 100755 16/tweak16/MISC.HPP create mode 100755 16/tweak16/MISC/CHIPTECH.TXT create mode 100755 16/tweak16/MISC/READ.ME create mode 100755 16/tweak16/MISC/SETMODEX.ASM create mode 100755 16/tweak16/MISC/VGA.TXT create mode 100755 16/tweak16/MISC/VGABIOS.TXT create mode 100755 16/tweak16/MODES.DOC create mode 100755 16/tweak16/NAMEDREG.CPP create mode 100755 16/tweak16/REGEDIT.CPP create mode 100755 16/tweak16/REGEDIT.HPP create mode 100755 16/tweak16/REGISTER.CPP create mode 100755 16/tweak16/REGISTER.HPP create mode 100755 16/tweak16/REGTABLE.CPP create mode 100755 16/tweak16/REGTABLE.HPP create mode 100755 16/tweak16/SCREEN.CPP create mode 100755 16/tweak16/SCREEN.HPP create mode 100755 16/tweak16/TESTPAT.CPP create mode 100755 16/tweak16/TESTPAT.HPP create mode 100755 16/tweak16/TWEAK.CPP create mode 100755 16/tweak16/TWEAK.DAT create mode 100755 16/tweak16/TWEAK.DOC create mode 100755 16/tweak16/TWEAK.EXE create mode 100755 16/tweak16/TWEAK2C.CPP create mode 100755 16/tweak16/TWEAK2C.EXE create mode 100755 16/tweak16/TWEAKOLD.DAT create mode 100755 16/tweak16/TWKUSER.C create mode 100755 16/tweak16/TWKUSER.H create mode 100755 16/tweak16/VGALIB.CPP create mode 100755 16/tweak16/VGALIB.HPP create mode 100755 16/tweak16/XINTRO/LIB.EXE create mode 100755 16/tweak16/XINTRO/LIB.SMP create mode 100755 16/tweak16/XINTRO/M13ORG.ASC create mode 100755 16/tweak16/XINTRO/M13ORG.GIF create mode 100755 16/tweak16/XINTRO/MXORG.ASC create mode 100755 16/tweak16/XINTRO/MXORG.GIF create mode 100755 16/tweak16/XINTRO/RUN.BAT create mode 100755 16/tweak16/XINTRO/XINTRO.TXT create mode 100755 16/tweak16/XINTRO/XINTRO.zip create mode 100755 16/tweak16/XINTRO/lib.c create mode 100755 16/tweak16/XINTRO/x.bat diff --git a/16/tweak16/09TO10.CPP b/16/tweak16/09TO10.CPP new file mode 100755 index 00000000..53aa8421 --- /dev/null +++ b/16/tweak16/09TO10.CPP @@ -0,0 +1,147 @@ +/* + 09TO10 1.0 - convert TWEAK 0.9 files to TWEAK 1.0 files + + by Robert Schmidt of Ztiff Zox Softwear, 1992-93 + + For documentation, see TWEAK.DOC. + + Most of the starting definitions was taken from the TWEAK095.CPP + file included elsewhere, so comments are removed. +*/ + +#ifndef __LARGE__ +# ifndef __COMPACT__ +# ifndef __HUGE__ +# error A large data model is required! +# endif +# endif +#endif + + +#include +#include +#include +#include +#include + +#include "Register.hpp" + + +struct vgaRegisterInfo + { + char *name; + unsigned port; + unsigned char index; + }; + +vgaRegisterInfo table[] = + { + {"Misc. output", 0x3c2, 0x00}, + + {"Horizontal total", 0x3d4, 0x00}, + {"Horizontal disp. enable", 0x3d4, 0x01}, + {"Horizontal blank start", 0x3d4, 0x02}, + {"Horizontal blank end", 0x3d4, 0x03}, + {"Horizontal retrace start",0x3d4, 0x04}, + {"Horizontal retrace end", 0x3d4, 0x05}, + {"Vertical total", 0x3d4, 0x06}, + {"Overflow register", 0x3d4, 0x07}, + {"Preset row scan", 0x3d4, 0x08}, + {"Max scan line/char ht.", 0x3d4, 0x09}, + + {"Vertical retrace start", 0x3d4, 0x10}, + {"Vertical retrace end", 0x3d4, 0x11}, + {"Vert. disp. enable end", 0x3d4, 0x12}, + {"Offset/Logical width", 0x3d4, 0x13}, + {"Underline location", 0x3d4, 0x14}, + {"Vertical blank start", 0x3d4, 0x15}, + {"Vertical blank end", 0x3d4, 0x16}, + {"Mode control", 0x3d4, 0x17}, + + {"Clock mode register", 0x3c4, 0x01}, + {"Color plane write enable",0x3c4, 0x02}, + {"Character gen. select", 0x3c4, 0x03}, + {"Memory mode register", 0x3c4, 0x04}, + + {"Set/reset register", 0x3ce, 0x00}, + {"Set/reset enable", 0x3ce, 0x01}, + {"Color compare", 0x3ce, 0x02}, + {"Data rotate & function", 0x3ce, 0x03}, + {"Mode register", 0x3ce, 0x05}, + {"Miscellaneous register", 0x3ce, 0x06}, + {"Color don't care", 0x3ce, 0x07}, + {"Bit mask register", 0x3ce, 0x08}, + + {"Mode control", 0x3c0, 0x10}, + {"Screen border colour", 0x3c0, 0x11}, + {"Color plane enable", 0x3c0, 0x12}, + {"Horizontal panning", 0x3c0, 0x13}, + {"Color select", 0x3c0, 0x14} + }; + +const registers = sizeof (table) / sizeof (vgaRegisterInfo); + + +class vgaRegTable + { + unsigned char value[registers]; + unsigned char selectedReg; +public: + void out(); + void in(); + void print(unsigned char selected); + void printOne(unsigned char r, int isSelected); + unsigned char& operator [] (unsigned char n) + { return value[n]; } + }; + + +// The main program starts here. + +main(int argc, char **argv) + { + if (argc < 3) + { + printf("09TO10 version 1.0\n\r" + "by Robert Schmidt of Ztiff Zox Softwear 1993\n\r" + "\n\r" + "Converts TWEAK version 0.9 files to TWEAK version 1.0 files.\n\r" + "\n\r" + "Syntax: 09TO10 \n\r" + ); + return 0; + } + + vgaRegTable rtab; + + char *fname = argv[1]; + FILE *f; + int r; + + // Open file in selected mode. + if (!(f=fopen(fname,"rb"))) + { + perror(fname); + return 0; + } + // Read file: + for (r=0; rN49pih2zv^5 z7XBhQiQ+2Cqo_Wj-ipS=Y%kh}=x(B)#IO@%{#JLfev8d3;#|ZN!6JoEm?d21GqSQx WREtENck>Ih^FU{Tei;~YNBaY&7AU*` literal 0 HcmV?d00001 diff --git a/16/tweak16/132X43S.TWK b/16/tweak16/132X43S.TWK new file mode 100755 index 0000000000000000000000000000000000000000..4c677d8080d21aa288670306bb02a70ec1f010f3 GIT binary patch literal 144 zcmWNHyA1*{6a=3=_d`N(+#L|o3kfBV(h49Vnm{6?0WvJ)*wOX_FBt7gGhgf_>>;#rl3dB`T(LPaQRV77jOm(8wMkWAxvmog{C%8wP;toG6RDrbih$1pl?CcD I&}_E00%p%4N&o-= literal 0 HcmV?d00001 diff --git a/16/tweak16/16.2 b/16/tweak16/16.2 new file mode 100755 index 0000000000000000000000000000000000000000..c61439375f71cc7a47c66f798ecf4cdcf121b01c GIT binary patch literal 100 zcmWN_y$ymu0D#duKkm?ih=MPy6hP63m;c4W1O;UUr!X>s7WS@UoW~)Ep{BaM1%-)I=qb;Om?dsfoMmwl x9#UQ<-6gMOd6X(-)l2=A%~Q5-X%5o+rjNuBE5Acf#1;ud)@Gw^Qr zmpL;_BGVK#?=<&=jlv$nokda$o+538Z$(&(#YHSltSXWHME(}VQIrR&U# xONxi2r{qf3SJ?z9d#S&&ear4F%}Lt-?>}Pi06@_@|J|vvK|pPtM4@#FM=@~>!!X2<*irq;mPPcH?@d@F+$COR)d^2Y vH_0z4J6T_36J*;<^_Be~^+TGowEsVRPi06@_@|J|vvK|pPtM4@#FcX15kE)YXvNA)XP7SUI}H(`-*mw1&`Cp;wG uBtNC>WPOoMkZmv3SN1Qd2WigI{{QfiW0KP{5#vNEGr5~7d8Fz`n(zZPTpiZ{ literal 0 HcmV?d00001 diff --git a/16/tweak16/256X240.256 b/16/tweak16/256X240.256 new file mode 100755 index 0000000000000000000000000000000000000000..c607a6255b1438fc76dc599c3acb492efffe54e1 GIT binary patch literal 100 zcmWN_u?>Pi06@_@KX*z&f`ZyQiNFG^;4Ti~6b?ZQHP!DeC`_C}U-@2yRl-eTC!1cl wOEF4%NUmgim0gf>koqh8rySnWT%`T~@gt`!=XEB=nIbQwej%rcdYEX!4@OWPI{*Lx literal 0 HcmV?d00001 diff --git a/16/tweak16/256X256.256 b/16/tweak16/256X256.256 new file mode 100755 index 0000000000000000000000000000000000000000..33c6dcc895bd717f253632fc234b71ae5051c745 GIT binary patch literal 100 zcmWN_u?>Pi06@_@KX;%NieO@8;viz{62?^=!x^lYfEa43zX5}&uY4cEBH=FaBCB3_ wN^z6)l6;nOkSfUfA@xSKZ`pmNIm!P2Z7JPR4$DN06Gfg${Y*|H^>w5PKP_e*SpWb4 literal 0 HcmV?d00001 diff --git a/16/tweak16/256X256C.256 b/16/tweak16/256X256C.256 new file mode 100755 index 0000000000000000000000000000000000000000..a87dce48d8f84e7767b8a87cac6b7f98f1aacdc1 GIT binary patch literal 100 zcmWN{u?>Pi06@_@KL=`IKu{Aa69*AnmoTj27`C=lOh61Z)!)ED)K|YZ;UnQL@gj>> ycu01W^pyN8#URTdt4_+bRK0A!QlF&x|6L*bqa0onF-~NgnbgkYX{5Z4)Zqs(?j2zO literal 0 HcmV?d00001 diff --git a/16/tweak16/320X200.256 b/16/tweak16/320X200.256 new file mode 100755 index 0000000000000000000000000000000000000000..316e15499478e253de23b33ab2f750a3173fcbde GIT binary patch literal 100 zcmWN_F%rQ*06@`QKf9p|K}v0oAt#{FD_q1l09`5gx9#!kh+!i|2MsCU($R>VjL;*MA}c}G*EQ|b@%}*eI5(| literal 0 HcmV?d00001 diff --git a/16/tweak16/320X240.256 b/16/tweak16/320X240.256 new file mode 100755 index 0000000000000000000000000000000000000000..e1f924bfc4d86f1b0bb41dc754e915dbfa80bcfd GIT binary patch literal 100 zcmWN_u?>Pi06@_@KX+43VT;E&f^foP*eThg2Kcp^p)>LSR~ve_Ocp; xhZI*ycgdx!FR}@;?WFq3?kW4X)Msh_fB48T%W0X2aiYjGsh!Dbr0PcM@B>Z&9#a4S literal 0 HcmV?d00001 diff --git a/16/tweak16/320X240.C b/16/tweak16/320X240.C new file mode 100755 index 00000000..0041f3e8 --- /dev/null +++ b/16/tweak16/320X240.C @@ -0,0 +1,29 @@ +#include "TwkUser.h" // get Register definition +Register Mode320x240[] = + { + { 0x3c2, 0x0, 0xe3}, + { 0x3d4, 0x0, 0x5f}, + { 0x3d4, 0x1, 0x4f}, + { 0x3d4, 0x2, 0x50}, + { 0x3d4, 0x3, 0x82}, + { 0x3d4, 0x4, 0x54}, + { 0x3d4, 0x5, 0x80}, + { 0x3d4, 0x6, 0xd}, + { 0x3d4, 0x7, 0x3e}, + { 0x3d4, 0x8, 0x0}, + { 0x3d4, 0x9, 0x41}, + { 0x3d4, 0x10, 0xea}, + { 0x3d4, 0x11, 0xac}, + { 0x3d4, 0x12, 0xdf}, + { 0x3d4, 0x13, 0x28}, + { 0x3d4, 0x14, 0x0}, + { 0x3d4, 0x15, 0xe7}, + { 0x3d4, 0x16, 0x6}, + { 0x3d4, 0x17, 0xe3}, + { 0x3c4, 0x1, 0x1}, + { 0x3c4, 0x4, 0x6}, + { 0x3ce, 0x5, 0x40}, + { 0x3ce, 0x6, 0x5}, + { 0x3c0, 0x10, 0x41}, + { 0x3c0, 0x13, 0x0} + }; diff --git a/16/tweak16/320X240.EXE b/16/tweak16/320X240.EXE new file mode 100755 index 0000000000000000000000000000000000000000..0d67ae82cb8028256d8635f833b96e0e5eb48d8e GIT binary patch literal 132 zcmXYlF%E)26b1h>>?(x`3TkWVDU2MzXklgJRSe-c9)cKZs@Gdkn0N`;f|txp@-C0Y zoS7w&ag3UGnESy7VNc<%BDo1_k=})WiLerjlUSO_Dv|%i`YkqJQ5;1X|Lsrgg4hoo R&UK`r$DezGZ^^5c!Y1SbA)f#M literal 0 HcmV?d00001 diff --git a/16/tweak16/320X400.256 b/16/tweak16/320X400.256 new file mode 100755 index 0000000000000000000000000000000000000000..3ceb4bd73d9652ccfa153c1b0ef393acdd41be98 GIT binary patch literal 100 zcmWN_F%rQ*06@`QKf9p|K}v0o5htL~D_q1l09`5gx9#!kh+!i|2MsCU($R>VjL;*MCvAT8mRUIb@%}*L>>zO literal 0 HcmV?d00001 diff --git a/16/tweak16/360X270.256 b/16/tweak16/360X270.256 new file mode 100755 index 0000000000000000000000000000000000000000..e4c1cfb34f790c3a15e3244b98a5799001ef3d19 GIT binary patch literal 100 zcmWN_Jrcn{0D#e5Uv|-j_$d@zz;FbPL6I4CZlZ7xx5${(slFR1(mF!C@_h({ght{` zCU@Z_MJ?$m`7G0)%!14xQXXXSmgP>WqpbeF-pl4B+iypV9YyX*m!6zj%4j+Rich8LZ3G)&5 zDYBPf6z(njSA^ZeUmT4%^&;LxK8T_bWi6`x&#kz0;<_fRO}Mb&?+d|C#K%NwHern( A1ONa4 literal 0 HcmV?d00001 diff --git a/16/tweak16/400X300.256 b/16/tweak16/400X300.256 new file mode 100755 index 0000000000000000000000000000000000000000..cf526b155fefb89ad7ddf4864fc4da26bb1e78d1 GIT binary patch literal 104 zcmWN_%@M&s0D#fmeA&fGh@YbZ91Io2jL`@R(1B5cCbW?;d(P?WKqI{4`w-p|?h-Fj zU4@s_H%U*)XBll|9Awf-vzOUJ=38kGviSdUC##dJzl9hJ)wEFOfz%D;)YBY$+VBH& CT^(Ei literal 0 HcmV?d00001 diff --git a/16/tweak16/400X300S.256 b/16/tweak16/400X300S.256 new file mode 100755 index 0000000000000000000000000000000000000000..74bf41ee3fd6ce7892b271f0b6f48500b7e423bc GIT binary patch literal 144 zcmWNHxeWqA5Cmth?zQd(@*o0;0(|fx4J3kEoz`Bf13<#WAp;nr)KXQi*hknygo`My zf~P2NqUuC_7tL3+Cc2jx&SLaFoy5Esi~Ehct^aoKLsj?{a literal 0 HcmV?d00001 diff --git a/16/tweak16/400X600.256 b/16/tweak16/400X600.256 new file mode 100755 index 0000000000000000000000000000000000000000..c701a9255eef3c507da19d498c1a8203d191424d GIT binary patch literal 104 zcmWN{u?>Pi0EW>!KJLT{1cW`90H%P%#zgI%!J3MRh`E~T-+;o_5xDl{eK9{_-oida z@)Rs0eF^swKKkh|G9%7+QQX937Ud|aPSnw_lW5{=_kgv5BoCy1!}S~9trWvbWe)fT BA8h~t literal 0 HcmV?d00001 diff --git a/16/tweak16/400X600S.256 b/16/tweak16/400X600S.256 new file mode 100755 index 0000000000000000000000000000000000000000..5d187023f77196dab44a5ce9c501db073b63c7a6 GIT binary patch literal 144 zcmWNHxeWqA5Cmth?zQd(@*o0;0!$?EAq^ygTAkKjt24mFAp;nr)KXQi*hkn?gsUiS zf|n@oqUuEb5Y1P#Cc29l&SLaFoy5Esi~Ehct^aoKLcQPn+ literal 0 HcmV?d00001 diff --git a/16/tweak16/40X12.TWK b/16/tweak16/40X12.TWK new file mode 100755 index 0000000000000000000000000000000000000000..201a1e0c0f68e395fc3c877e08d6efcf314a09e5 GIT binary patch literal 104 zcmWN`u@1pd06@{#-nO1ZBy<2TI2vhmSL`F~CBjWq zj;E;aqKTq?i0&(T6Pv3TE@Jd{I*a)r7XP>Y?Y!H+Ga+QEn87l2TQDmGS2rgfzKi_vbXR-gs;di;%MS@7sVvXm#79&-^6+UW)$s5bX&r?1eVCcitkr~j}+HP=_0lL E0fZPJzyJUM literal 0 HcmV?d00001 diff --git a/16/tweak16/800X600.16 b/16/tweak16/800X600.16 new file mode 100755 index 0000000000000000000000000000000000000000..b6f266f5c081d25e0e2803694404d6051b46f329 GIT binary patch literal 100 zcmWN{u?>Pi7>42hc)0^Q@BsH<8BJ_Vl-?PvshH?OsHwgUENmUYYo9zD_7(OL?jee& xU=`&o{9An~;O!vzjoNLrb^+S29+Ch6 literal 0 HcmV?d00001 diff --git a/16/tweak16/80X43.TWK b/16/tweak16/80X43.TWK new file mode 100755 index 0000000000000000000000000000000000000000..a7d1ee37d3a601359e786f13c95fa7982d428b07 GIT binary patch literal 144 zcmWN`yA1*{6hzTy-~AyW*dGv*(g`6Xh!9#~5tVEcWLU_tqv;169Nm%Ti_OAr!kvUa z3no!qMEMZaN7Q@Km{=S|`xM;cztuym-(vHMI2Z9mut?z(W(k-1jI3-E V)gn>n-TVUWJkVL7Uj~NU(f%XcC$azl literal 0 HcmV?d00001 diff --git a/16/tweak16/C&T.DAT b/16/tweak16/C&T.DAT new file mode 100755 index 00000000..8fa3d19b --- /dev/null +++ b/16/tweak16/C&T.DAT @@ -0,0 +1,47 @@ +45 +3c2 00 Misc. output +3d4 00 Horizontal total +3d4 01 Horizontal disp. enable +3d4 02 Horizontal blank start +3d4 03 Horizontal blank end +3d4 04 Horizontal retrace start +3d4 05 Horizontal retrace end +3d4 06 Vertical total +3d4 07 Overflow register +3d4 08 Preset row scan +3d4 09 Max scan line/char ht. +3d4 10 Vertical retrace start +3d4 11 Vertical retrace end +3d4 12 Vert. disp. enable end +3d4 13 Offset/Logical width +3d4 14 Underline location +3d4 15 Vertical blank start +3d4 16 Vertical blank end +3d4 17 Mode control +3c4 01 Clock mode register +3c4 02 Color plane write enable +3c4 03 Character gen. select +3c4 04 Memory mode register +3ce 00 Set/reset register +3ce 01 Set/reset enable +3ce 02 Color compare +3ce 03 Data rotate & function +3ce 05 Mode register +3ce 06 Miscellaneous register +3ce 07 Color don't care +3ce 08 Bit mask register +3c0 10 Mode control +3c0 11 Screen border colour +3c0 12 Color plane enable +3c0 13 Horizontal panning +3c0 14 Color select +103 00 C&T: multiple enable +3d6 00 C&T: chip/revision info +3d6 01 C&T: DIP switch states +3d6 02 C&T: cpu interface +3d6 04 C&T: memory mapping +3d6 0b C&T: CPU paging +3d6 14 C&T: emulation mode +3d6 2b C&T: default video reg. +46e8 00 C&T: setup control + diff --git a/16/tweak16/DETECT.CPP b/16/tweak16/DETECT.CPP new file mode 100755 index 00000000..06eeeaa0 --- /dev/null +++ b/16/tweak16/DETECT.CPP @@ -0,0 +1,135 @@ +/* + * Mode detection: + * --------------- + * Currently incompatible with CGA and Hercules modes. + * 200-line CGA modes are detected as 100-line. + * 640x200x2 is detected as 16-color. + * Hercules not supported at all. + * Monochrome EGA/VGA modes are also *not* supported, due to use of + * different port addresses. + * + * Variables of interest: + * hPixels, vPixels - the actual resolution of the mode, in characters + * in text modes, in pixels in graphics modes. + * adrOffset - the number of addressable bytes between two vertically + * adjacent pixels, or words between two vertically adjacent + * characters in text mode. + * + */ + +#include "detect.hpp" +#include "screen.hpp" +#include +#include + + + +void ModeInfo::detectFrom(RegisterTable ®Table) + { + Register *GCMode = regTable.getRegister(GRACON_ADDR, 0x05); + Register *GCMisc = regTable.getRegister(GRACON_ADDR, 0x06); + Register *ACMode = regTable.getRegister(ATTRCON_ADDR, 0x10); + Register *CRTChde = regTable.getRegister(CRTC_ADDR, 0x01); + Register *CRTCoflo = regTable.getRegister(CRTC_ADDR, 0x07); + Register *CRTCscan = regTable.getRegister(CRTC_ADDR, 0x09); + Register *CRTCvde = regTable.getRegister(CRTC_ADDR, 0x12); + Register *CRTCoffs = regTable.getRegister(CRTC_ADDR, 0x13); + Register *CRTCmode = regTable.getRegister(CRTC_ADDR, 0x17); + Register *SEQmmode = regTable.getRegister(SEQ_ADDR, 0x04); + + int temp; + switch ((*GCMode)(5,2)) + { + case 0: + colors = COLOR16; // might also be COLOR2 !!! + hPixelsPerClock = 8; + break; + case 1: + colors = COLOR4; + hPixelsPerClock = 16; + break; + case 2: + colors = COLOR256; + hPixelsPerClock = 4; + break; + } + + temp = (**GCMisc & 1 != 0); + if (temp == (**ACMode & 1 != 0)) + alphaGraph = temp ? GRAPHICS : ALPHA; + else + alphaGraph = AG_CONFLICT; + + if (alphaGraph == ALPHA) + hPixelsPerClock = 1; + + chain4 = (*SEQmmode)(3,1); + countBy2 = (*CRTCmode)(3,1); + adrOffset = **CRTCoffs * 2 * (countBy2+1); + + hClocks = **CRTChde + 1; + vClocks = + (**CRTCvde | ((*CRTCoflo)(1,1) << 8) | ((*CRTCoflo)(6,1) << 9)) + 1; + + xres = hClocks * hPixelsPerClock; + vxresBytes = vxres = adrOffset * hPixelsPerClock; + + if (alphaGraph == ALPHA) + vxresBytes *= 2; + else + if (alphaGraph == GRAPHICS) + if (colors == COLOR16) + vxresBytes /= 8; + else + if (colors == COLOR256 && !chain4) + vxresBytes /= 4; + + lineClocks = (*CRTCscan)(0,4) + 1; + if ((*CRTCscan)(7,1) << 5) + lineClocks *= 2; + yres = vClocks / lineClocks; + spareClocks = vClocks % lineClocks; + vyres = (alphaGraph == GRAPHICS ? 65536L : 32768L) / vxresBytes; + xpages = float(vxres)/xres; + ypages = float(vyres)/yres; + } + + +GraphicsAPI *ModeInfo::getGraphicsAPI() + { + if (alphaGraph == GRAPHICS) + switch(colors) + { + case COLOR16: + return new Planar16(xres, yres, vxres); + case COLOR256: + if (chain4) + return new Chained256(xres, yres, vxres); + else + return new Unchained256(xres, yres, vxres); + } + return 0; + } + +void ModeInfo::show() + { + window(editWidth/2+2, editHeight-18, editWidth, editHeight-7); + clrscr(); + textattr(INFO_COLOR); + cprintf("This seems to be a %d-color\n\r" + "%s mode.\n\r\n\r" + "Physical resolution: %d x %d\n\r" + "Virtual resolution: %d x %d\n\r\n\r" + "Page resolution: %3.1f x %3.1f", + colors, + alphaGraph==ALPHA ? "text" : + alphaGraph==GRAPHICS ? (chain4 ? "linear graphics" : + "planar graphics") : + "graph/text conflict", + xres, yres, + vxres, vyres, + xpages, ypages + ); + window(1,1,editWidth,editHeight); + } + diff --git a/16/tweak16/DETECT.HPP b/16/tweak16/DETECT.HPP new file mode 100755 index 00000000..a26aed9e --- /dev/null +++ b/16/tweak16/DETECT.HPP @@ -0,0 +1,29 @@ +#ifndef _DETECT_HPP +#define _DETECT_HPP + +#include "misc.hpp" +#include "regtable.hpp" +#include "vgalib.hpp" + + +struct ModeInfo + { + enum EmulType { EM_CONFLICT, HERC, CGA, VGA }; + enum ColorsType { COLOR2=2, COLOR4=4, COLOR16=16, COLOR256=256 }; + enum AGType { AG_CONFLICT, ALPHA, GRAPHICS }; + + EmulType emulation; + AGType alphaGraph; + ColorsType colors; + int hClocks, vClocks, xres, yres, lineClocks, spareClocks, adrOffset, + hPixelsPerClock, vxres, vyres, vxresBytes; + float xpages, ypages; + Boolean countBy2, chain4; + + ModeInfo(RegisterTable &rt) { detectFrom(rt); } + void detectFrom(RegisterTable &); + GraphicsAPI *getGraphicsAPI(); + void show(); + }; + +#endif \ No newline at end of file diff --git a/16/tweak16/EXAMPLE1.C b/16/tweak16/EXAMPLE1.C new file mode 100755 index 00000000..ab486c6e --- /dev/null +++ b/16/tweak16/EXAMPLE1.C @@ -0,0 +1,87 @@ +/* + Example1.C version 1.5 + by Robert Schmidt of Ztiff Zox Softwear 1993 + + Example of making use of a TWEAK file by loading it directly at + run-time. This program needs the file(s) created by TWEAK + available at run-time. +*/ + +#include +#include +#include +#include +#include "TwkUser.h" /* declares the neccessary functions and types */ + +main() + { + /* Define the pointer that should point to the loaded array of + Registers, and the int to hold its size */ + + RegisterPtr rarray; + int rsize; + + int y, lastMode; + + cprintf("This example program loads a TWEAK register file at run-time\n\r"); + cprintf("and uses this to set Mode X (320x240x256).\n\rPress any key."); + getch(); + + /* Now use the loadRegArray function declared in TwkUser.h to load the + TWEAK file. Memory is automatically allocated. Note that the + second argument is the address of the pointer defined above! + The returned value is the number of Register elements loaded. */ + + rsize = loadRegArray("320x240.256", &rarray); + + /* Save the number of the current BIOS mode, so we can restore it + later. */ + + _AH = 0x0f; + geninterrupt(0x10); + lastMode = _AL; + + /* Set mode 13h, to make sure the EGA palette set is correct for a 256 + color mode */ + + _AX = 0x13; + geninterrupt(0x10); + + /* rarray now points to the loaded array. The second argument to + outRegArray is the number if Register elements in the array. */ + + outRegArray(rarray, rsize); + + outpw(0x3c4, 0x0f02); /* Enable all 4 planes */ + + /* Fill the screen with a blend of pink and green lines, defining the + palette on the fly. */ + + outp(0x3c8, 0); /* start with color 0 */ + for (y = 0; y<240; y++) + { + outp(0x3c9, y>>2); /* red component */ + outp(0x3c9, (256-y) >> 2); /* green component */ + outp(0x3c9, y>>2); /* blue component */ + memset((char*)MK_FP(0xa000,0) + y*80, y, 80); + } + + /* The mode is now set, so wait for the user to press a key... + Nothing much interesting to look at, I'm afraid. */ + + getch(); + + /* Restore the saved mode number. Borland's textmode() won't work, as the + C library still thinks we're in the mode it detected at startup. + The palette will be set to the BIOS mode's default. */ + + _AX = lastMode; + geninterrupt(0x10); + + /* Free the Register array allocated in loadRegArray. *You* are + responsible for doing this! */ + + free(rarray); + + return 0; + } diff --git a/16/tweak16/EXAMPLE1.EXE b/16/tweak16/EXAMPLE1.EXE new file mode 100755 index 0000000000000000000000000000000000000000..60c4f59eca2a695c2a19b881be9cf99398421995 GIT binary patch literal 14032 zcmeHue|%F_w(maYBqt$B(*U(7azhXaYOyl(PE`W6fChhzC4i<>q*9?^6ojCWoc<1^G5EiJZar!%yjt5EzXf|=nn0HWW^CUtw+LBIt-Ki~{N0(=fQ0r(hj6!15|5x}1ThXIEGEr34)Vt^>13Gh1L zw}4jxy8yogyaf0c!1I6xz&60MfFNKq;3up00%U`X3Vb|1N>%y=-ncdj}hx-8D_jWr=8?MH>5F*+LrlXGqvyL&CW`i1Z+{ zyM{EjJ`FP8{Z|YGmN+Wy54UVyS}OB;+GilQ?4&;4};fsvilj5bF{G~dT(*p zv`2cs8fxqjzZ#B#NQ>GnuO+vU-@(2++i>6yhMd19&+iKrq}Z&$;$XoR!ubko48ek0 zV)xw|V^+M)lCEjKo1*JQdx}NL5xx6uhE`1~d}Rl@8%*xOi-}?qRAVTWOq6s@4rkYs zur)+XErKOhh&jK#i8$L0Oy1Wj?{}^@fW7o4QSz$+PXej{8v##{omQAR&+}HPjZu-k z#qZ2k(LW%Mly-KCXQDrexOH9A4p>R^EhNq{_89qb*R-&GC8WKI#B}P*BX}tzF}?b- z1~26##;Y&u@lruzWJbdWjeX4m(=}~s8%WG}FMB1XFx4K@q46-Tj`S}GEbizdC*%do)IsJZj

h^1Ds$Yy@uZ#4G^73SkYd7=a3onr2J+LY)^ z91Zo6&|fX)_wjZtaXfU4gc3S2e!xMB^OU@S?i1ZT-5+*; z`PIrq8%qRUY!^T3mJ@9{A{f%t9w}Y*fsrK6Cpv(@ypY!;f4$PWJb1}gZ4;07p6ER} za4dMx)+?KPJA-lC3wbTQCp!&R-u(U+OQJW?9cp7j-9)~HYpd4Pw-Q?)QVc}onjKspT$L<&E;Ma z`{j(pC!y5rx_Adai&KLu2%tSm*_^-?(J*uSj4CC!SRsS2pDVL)QBW`E~FBU;Pj4)BGtoKMC zr(RywxilidaH?XCoa&WJxX#GOkay@*rmNe}y4uEBQ0I}v)T+({dg8LC*y`KFW8J4Z(1#H5U~?8poEDF^Z}l-s`b}TSct#smgtrEn z1+<^<@Gc+o65X`nR0)K_*E=^c%Hp89O{Ud#!9qs$9))zZwY~P=%eV?Fx+am1}OCqg*vpshLh38J_o}ZajICCErK>e9t z5N~mZ`z#?H?lT_zIZcRsZ}9;|nbUIa_lfR%9%;+preB;YI^)k_;XzFGN~C16{Q&YueA6zimZHy7EcCiFXjl` zHt$6_8d{h7RMw%*@upt>HEq2=;ZCu{eheW>$gN|8m)YtG=9Z^< z=sf6!-Ggu96jXwjb^edS?t#>M@iO{S{lS|$#XS&zKzU)-?3d7~=9)Lzt?of{%jWLx z6XFpVp%Yvy;~tF9QTzVeR`-CpMR;>;+dw>90S{ZeT&XWg5e6guCSIbvWt2^CnETDcjyMwY!HH)M^zkFJ2rD@R*d12>N{SD!kU}w%5Lm<(gpb z@moW+1H^C1Z`TvCL(T$6-7-&hairrVPsBasSuXVtXJdB`n0vNx@e3rbP<|k|y|!5_ z)#WRR7`72pSO^KKT5^BjV1UXI`3d|kRVdCz@YKR9Io{;cH5ODImrIp%zQWFKSghQ*7W9eP6I)}$Ed zZ-fg{n{1jPH4oFB?@t74&v>?QQgql5syz**#L*;kqWi37{Vn8=hF=@LHS9M`HO?|V zZhX=hF!mXKW!z${H~!417+)W^WL(v_e$y;7{r6`>j{zoZSCWI1<<;GrIPKZ3a1U{< z@Otj$TCt(B8QrQ@9X(P)XIO9Xt`soC?v!0D(w%w;C)|4hKIuwSo5X{6V^j8XgO@|K zDdN|ie@%8Z_i+s^4aZ$=!uX*xM-Kaj@uzzDwc(TB%2UTw{QIzY^h&eX_PgPepCzYi z(=lnBjnv(0cMlWkvkaBLbSz`Pu~(wyWc*`tsMMsmP0om6n|nA)ZZ;6{XlR(P$yM#y z@{Fjp$siRla$wg54BzEWZP}m{rR4SMD`q3FQrt;-#jeX}#m3GJ6>xB1W=5QY9JB&v z3QArGO-~kjq`#)H!MD2yRZmR%G9}w1-c%%zjIwVLsgFeLYMN)+e`2Y2rO-^6a_@7yu+VPZQ&jHkg&7q}W~r^C8OR94sUwx<)=2Zu29V#^{ZliOq zLD1#3$QIO7FWmnrw)U!4BZ*FU!zLL>q)pc!C2bGdmmWZPa;zknB*M60GE*q&vdK@* zLyBS^=fB1iBa^#q^Cn{hI=7NklsRDFyKF1uMs|WndP*_1tN_D;XUWw9+f+DpRa-Pu+N5}-EK(9R zLh5Uk;OBMQoR_$5STK4dBj(vN!~yGGWt%g}&EO2L_v?W+D#BqU% z^if!Cp%25T53%R6+FU5;ny!(}YGmfz^(;xX>={-Y41yy@`kPNH)X&hv!`YL9?pUP5 z^fBUy>`7_3s31);7bCG(7+nXi!1HM$doFT&E^yd^6NMmcd-rx*djYKx#0l$iqmJ&lli<1Ld<56v(OdGmt z9bqLnJ6hVDudoCb!w&!Wnns={jdmS)^2FJI0w#7>X5;ZTjF%3yEqC`_nb;cB8hU>@ z)OaMH;^#M@YeTkc4gbt z##Y|GT*Mrb_r9wmVge4x`Pabm)`phC#+HVog^fq^6u1W;)L$aD0C#}cx<8};&c8;3 zzkscwMNe!Lkv@*fy(&+uG<=zgiwZHphR+>cPIr$&MtG=VmU&giG)_ZQm=-aV;-1Xh zSMJM196pzdUbrJI^FmeTb4O$j%A%DJ*I}Qv#vt~Bn>Mp*dL_882Qv7DI9mvuv1v)u~G#b~6ELR8ra~O%d7DUFX z&mdaE$nR~1Z^4Uho%H)}eGbtI;`X19RQ=nxH5po%Dy>jd!%1TlWLfAo4V^LW-cIs* z_Uok1Z#Z70+Q_+e6TN(BD06dWogUjOU~EH~SjY~=GqA{Oy*t);iW342rU4n~F` z{pefYe_Uan!f7tqzpZHn0}+!CyNANwK_!q<0!isFFyX>)MFa&n`oCD!7Az=)KVWL- z@z}LMC&QQVlRyc0~TqJg*fQBd<#@2r=yViDN~eyO$k_wz0%zS%a9gINxxv> zn{=OG+*Y?MV5y}?x9U03?2+oReUIv%AEF9+gBK}1N}N(H{4c25-}9QHcShir(wu>n z2Kbgxtr0$-*edfh)ZcY>Rp-cjp;P*(xog@>+JJPJW&jQ?f?l3Zv{)LC0SVJpzBW2h zs*zUi$TG1br(N{gP?F9vX-O;>KMdEVI^0QyxB|81@T#*OEL0VAQi8_EP)pHmaq*09)TKb642eO2G;tuUR-hM1 zQ+^NS0#MdyzMnK7C`tLjQ0)bTVVGr-`maMCX_bNz871cc)Yf#Uly{1^hTJ?$BU<5~ zfRak%{TQjP$j9(zfj&-3T%^c2)`4td#f~Ldn^zIssk7_5IL2*R$c>(ja!u5&fh zZujbHrnmySx=Dz;CYqJnO!GjkIaI47wIeg$KeLOZ#|)2qE~5_H&&6jm!CD=Is+mm6ZArOJDYr4@=7Y6X9+f-bjGLka5x+(K z%d3Bl>R;3srW;@qhLT7oA@j3ZL7j#+whJu->+9h$SXw(JCb^XFcGWmsA%m_)${@Z| z8_)=2mDSzgI69;&BYJG?h{jIhN*QEV{+$u+O^u95Lr*h^KcPel5C^TZ!V`~Fnj%G( zNPv%cjnaYhbaPm!qDSw=IoRk%-qfd>MILUy!Z2ZFy-r)d1CBB?FEJcr{+T?zRVa|h&J4Q(1VgDggd2|v2>$W z99~y`ift&R=C_iOuRT?O!a`9m z$^;h%rd@M-Mi$73b15CaQ?etg>!zJFuZDIt(ym;5Nk@#lz&jJ(ZJnvy3*VNHx3 zA%!I$B{lq&N@@s43?)S!DPc9dR?Pt#%e0$fQk)FRZp7L8XAuXJ7snG7clw-Jka`(O zjq%{&ixleUyfc~=yKlA>7l`J`bLJT4BQG6+=@gyY4IC(-@wfvE#`i8Lg|J48%!9F z@dAT^)PiJs!A+dlu{X&04OHCH=`WDEQvB0H1+zF-Fe$hXl0N(*ZeS7}L82x|IN*VT zOu6WUJCM2a$R8)#`-x!JCQRM_1&WA7HL|^bCdJU7J;NpPRaz@`tfp(NwejD>qaM+* zeTWoz+H3PVP@uhD94INlUfc`D)9e329AFp}rq57Fh6C;}HY^5A@u~)}II;=NNS72# zCsN2DGDMh4Cn;Q`4s9aEP471J=o&%~v$FXXpm0!YVx!)+_+kA?Wzc+Nnbx0royb)% z51EgMpLU-Lzepgd(cKGgsENUCQQ{!dsir12aZpG6Y!iWF$nWpJuE=CM7@bco@ni@K zp4SW|mO+AIX$q8}l<>Z&X?^DNE9PW(9dYrje#_KQK^-BRuNLifM7@69dZ$i&aiLCA zGufz_8wHnI)J@mqXOCqVJoeZx)XSPZSY%t8E;Tat7%p)%JT(QjYscCUl9Q;rR<-Xo)N6^6sm9bShm44iuemX5a;8Pd8*ddWbjb@5wlj4 zZWgR*Dmb;c_}8gjO$KB*HFKb?BX5-+MwqKDR64pbA|gni1-NF&m9NvH$J)2;9%W}qq>f-t{9O#Pmi-iLS4sqXqW#=K3Xev z<6b<8X{RsvMtafutw^gG5q(g%GQLrX-=q#hG;kf8os^~D0!4A=EatJca+Wq7bPK2h zfO5@M#t>C%tWKrIg7#Ojv!O=xkmNe3S}=8%_+PM||F7fy>a!mn??=c-Y2yu&I8r*# zP?D-{E|VA2vSQfcfHscqkrCNXQa4JZHA>`3-&++A<^#`DT@)_-n0X=0Noq`lp&5QR@8aR&nN%0=`V;Xcf{>|jK1+NVIP$trsV5=shOzel3dN`A z@TlpXPv;Et@_qC|zn8stCNM<^D+eezLV$WsVBeTms54#?!KH2 z6GMH4{u3a!(tw+!%lllzepY@#zD~tS9J{u~vs6Q>r%39!>VJ+Cnq8SQ{Gw)BH?~_`7JWNlMTe5SzpWll<^xo_{j#u*;%22t5KVQ z+DgXHckoxEmXe_cB%6*^yA{XesX}KZRDDtXL}WKIp++VEwOJpZE-6tvu4m6XI~F6e zr+o+mXBM6*V!taMDuyPkHV*_I?%>zrbIcC@QKo$+jK0}z@lW%D)=s%3?1f)uGPgqG z?@&~_OIT#MaeIpwtd-~mNzLKCLcWF%DU4rFy;oyiOWG}{Khuc2cBC|1_zWw(;&VQM zX-%(qHC^Os_`)l_>PBJW728D*Ozu-E{gLKEKaS?KKG4>$aS9mYpAm|neH?+Az%N0_ z9rj)T4}{~gUnv?oRC+;iUr_IxF3mGh>z%~6OBrx0QHr=PIky>5-u|3V5xvR0<2gq{ z$BFs)<~#Ap!cdU-=BX`#WL{5BKfbr|W^0Ez<&FrqU6`QyWYj5K3Z^+=dKc}{peD3J zwL=7Z;VI?2M8tM;OW=Ah;xQjSE5KwNqvWh0C+r6$t~IBf-W6I#&+^d?0UJ3a&_TTV=F3np^0g#vyY? zvlLef#(Zyb5bDMRqN+_#`zqEyCOCd{`|Uq+j5OX;DQw6kcUA-{)|NZUeZDGRhH1g0 zl~ultWg8rud{ygxWg8trxo=}dWtmV>RheNLA^+b$|A36ZnBN1BRa865pDNq9X+!xa z=?zt7YpWe)jt7eGT5zAkSH8ZY8r&S~Du7caIDG!fn}v#v<)#cmr{b?JuXYHOj!@;O zE*Bj4S7F#I95>|6nf=t9e+K+G|HfQXhR0W44XTw-JDwpNfZB;k&s} zAY>f9M;!C3#Ia#w@n_8Mr+8)I7mxk@0(Fa!U>N(`hq{HVZfq5K=ewl7)Ao;-?@J(y zFsoVo)9qq+eZTE{?}dtjnu#o{)AL57G3zS*L~FKwJZryk)(!NhKJ@wY0sj;58sOJ}-vE9K z*bCSP_#NPNz`p~25BT4JKLP#%I0?7_xCj^kBmjeeOMoH3FdzxI3`hZHle?%jbId09 zR0hg6RIGKZ^H;8+Cd^Uk-}q>`j}*a#_}4t9*&1N3t?-qv5wP)zr%ZTEmB_j(f8|>8 zKvk7vBQ+*fo60Ly^lIXvCb7Djl3QC|Sy8^0EGz>HYPQnk?@t>MUwLJjL-3VVKL(^C zh`GG7%D?`xw2>JdUE1b63X}7MqipS3YQaVu%PRvFzN*TN<(0x{owjnLuVri2P@A^~ z2641*ZJAI;M(4S^0m~4`Y^~qxnqsrhhYk1L_h~xUAD0tvr~IP zSg?uZ>DiBnw9L2OuMTQ~Z#~qfS^&)|$DBK(s*Tx+ z_fvt75?fYY?cbo0+JMS(;#NF~je=%$e#x!VcquG-6wXJLrG>zAJ(M3)YTC;Q#;t literal 0 HcmV?d00001 diff --git a/16/tweak16/EXAMPLE2.C b/16/tweak16/EXAMPLE2.C new file mode 100755 index 00000000..ff3d3274 --- /dev/null +++ b/16/tweak16/EXAMPLE2.C @@ -0,0 +1,81 @@ +/* + Example2.C version 1.0 + by Robert Schmidt of Ztiff Zox Softwear 1993 + + Example of making use of a TWEAK file by linking its contents in + with the program. This program doesn't need any external files at + run time. +*/ + +#include +#include +#include +#include +#include "TwkUser.h" + +/* The following included file defines the Mode320x240 table of Registers. + The file should be created by running + TWEAK2C 320x240.256 320x240.c Mode320x240 */ + +#include "320x240.c" + +main() + { + int y, lastMode; + + cprintf("This example program was compiled with the C version of a TWEAK\n\r"); + cprintf("register file, and so will not need the external file.\n\r"); + cprintf("The C array is now used to set Mode X (320x240x256).\n\rPress any key."); + getch(); + + /* Save the number of the current BIOS mode, so we can restore it + later. */ + + _AH = 0x0f; + geninterrupt(0x10); + lastMode = _AL; + + /* Set mode 13h, to make sure the EGA palette set is correct for a 256 + color mode */ + + _AX = 0x13; + geninterrupt(0x10); + + /* Note that no initialization is neccessary now. The Register array + is linked in as global data, and is directly accessible. Take + note of the way the number of Register elements in the array is + calculated: */ + + outRegArray(Mode320x240, sizeof(Mode320x240)/sizeof(Register)); + + outpw(0x3c4, 0x0f02); /* Enable all 4 planes */ + + /* Fill the screen with a blend of red and blue lines, defining the + palette on the fly. */ + + outp(0x3c8, 0); /* start with color 0 */ + for (y = 0; y<240; y++) + { + outp(0x3c9, y>>2); /* red component */ + outp(0x3c9, 0); /* green component */ + outp(0x3c9, (256-y) >> 2); /* blue component */ + memset((char*)MK_FP(0xa000,0) + y*80, y, 80); + } + + /* The picture is drawn, so wait for user to get tired of it. */ + + getch(); + + /* Restore the saved mode number. Borland's textmode() won't work, as the + C library still thinks we're in the mode it detected at startup. + The palette will be set to the BIOS mode's default. */ + + _AX = lastMode; + geninterrupt(0x10); + + + /* Also note that since the array is static, global data, there is + no pointer to free(), as was done in Example1.C */ + + return 0; + } diff --git a/16/tweak16/EXAMPLE2.EXE b/16/tweak16/EXAMPLE2.EXE new file mode 100755 index 0000000000000000000000000000000000000000..ab3772826575df6993d29775d056976be80d6165 GIT binary patch literal 14160 zcmeHue|!^F*7wcKWD=4z4N!|9PYALEv{+rbTa`d9R8rBkM9`FqR4Wv$mKM`VDv#2p zPj-c5psVbv$hs@w?z77J?hB7`4fRD~8xbQ8$}l1~UxlpEL}?)1t7=*XbwQJ?zwPkwZ$ zF9o~;Scr!|k$UC8@b7>Czz3)TJPKF|co&2-FTp}w@J`-PM*{X5>wyHT#6}7vd1_SAJmF^6qjp79>rC(*byT-@gwnL*KuLI zGkBXKSe=oDx|v_P_SbOYUa=?C%FCx*9|_lpy=bP>R(QeSR32mu@;;|hjN6}Eqa;OQ zoJzvtyk(Wn$2%jdbQ*!r{t1D0jX-m2G+$kt);)I8G>2q2+Mi{l(@KmbRB~IeQMl&& z#51A1q|V{j$8{-AvCZ(QOpHe0cpqL->Ucz*|z6)4Z&s1K3_MU^Mspua#|z zHK`lIS6=?WKN?nq;VsC;qF@%c$5nMzI?iCBUJjI9XDNL!_9rK7}pPtN;tCT@Gczm?t@BJ=dl zlKZ^H;u-Ox=r)O7i&$zEi)`li{YG=QP+>kQln=Cn--+h#wWfjIfy1F*68fvf{63zJ z3>*y|A)x_IjPG%f;v6NXzw1O-ch`qqAGt33%(a~ByicEX{+i4AC%;%a(8>^j7u&>- zy5xaYjtGVnwFgU=9WauC^8@Wb&~47?mcLwTT^zh^~CRYwMBCJsrWg zZF5d@&&dvhl{de?&N9$5&=qRcg}R7*BimZTHM9_0B)*&L{*3uHBK1h@!N_}4)5$+T z@5-X+r-6PE=wHk{n$^sFIoO^(c{PZvE7O_uG8~8Ysys19k z&L3bEC7fGNVv2$#V(1cK3kl{XMlKbc* zEt{MD-)t)Sc;E>8L82%(!p$(%aNI1JW!&7(lV^94od&wDZqtLM;%CcRtSLQG0!HW! zG%RK!o?ZA~=8+y&QhEk{yG}Ly{x__0IXW-mhF0)m5!Ay76UE4Sk8~{g;xixw9m5b2U_2|hx%SS z-1l0oFLunxz7DnTW3+E;q)lQ-q~(z9=@TeCeS&*tT1Nh~om2n~XPzhC;&%60LfYMD zJoq_Hh-;e5ht@v(8}a- znM0f7O}+e|wDs-*cakCg>riKWQzvhZyI8S~%N6w@H^&4oGc{w(&1-q+Jm`hp7v97v zs01%_{*S`${^Wb{GWt++;7v|(_s8#5HqW?e3p&+~f0J47zF=;Cs;ldSco0VD1lyu> zUx?3C`~GUZyWiX_yg9P1Kc1;z3|qWhX(&n(9XS0eUZT8Zlud7$0Jb;cOmCa}Te87B znA5$%dr9L`w!LL)b6?V-R;zfiurM6pF)14n^ts|yc&y_#)xC}78e{JETSImI#Ba%M z(-W~>&cKM=B2Q*=~A?aVaXFa7K?r45z{W-z#^s445>`oDsptE-+7yW-mkhz&DK zWt?dMcQZfD4eN0d#P?lkR|oN@<%)ACn%!VlWOMF5`oL{$Hn;orcEh{VImvz5Rn#9~ z#iIWB`YWCB2!qV-;YnukJ(-(I-(I{3$IldZ(j&T)uMwRvDrO`gWs(i}HO6@2k@i|t zUNEka2v>{V3+C>+(bDG$XK>C9e%*qst~xgCJx8AebHx2Ev^ry}t9vkNzj=gJwi6;boFtNlx8Viws*Il8i zbIdy0NC;bW4vauEEi%8$A+1i_>C8*Y=^+j&hi_auS+*47TmS|z$pXpXCzKuL~%^k5$Eee`;e6;B~JF4kJgP6J21v5 zpv3P^V1b}Yn)J=X(w7Y>*~dKOdiNRDebyP)0|{zoC@gfg>j{Zl6JnsR5iUqwV%Jou zX^`%G|3I+rjAtDyMF$O`y36;CyzM1mhTTcKSj3&WA1B;<0Y2dxs4bmriG-ynW!27fnr@@sk0h>HI;C?3AjEVlk(@Z=|nN!oNw+Q>%g zZne1wiS$XDI=*xyZMU&UqUA*V7}-~9QrsqI#IV6V7$r9th}C4hLph#Q8i2t$>+=lIKIy z6ZszLuSsn1P3{Y-CnkNKl*@_IvgqJULPlOb}sIFp(~lblT*{XEWFy ztbe>GMkaLHW>3Hdbgn1KsBVve@3bwEkIv5bfAoeeI;PVW9JC2@V`E0oJlbiCkuh&L z=uPW%ebBm|=+KFvlROcGG_qqn(i4iQc?ky0`zg6vV0PtCTGkp(m)0mADT9sYZ!U-AMP(!3!6jbLZXr?W}ye%9X7)x*Y zH5Pg^4Eqo}ex)|&3*4^pvRRGHoZEg%lFd6_R2vL}BS!j~PAk;Ucm*ELjwE!)BJHQQ zAxC7#OByaJ$S#?Uk=QFQbM5@EIYM@k9lzjqZ04}}IAzB#xot1f`*Yl~)~21D%r^aR z4(?JablEeFG)1{+e&^))t>;HZ_Svq?x#_~qjlGR_hJ^AM0`rl*(O!@)-?H&=wu?vO zRojgu`;~%pI}H_f(D0`)U7nIHqGNVD5D3AoK)cPSH;S-`BG2JM`?%J|UV9_Ykahq; zI0$0unAuKsIKOi{Axn9ujz{BO_F!X6s@~uXTa83E;Re5omF^*ijm=ILXpM(8Ms=;| zs&#~wVC`sWb-uz7SPVP-Bk3+M2z6emb_sm##9NH2!gTn%2!hfvp@MY3UfP`mpXrJ! z07NYv9<>BXc%;W!hyt#!kkMo#SqEue0R26Sq$RXri6`f1W6#Yf)V{!XN%T??{tSiY4^p81`g|O zBtZn4{pxV+Jh_un7JILQu-QzAwHMjaFcd`WRi%7%hyh33xv z<^w6|2&MY5B-BlOa|c@b6u*mx0zD^9Csoyf+#D!i0lI}TVsB&btr)CkqL|4OSC79> zaw_s9>CZ`df)r5XtH6(JtNlirk`(Pml@&~2Sk8;H#oPtyUi{vb?zKuj1#^LK#Vl=| z)Y!t?7mJuf;?8$DA`ZX-IsZEhdGp5R{Kn>uhw~c`=O}Ow4m4aOwg9__*t$NU|IYu8 z27dwD#%4XSQABz>Ecd8mTBX6uR9sYu*)D7rVZJ!XUTAC=zs~A&hI65nR9d`;>LWsw z9=2;pt&yAvW0%Q#+>As#Z&iXG`Nz-&_j0dnf=Y@6R$q3b?Q=2n zSt7QvNXNNa;Jlop-Mk8Z5K7JGOG?Cpp-YP2EVcnzdgT}=$B;&2Tae{y=YI|(k<*OG zSoIl1YZ&>x_3$lt(alMJ{MzRbtsrjy`B2rbzOGHv!c=LAq8d&bqae#dw`u5%ar-8c z)4iLMI=*6gk!mCB=Ei#Y(53XJ((CouUIAm1qEH{mD`p~}ClaxUhifgp{Z-hTgm*B+ zg7m|$eSf<$coL_%WdFLh1p|nfeAs;{?7g4_l1d;UeE<_Kyec9nz|sHNvesbU$M6SC zZ9Hzh|B&~y1ls7zLSKJ`;3Dgm1kuoiozJNg$PEtHg= zXW*N3ozS_hZdbrkM~`mRbE4TJ)noe})gAwcD(GGKmeQldDb@V{fvWvIuPJ(a1a2wK z8CYq6Zwb{I;q!?tGEYPOZD*Ht49yohrH`6BCvVXh;xNqs99jguJe_EF8@x*7RK%^&ER3rD@UNWWIO{ zL@WFoP?9OUA0yQjIR$- zm{hhy%}gzlUOSKMsh0mp)g+V4T2z-GA}BSfn!;$Ri>v;WC z*SXrsw|cqSiLL-wKMrx%ShG@>Ztkx$hw3;|H{^riDAz;_D-_9op4;t^&8o=LLvAB8 z&*kOn`cfDTXSR_P&+xcs=~TA;Z2Tr&u#VHAYML(Twj|xAq}!Nu^T9eRkIHA^jGLka z5x+(K<<(!K`iuJfR0B-Hr38{m$oxE{piV;@*@c#Y_2u9QEUldqlU&MoyJ{m`A%m_) zIzW7@#?a8f>QHxJ#9@}MaP-JXjz&)6N*QFA{u7Q~OAc|Qp{E9jKc+MILU<%F|1hbwpYC^v|3ZTUw>_3f*Cw zvBR=j@;jtY6)otCWd0&m1v&^tEztt3z@wDbn`IXocD9OG36gD^2C^V+5-#)PR;vEeCaVV4{dn+K@Uor5bls( z#L^90ad=(1FR>d-srj`q@-_QP6Ldfpd2JjZiy^4CWJyV3$eqYg16cpZV*BvH6q|o7 z4jU~!O|94_x78!Pp{-cx4CkdL62e?(af%Bu@$|Xk*K#_o6b&!tv}Co2`^7%`hynA7 zzd&t)z{Fw;jA7WDP&-eR(-1vVzJj-z{5rR|cL7Y*894)02=~8Ri-UUDYQt5+AxOEy zEC^-+TdHd4L!qS34|C2_`gIg%vGfz=#p~Rr@m>Vayt82y^I&plb-%NaIP2&{hZpKe z2@6HNC=*;5n0C$S8CoDC&ZSiRPRS0fuA6q!yc*ioNV~G}9mBfE#-AoCGV(TuX-b|L zh2=43h!mE5nAG4GDyd62Vkjx5sQ~WADB?{=EQ_eAcdb;{5MwbiZxv)#48t zcWIlNi_T8%X!ZTUU7ruXy5O?j&+4YZaO#Z=RT;PyCb$&?ZKT<6+}_4cCC%nObwa6y zJOmTQgI{3iAhjTwlDD4~+g}Un{01s+>GWsFTq*u3p}YeuBbXGt50XCoEN;*Zv^e`(=-3SyGYE5j^+ZI1;IH_DPA6%sM zr(P#=6}tP)2gT!Er@}A%29g@yz3_&1>F~B_U@y|Crd`ayUXJ*gT?CFHzq{|+B9m!v zbPlz|6Cf;jUQ?A=8VQP}Nl=1P!uz78^~q1Kn3L`G#KmvZubULgt0&~Ct3`V~QD48V zKgo$NoZvJylZ~3W`L#jQQcZsL*dGiYd+bN*%bFcnWLt_ZH8S=XUgBtYY6@)O=c;zm z(_cx)eq4;BQ8k=;x&&&QmpbM}Mv4-;O<8xZQ!!9e?G$S*PNmQi$t*JBnjk{4tPl{|^+^M6)(f1hw>x?@UqdFc8 zwcJZf4GS5fbB5}X2C1gTMo^grwZ}DTZ&D<&5bsf(;r}~(Z<6n^_ggZ|o@0o;XGpwM ziAPjtlp357HsqR-HpDn=L*6`jac!m+5*8_15UNTS8+KP-G zia%u5YE#XEHAMxd790OExvdE9M9Lg!>&RQB2N33J3zdp)jED$QX8~R_WXsoT(d2MO zc#Fp>O{1MuLz~kae@CY|tsljAVc+ir64Oq-;2Y{i>(?W#W<>Ns-OBiCC4RlihG<~hpK{V6{T3*SGpmrt+R7Q) zbkHrJG63b8rHmk|)LNZNtp)AB#mb3hx1_sEd!$Eh17(h?=|xbLls2lIjFsV)i|eOFD}FIm z=S}X*nJ_WbSLizdVoMEplXQ8fYtYZgo8@a&oPi_PG<)vRkQykG%2&hBaY8dovj$(# zOly3Gf|HL1e^xPIqi3+@V*1S?g{kKol1hC*^)|morZ;9F{`7`A-T@D@+ z{)E~z)LIxn-_HLDwUi7sAeod`?X5T_PZc_2K-Cx3PegVj9cp9(P@8q^bV-TYaTRmk z*v`vH2H@hwV$zIUfDwl-4@XJi* z7HIr!ib{7OgA6y`-r@mkC3-Uk3@f$b zGe3rDO|5thUF6C5!Yj4vMq%s~+eHsd_BfUPP;>UMmxa4AT9v(=VBBBwj658vB(GquBUz#I|I$(RYQG;j?^rgTQOh zzTTK@kLIHmK~?JOjdafyZN>W>9No>whU0*DkW>E$F@QN01GJngDJh~c06u#9gnHP+ z@q;~ffq1r-r4ew+*<-VGBOYq5JZya|ES4QLM`SMHjuEw{!upv$R z*cg-kRnvZU7de}AG^crk`*Kcy1mBIphqy3wZ+f4_r!r@;H>0HI!r2(vCgSCFt08h? z&vbJB56Pm-p*BxJLz3L(|BE^*_J601YThv0Ow%ED*XXlNe`C)?$<%tv(Qr+~ojjXD zM6fugnH4N^T3BJioK{x2N}h;Up?E80v^biYS@19l88VuUxKc2l#b-FQnwkLkvQ|k% z-W>Y_DH&MUTE?l|Y?Zdr)VLN;eL55@@CcVo*rnKgYUmNu1ye51)`fW400D`8TBPtE z@orsr4Xt9}wL_Pwnx&$M*O0Ys;)rJv@}ElJ($-b@Hpko|OwcT)Jr={7lsjl&>_$~2 z-^E`7e8_`#6-TQ>s7az?e12)b&L5`px4)xxWYi>XkXFbG#4_e38Qk_+F(AF%rT z4_IE`%-ZHQvt!A@njrht}Rn%a@j+H>4;h+MnsYb8LN=H?-;HWAG4cfi@2_RKL zNE9y{9q(0Xmic^TYaL*ss=C(Uuc64*j+%18ad$NYyu>j*XXZ^$%={7H$GO*`o5xpP zQ-e{~Ivy)un@tu}R+g^9=1ZDY3med~8>@)ZToV;P3i^G2gF<0}1FYo>lQ zW4~_3bb6^bz5cp!-g$E6!lG-PBB)nud%mojXo^z?M2DI+jQCU&-Sow;S{n>%P64?o80UQI!00l6bf0daG$OYU1C)lk~!^9Sq*Z3 +inline void swap(T &a, T &b) + { + T t(a); + a = b; + b = t; + } + +template +inline T min(T a, T b) + { + return (a +inline T max(T a, T b) + { + return (a>b) ? a : b; + } + +template +inline T absolute(T a) + { + return (a<0) ? -a : a; + } + +template +inline void sort(T &a, T &b) + { + if (a>b) + swap(a, b); + } + +#endif \ No newline at end of file diff --git a/16/tweak16/MISC/CHIPTECH.TXT b/16/tweak16/MISC/CHIPTECH.TXT new file mode 100755 index 00000000..6e673055 --- /dev/null +++ b/16/tweak16/MISC/CHIPTECH.TXT @@ -0,0 +1,1135 @@ + Chips and Technologies Super VGA Chip Sets: + + + 82c450 + 82c451 256k DRAM max 800x600 16col + 82c452 1M DRAM max 640x480 256col, 1024x768 16col + 82c453 1M VRAM max 800x600 256 col + 82c455 256k DRAM Flat Panel version + 82c456 256k DRAM do + 82c457 do. Full color. + F65520 1M D/VRAM do. Full color. max 1280x1024 16 col & 800x600 256 col + F65530 1M D/VRAM do. Full color. max 1280x1024 16 col & 800x600 256 col + Supports Local Bus. + + + 94h (R/W): Setup Control Register for Microchannel boards + bit 0-2 Reserved + 3 Enables Adapter VGA if set + 4 Enters Setup Mode if set + 5-7 Reserved + Note: This is the same register as 46E8h. + + 100h (R): Microchannel ID low + bit 0-7 Bit 0-7 of Microchannel Card ID + + 101h (R): Microchannel ID high + bit 0-7 Bit 8-15 of Microchannel Card ID + + 102h (R/W): Global Enable + bit 0 VGA is enabled if set. + + 103h (R/W): Multiple Enable + bit 0-3 Multiple VGA Enable + 4 Must be 0 for propper operation of 82c455/6/7. + 6 Extension registers at 3B6h/7h if set, + 3D6h/7h if not. + 7 Extension Registers Access Enable. + VGA Extension registers at 3d7h can only be + accessed if this bit is set. + Note: This register only available in Setup Mode. + + 104h (R): Global ID (Setup) (Only in Setup Mode) + bit 0-7 Chip I/D. 0A5h if Chips and Tech Chip set. + + 3C3h (R/W): Setup Control PS/2 + bit 0 Enables motherboard VGA if set + 4 Enters Setup mode if set + + 3d4h index 22h (R/W): CPU Data Latch or Color Compare from last read + + 3d4h index 24h (R/W): Attribute Controller flip/flop + + 3d6h index 0 (R): Chip Version + bit 0-3 Revision number + 4-7 Chipcode: + 0: 451 1:452 2:455 3:453 5:456 6:457 + 7: 65520, 8:65530 + + 3d6h index 1 (R): DIP Switch Register + bit 0-6 State of the DIP switches. + 0-7 (655x0) Read from Memory Address bus A on Reset. + Bit 0-1: CPU Bus type + 0=PI bus, 1=MC bus, 2=Local bus (65530 only), 3=ISA bus. + 2: Pixel Clock Source (OSC/) + 0: CLK0-CLK3 are pixel clock inputs. + CLK0 or CLK1 is MCLK input. + 1: CLK0 is MCLK input. + CLK1 is pixel clock input. + CLK2 is CLKSEL0 output. + CLK3 is CLKSEL1 output. + 3: Memory Clock Source (56M/) + 0: MCLK = 56.644 MHz (80ns RAM) + If bit 2 is 0: + CLK0 is 50.350 MHz + CLK1 is 56.644 MHz (MCLK source) + CLK2 is 40.000 MHz + CLK3 is 44.900 MHz + If bit 2 is 1: + MCLK (CLK0) is 56.644 MHz + Clock Select 0 is 40.000 MHz + Clock Select 1 is 50.350 MHz + Clock Select 2 is user defined + Clock Select 3 is 44.900 MHz + 1: MCLK = 50.350 MHz (100ns RAM) + If bit 2 is 0: + CLK0 is 50.350 MHz + CLK1 is 28.322 MHz (MCLK source) + CLK2 is 40.000 MHz + CLK3 is 44.900 MHz + If bit 2 is 1: + MCLK (CLK0) is 50.350 MHz + Clock Select 0 is 40.000 MHz + Clock Select 1 is 28.322 MHz + Clock Select 2 is user defined + Clock Select 3 is 44.900 MHz + 4: Transceiver Control + If set there are no external transceivers (pin 69 is + VGARD output), if clear there are external transceivers + (pin 69 is ENAVEE/ output). + + 3d6h index 2 (R/W): CPU Interface + bit 0 16bit memory enabled if set + 1 (82c451-453) 16 bit I/O if set + (82c453 Only) Fast Font Enable ??? + The byte written to memory is used as a mask + for painting foreground color to the pixels + with the corresponding bit set and background + color to the rest. + (655x0 Only) Digital Monitor Clock Mode + 0: CLK0 = 25 MHz, CLK1 = 28 MHz + 1: CLK0 = 14 MHz (56MHz /4 or 28MHz /2) + CLK1 = 16 MHz (50MHz /3) + 2 (82c451/2/3/5) Fast MCA buscycle decoding if set + 3-4 (82c453 and 455-457) Attribute port pairing + 0: Normal Attribute addressing + 1: 3C1h is both read and write, 8 and 16 bit. + 2: 3C1h is both read and write, 8 bit only. + 5 (Not 82c451/2) 10 bit I/O decoding if set, 16 bit else + 6 (82c453 Only) Pel Panning Control + (655x0 Only) If set external palette registers can be addressed + at 83C6h-83C9h. (Brooktree/Sierra type DACs). + 7 (Read Only) Attribute flip-flop status. If set the Attribute + register (3C0h) is currently in Data mode. + + 3d6h index 3 (R/W): ROM Interface (not 655x0) + bit 0 Disable on-card ROM if set. + Enable ROM at C0000h-C7FFFh if clear. + + 3d6h index 4 (R/W): Memory Mapping + bit 0-1 (82c452/3) Display Memory Size: + 0: 256Kb, 1: 512Kb, 2: 1Mb. + (655x0) Memory Configuration + 0: 2 x 256Kx4 D/VRAM 256K tot 8 bit datapath + 1: 4 x 256Kx4 D/VRAM 512K tot 16 bit datapath + 3: 2 x 512Kx8 DRAM 1M tot 16 bit datapath + 2 (82c451/5/6/7) Enable bank access if set + (82c452/3, 655x0) If set CRTC Address can cross bank boundaries. + 3 (82c457) If set DRAM timing is for 64Kx16 (4 WE, 1 CAS) + if clear for 64Kx4 (4 CAS, 1 WE). + (655x0) Enables bank addressing if set. + 4 (655x0) If set VRAM interface, else DRAM interface. + 5 (655x0) If set CPU memory write buffer is enabled. + 6 (655x0) If set enables 0WS capability. + 7 (655x0) If set allows faster 0WS cycle timing. + + 3d6h index 5h (R/W): Sequencer Control (452/3/7 only) + bit 2 (82c457) Clock Pin Polarity. + If set CLK0 is defined as a common clock and CLK1/S0 + and CLK2/S1 are select outputs. If clear one of CLK0, + CLK1 and CLK2 is selected as the display clock. + + 3d6h index 6h (R/W): DRAM Interface (82c452 only) + + 3d6h index 6h (R/W): Palette Control Register (655x0 only) + bit 0 If set enables external DAC if 3d6h index 6 bit 0 is 0. + 1 If set disables the internal DAC. + Causes the DAC to power down and tri-states the outputs. + 2 If set enables 16 bit/pixel operation. + Timing to an external DAC will be SC11486 (Tseng) compatible. + (Two bytes output per pixel, one on the rising edge of PCLK + and one on the falling edge). + 3 If set 16 bit pixels are 5 red-6 green-5 blue. + If clear they are 5 bits of each. + 4 If set the Sense Status bit (3C2h bit 4) is driven by the SENSE + pin from external logic. + 5 If set bypasses the internal RAMDAC. + This bit should always be clear. + 6-7 Color Reduction Select. + In flat panel modes these bits determine the algorithm used to + reduce 18 bit color data to 6 bits for mono panels. + 0: NTSC weighting, 1: Equivalent weight, 2: Green only, 3: Color. + + 3d6h index 8h (R/W): General Purpose Output Select B Register. (451/2/5/6/7 only) + bit 0 Select bit B for ERMIN/ pin. + 1 Select bit B for TRAP/ pin. + 2 (82c457) If set PNL14 pin outputs panel data bit 14, + if clear PNL14 pin outputs DATEN/. + + 3d6h index 9h (R/W): General Purpose Output Select A Register. (451/2/5/6/7 only) + bit 0 Select bit A for ERMIN/ pin. + 1 Select bit A for TRAP/ pin. + Select A and B determine the output on the pin: + B A Output + clear clear Normal + clear set 3-State + set clear Force low + set set Force high + + 3d6h index Ah (R/W): Cursor Address Top (82c452/3 Only) + bit 0-1 Cursor Address bit 16,17 + 2-7 Reserved + + 3d6h index Bh (R/W): CPU Paging (82c451/5/6/7 only) + bit 0-1 Bank number in 64k chunks. + Note: This Bank register is used if in a 256 color mode and + the chip is a 82c451/5/6/7. + + 3d6h index Bh (R/W): Memory Paging Register (82c452/3, 655x0 only) + bit 0 Enable extended paging (256 color paging) if set + 1 If set Dual Pages are enabled. A0000h-A7FFFh uses 3d6h + index 10h, A8000h-AFFFFh uses 3d6h index 11h. + 2 CPU Address divide by 4 (256 color addressing) + 3 (655x0) If set CPU address divide by 2 is enabled. + 4 (65530) If set Memory is mapped as 1MB linear Memory. + + 3d6h index Ch (R/W): Start Address Top (82c452/3, 655x0 Only) + bit 0-1 Display Start Address bit 16,17. + + 3d6h index Dh (R/W): Auxiliary Offset Register + bit 0 Bit 8 of Offset field. If set each line is >255 words. + 1 Bit 8 of simulated Offset field. + + 3d6h index Eh (R/W): Text Mode (82c452, 655x0 Only) + bit 0 (82c452) Extended text Mode Control ?? + 1 (82c452) Enable anti-aliased fonts if set + 2 (655x0) If set cursor is non-blinking. + 3 (655x0) If set Cursor style is Exclusive-Or. + + 3d6h index Fh (R/W): Software Flags 2 (655x0 only) + bit 0-7 Software flags. + + 3d6h index 10h (R/W): Single/Low Map (82c452/3, 655x0 Only) + bit 0-5 (82c452) Bank no in 4K/16K chunks. + 0-7 (82c453) Bank no in 1K/4K chunks. + Note: This Bank register is used if in single-paging mode + or if addressing the lower half (32 or 64Kb) of the + adapters address range. + + 3d6h index 11h (R/W): High Map (82c452/3, 655x0 Only) + bit 0-5 (82c452) Bank no in 4K/16K chunks. + 0-7 (82c453) Bank no in 1K/4K chunks. + Note: This Bank register is used if addressing the upper + half (32 or 64Kb) of the adapters address range. + + 3d6h index 14h (R/W): Emulation Mode Register + bit 0-1 Emulation Mode: + 0=VGA/EGA, 1=CGA, 2=MDA and 3=Hercules. + 2 (R) Hercules Configuration (3BFh) bit 0 Readback. + If set it is possible to set the Graphics Mode bit (3B8h bit 1). + 3 (R) Hercules Configuration (3BFh) bit 1 Readback. + If set it is possible to set the Graphics Page bit (3B8h bit 7). + 4 Display Enable Status Mode. + If set bit 0 of the Input Status Register 1 (3dAh) + shows the Hsync Status (as MDA/Hercules), if clear the + Display Enable is shown (as CGA/VGA). + 5 Vertical Retrace Status Mode. + If set bit 3 of the Input Status Register 1 (3dAh) + shows the Video signal (as MDA/Hercules), if clear the + Vertical Retrace status is shown (as CGA/VGA). + 6 Vsync Status Mode. + If clear bit 7 of the Input Status Register 1 (3dAh) + shows the Vsync Status (as MDA/Hercules). + 7 Interrupt Output Function. + If clear the IRQ pin will always 3-state, if set it + will 3-state only when interrupts are disabled. + + 3d6h index 15h (R/W): Write Protect Register. + bit 0 Write Protect Group 1 Registers. + If set the Sequencer (3C4h), Graphics Controller (3CEh) + and Attribute Controller (3C0h) registers are write protected. + 1 Write Protect Group 2 Registers. + If set the Cursor Size Register (3d4h index 9 bits 0-4) + and the Character Height registers (3d4h index 0Ah and 0Bh) + are write protected. + 2 Write Protect Group 3 Registers. + If set CRT registers (3d4h) index: 7 bit 4, 8, 11h bits 4-5, + 13h, 14h, 17h bits 0-1 and 3-7, 18h are write protected. + 3 Write Protect Group 4 Registers. + If set CRT registers (3d4h) index: 9 bits 5-7, 10h, 11h bits 0-3 + and 6-7, 12h, 15h, 16h, 17h bit 2 are write protected. + 4 Write Protect Group 5 Register. + If set the Miscellaneous Output (3C2h) and Feature Control + (3dAh) registers are write protected. + 5 Write Protect Group 6 Registers. + If set the DAC registers (3C6h-3C9h) are write protected. + 6 Write Protect Group 0 Registers. + If set CRT registers (3d4h) index: 0, 1, 2, 3, 4, 5, 6, + 7 bits 0-3 and 5-7 are write protected. + + 3d6h index 16h (R/W): Trap Enable Register. (not 655x0) + bit 0 If set accesses to registers 3B4h or 3B5h cause a Trap. + 1 If set accesses to registers 3B8h or 3BFh cause a Trap. + 2 If set accesses to registers 3C0h-3CFh cause a Trap. + 3 If set accesses to registers 3D4h or 3D5h cause a Trap. + 4 If set accesses to registers 3D8h or 3D9h cause a Trap. + 5 If set accesses to registers 3d4h index 0-0Bh and 10h-18h + cause a Trap. + + 3d6h index 17h (R/W): Trap Status Register. (not 655x0) + bit 0 If set a trap occurred due to access to registers 3B4h or 3B5h. + 1 If set a trap occurred due to access to registers 3B8h or 3BFh. + 2 If set a trap occurred due to access to registers 3C0h-3CFh. + 3 If set a trap occurred due to access to registers 3D4h or 3D5h. + 4 If set a trap occurred due to access to registers 3D8h or 3D9h. + 5 If set a trap occurred due to access to registers + 3d4h index 0-0Bh or 10h-18h. + Note: Any bits in this register can be cleared by writing a 1 bit to them. + + 3d6h index 18h (R/W): Alternate Horizontal Display Enable End Register + bit 0-7 This register replaces the Horizontal Display Enable End Register + (3d4h index 1) in low resolution CGA text and graphics modes, + Hercules Graphics and all flat panel modes. + Note: Probably doesn't exist in the 82c451/2/3. + + 3d6h index 19h (R/W): Alternate Horizontal Sync Start Register + bit 0-7 This register replaces the Horizontal Sync Start Register + (3d4h index 4) in low resolution CGA text and graphics modes, + Hercules Graphics and all flat panel modes. + Note: Probably doesn't exist in the 82c451/2/3. + + 3d6h index 1Ah (R/W): Alternate Horizontal Sync End Register + bit 0-4 Alternate Horizontal Sync End. Replaces 3d4h index 5 bits 0-4. + 5-7 Alternate Horizontal Sync Delay. + For CRTs replaces 3d4h index 5 bits 5-6. + Note: This register replaces the Horizontal Sync End Register (3d4h index 5) + in low resolution CGA text and graphics modes, Hercules Graphics and + all flat panel modes. + Note: Probably doesn't exist in the 82c451/2/3. + + 3d6h index 1Bh (R/W): Alternate Horizontal Total Register + bit 0-7 This register replaces the Horizontal Total Register + (3d4h index 0) in low resolution CGA text and graphics modes, + Hercules Graphics and all flat panel modes. + Note: Probably doesn't exist in the 82c451/2/3. + + 3d6h index 1Ch (R/W): Alternate Horizontal Blank Start Register (CRT) + bit 0-7 Alternate Horizontal Blank Start. + Note: For CRT systems this register replaces the Horizontal Blank Start + Register (3d4h index 2) in low resolution CGA text and graphics + modes and Hercules Graphics mode. + Note: Probably doesn't exist in the 82c451/2/3. + Note: This register has different meaning for CRT and Plat Panel systems. + + 3d6h index 1Ch (R/W): Alternate Horizontal Blank End Register (Flat Panel) + bit 0-7 For Flat Panel systems this value specifies the end of Horizontal + Blank in terms of character clocks. + Note: Probably doesn't exist in the 82c451/2/3. + Note: This register has different meaning for CRT and Plat Panel systems. + + 3d6h index 1Dh (R/W): Alternate Horizontal Blank End Register (CRT) + bit 0-4 Alternate Horizontal Blank End + 5-6 Alternate Display Enable Skew Control. + Note: For CRT systems this register replaces the Horizontal Blank End + Register (3d4h index 3) in low resolution CGA text and graphics + modes, and Hercules Graphics mode. + Note: Probably doesn't exist in the 82c451/2/3. + Note: This register has different meaning for CRT and Plat Panel systems. + + 3d6h index 1Dh (R/W): Alternate Horizontal Blank Start Register (Flat Panel) + bit 0-7 Alternate Horizontal Blank Start. + Note: For Flat Panel systems this register replaces the Horizontal Blank + Start Register (3d4h index 2). + Note: Probably doesn't exist in the 82c451/2/3. + Note: This register has different meaning for CRT and Plat Panel systems. + + 3d6h index 1Eh (R/W): Alternate Offset Register + bit 0-7 Alternate Offset. + Note: This register replaces the Offset Register (3d4h index 13h) in low + resolution CGA text and graphics modes and Hercules Graphics mode. + Note: Probably doesn't exist in the 82c451/2/3. + + 3d6h index 1Fh (R/W): Virtual EGA Switch Register (655x0 only) + bit 0-3 If bit 7 is 1 one of these bits is read back in the Input Status + Register 0 (3C2h bit 4) depending on Miscellaneous Output bits 2-3: + 0: bit 3, 1: bit 2, 2: bit 1, 3:bit 0. + 7 If set one of bits 0-3 is read back in the Input Status Register + (3C2h) bit 4. + + 3d6h index 20h (R/W): Sliding Unit Delay (452/3 only) + + 3d6h index 21h (R/W): Sliding Hold A (452 only) + + 3d6h index 22h (R/W): Sliding Hold B (452 only) + + 3d6h index 23h (R/W): Write Mask Control (452/3 Only) + bit 0 Enable VRAM Write Mask function if set + 1-2 Write Bit Mask Select: + 0: Write Bit Mask Pattern Register (3d6h index 24h) + 1: Graphics Controller Bit Mask (3CEh index 8) + 2: Rotated CPU byte + 3 Enable Fast Read/Modify/Write function if set + + 3d6h index 24h (R/W): Write Bit Mask Pattern (82c452/3 only) + bit 0-7 Write Bit Mask (if 3d6h index 23h bit 1-2 =0) + + 3d6h index 24h (R/W): Alternate Maximum Scanline Register (655x0 only) + bit 0-4 Number of scanlines -1 per character row of TallFont. + Note: Used in Flat Panel text modes when TallFont is enabled. + + 3d6h index 25h (R/W): FP AltGrHVirtPanel Size (453, 655x0 only) + bit 0-7 Should be: (9/8)*(3d6h index 1Ch +1) -1. + + 3d6h index 26h (R/W): Configuration (82c453 Only) + bit 0 PC/AT if set, PS/2 else + 1-2 VRAM memory + 0: 512k 16 chips of 64k x4 + 1: 512k 4 chips of 256k x4 + 2: 1M 8 chips of 256k x4 + 3: 512k 8 chips of 64k x4 ????? + maybe 256k ?? + + 3d6h index 27h (R/W): Force Sync State + + 3d6h index 28h (R/W): Video Interface + bit 0 BLANK/Display Enable Polarity. + Positive if set, Negative if clear. + 1 Blank /Display Enable Select (CRT). + If set the BLANK/ pin outputs DE, if clear BLANK/ + 2 Shut Off Video. + If set the video signal is forced to default video + (3d6h index 2bh) during the blanking interval. + 3 Shut Off Blank. + If set the BLANK/ output is forced active + during the blanking interval. + (655x0) Read/writable, but has no function. + 4 (655x0) 256 Color Video Path. + If set Video Data Path is 8 bits rather than 4 bits. + 5 (655x0) Interlace Video. CRT graphics modes only. + If set Video is interlaced. + 6 (655x0) 8-bit Video Pixel Panning. + If set 3C0h index 13h bits 0-2 are used to control + pixel panning rather than bits 1-2. + 7 (655x0) Read/writable, but has no function. + + 3d6h index 29h (R/W): External Sync Control (452 only) + + 3d6h index 2Ah (R/W): Frame Interrupt Count (452 Only) + bit 0-4 Generate Vertical Interrupt every (n+1) frames + + 3d6h index 2Bh (R/W): Default Video Register (not 453) + bit 0-7 On CRTs this is the color displayed during blank time. + + 3d6h index 2Ch (R/W): FP Vsync (FLM) Delay Register. + bit 0-7 Number of Hsync pulses between internal Vsync and the + rising edge of First Line Marker (FLM). + Note: Only used in Flat Panel modes when 3d6h index 2Fh bit 7 is 0.. + + 3d6h index 2Dh (R/W): FP Hsync (LP) Delay Register. + bit 0-7 Number of character clocks between the FP Blank inactive + edge and the rising edge of the LP. + Note: Only used in Flat Panel modes when 3d6h index 2Fh bit 6 is 0 and + graphics mode horizontal compression is disabled. + + 3d6h index 2Eh (R/W): FP Hsync (LP) Delay Register. + bit 0-7 Number of character clocks between the FP Blank inactive + edge and the rising edge of the LP. + Note: Only used in Flat Panel modes when 3d6h index 2Fh bit 6 is 0 + and 9 dot text mode is used. + + 3d6h index 2Fh (R/W): FP Hsync (LP) Width Register + bit 0-3 Width of the LP output pulse in number of character clocks. + Only in 8 dot text modes on Flat Panels. + 4 Bit 8 of the FP Hsync (LP) Delay Register (3d6h index 2Eh). + 5 Bit 8 of the FP Hsync (LP) Delay Register (3d6h index 2Dh). + 6 FP Hsync (LP) Delay Disable. + If set the FP Hsync (LP) active edge will coincide with the + FP Blank inactive edge. + 7 FP Vsync (FLM) Delay Disable. + If set the external FP Vsync (FLM) will coincide with + the internal FP Vsync (FLM) active edge. + + 3d6h index 30h (R/W): Graphics Cursor Start Address High + bit 0-7 Bit 8-15 of the Cursor Start Address. + + 3d6h index 31h (R/W): Graphics Cursor Start Address Low + bit 0-7 Lowest 8 bits of the Cursor Start address. + 3d6h index 30h and index Ah forms the upper 10 bits. + In 256 color modes this address has a granularity + of 16 bytes and 4 bytes in 16 color modes. + + 3d6h index 32h (R/W): Graphics Cursor End Address + bit 0-7 End address of the cursor bit map. + + 3d6h index 33h (R/W): Graphics Cursor X Position High + bit 0-3 Bits 8-11 of the X coordinate of the cursor. + + 3d6h index 34h (R/W): Graphics Cursor X Position Low + bit 0-7 Lower 8 bits of the X coordinate of the cursor. + + 3d6h index 35h (R/W): Graphics Cursor Y Position High + bit 0-3 Bits 8-11 of the Y coordinate of the cursor. + + 3d6h index 36h (R/W): Graphics Cursor Y Position Low + bit 0-7 Lower 8 bits of the cursor Y coordinate. + + 3d6h index 37h (R/W): Graphics Cursor Mode + bit 0 Cursor Enabled if set + 1 Cursor Status enable + 2 Horizontal Zoom. Zoom to 64 pixels wide if set. + (Normally 32 pixels wide). + 3 Cursor Blink enabled if set + 4 Cursor Blink Rate. 8 frames if clear, 16 if set + + 3d6h index 38h (R/W): Graphics Cursor Plane Mask + bit 0 Enables graphics cursor in bit plane 0 if set + 1 Enables graphics cursor in bit plane 1 if set + 2 Enables graphics cursor in bit plane 2 if set + 3 Enables graphics cursor in bit plane 3 if set + + 3d6h index 39h (R/W): Graphics Cursor Color 0 + bit 0-7 Background color of Graphics Cursor. + + 3d6h index 3Ah (R/W): Graphics Cursor Color 1 + bit 0-7 Foreground color of Graphics Cursor. + + 3d6h index 44h (R/W): Scratch #0 Register (82c453, 655x0 Only) + bit 0-7 Available + + 3d6h index 45h (R/W): Scratch #1/Foreground Color (82c453 Only) + bit 0-7 Used as foreground color if in Fast Font Paint mode, + Available as scratch else. + + 3d6h index 50h (R/W): Panel Format (82c455/6/7 Only) + bit 0-1 Frame Rate Control + 0: No gray scale simulated for mono, + 8 colors simulated for color panels. + 1: 4 simulated colors for color panels only + (64 colors displayed). + 2: (82c455/6) 64 gray levels simulated for mono. panels only. + (82c457) 16 levels simulated for each color output. + 4096 colors simulated. + 3: (82c457) 3 levels simulated for each color output. + 27 colors simulated. + 2-3 Pulse Width Modulation + 0: No gray scales for mono or color systems. + 1: 4 colors supported by the color panels only + (64 colors displayed). + 2: 16 gray levels supported by the mono panels only. + 3: 256 gray levels supported by the + color single panels only. + (655x0) Dither Enable. + 0: Disable Dither. + 1: Enable dither for 256 color modes. + 2: Enable dither for all modes. + 4-5 Clock Divide (CD). + 0: Shift Clock = Dot Clock + 1: Shift Clock = Dot Clock/2 + 2: Shift Clock = Dot Clock/4 + 3: (655x0) Shift Clock = Dot Clock/8. + 7 Shift Clock Mask. + If set the Shift Clock stops outside the + Display Enable interval. + 6-7 (655x0) VAM/FRC Control + 0: bit 2-3 determine the dither: + 0: 6 bpp VAM (dither bits 0-1). + 1: 4 bpp VAM (dither bits 0-1). + 2: 2 bpp VAM (dither bits 2-3). + 3: 1 bpp VAM (dither bits 4-5). + 1: 3 Bits/Pixel VAM (dither bits 1-2). + Use with bit 2-3=0 or 1 for mono panels, + Use with bit 2-3=0 for color panels. + 2: (65530) 2-Frame FRC + 3 level gray scale simulation without dither or + 9 level gray scale simulation with dither. + 3: (65530) 3 Bits/Pixel VAM + 2-Frame FRC. + 15-level gray scale simulation without dithering and + 56 level gray scale simulation with dithering. + + + 3d6h index 51h (R/W): Panel Type (82c455/6/7, 655x0 Only) + bit 0 (82c455/6) Double drive if set, single else + 1 Double panel if set, single else + 2-3 Type of display + 0=LCD, 1=CRT, 2=Plasma or Electrolum. + 2 (655x0) Display Type. 0=CRT, 1=Flat Panel. + 3 (655x0) 8/16 bit FP Video Interface. + If set the Flat Panel Video interface is 16 bit. + 4-5 0=Color panel 3 bit data pack + 1=Color Panel 1 bit data pack + 2=(82c455/6) Monochrome Panel + 3=(82c457) Extended 4-bit pack + 4 (655x0) Video Skew. + If set Video data is delayed 1 shift clock cycle. + 5 (655x0) Shift Clock Mask (SM). Flat Panel mode only. + If set the shift clock is forced low outside the display + interval. If clear it also toggles outside the interval. + 6 Flat Panel Compatibility enabled if set + 7 Text Video output polarity + + 3d6h index 52h (R/W): Panel Size (82c455/6/7 Only) + bit 0-1 Horizontal Size of panel + 1=640 pixels, 2=720 pixels + 3-6 Vertical Size of panel + 1=200 lines, 2=350, 4=400, 8=480 lines + + 3d6h index 52h (R/W): Power Down Control Register. (655x0 only) + bit 0-2 FP Normal Refresh Count. Flat Panel modes only. + Number of memory refresh cycles to perform per scanline. + 3 Panel Off Mode. If set the CRT/FP interface is inactive. + 4 Panel Off Control Bit 0. Only effective if bit 3 is set. + If set the Video data, CRT and Flat Panel timing signals + are forced inactive, rather than only the Video data. + 5 Panel Off Control bit 1. Only effective if bit 3 is set. + If set inactive video data and/or timing pins are tri-stated + rather than being driven. + 6 Standby Control. Only effective if the STNDBY/ is low. + In standby mode the video output, timings and CPU interface + are inactive. If set set the Display memory refresh is derived + from the 32kHz input. If clear the DRAMs are self-refreshed. + 7 CRT Mode Panel Off. Only effective in CRT modes. + If set Video data and timing signals are tri-stated. + + 3d6h index 53h (R/W): Override Register (82c455/6/7, 655x0 Only) + bit 0 Disable AR10D2. If set the ninth pixel of characters is + controlled by this register, if clear it is controlled + by the Mode Control Register (3C0h index 10h) bit 2. + 1 Alternate Line Graphics Character Code. + Only effective if bit 0 is set. + If set the ninth pixel of a character is forced to the same value + as the 8th pixel. If clear it is forced to the background color. + 2 (655x0) FRC option 1. + 3 (655x0) FRC option 2. + 4-5 (65530) Pixel Packing. Only effective for Color STN panels. + 0: 3-bit Pack. 3d6h index 50h bits 4-5 can be 0,1 or 2. + 1: 4-bit Pack. 3d6h index 50h bits 4-5 can be 1 or 1. + 3: Extended 4-bit Pack. 3d6h index 50h bits 4-5 must be 1. + 7 (65530) High Color Mode Flat Panel Operation. + If set Hi-Color operation is enabled in hi-res modes on + Flat panel. If clear it is enabled in low-res modes. + + + 3d6h index 54h (R/W): Alternate Miscellaneous Output Register (82c455/6/7 Only) + bit 0 Panel Video Skew + 2-3 Clock Select Bits + 6 Hsync. Negative if set, Positive if clear. + 7 Vsync. Negative if set, Positive if clear. + Note: For Flat Panel systems this register replaces the Miscellaneous + Output Register (3C2h). + + 3d6h index 54h (R/W): FP Interface Register (655x0 Only) + bit 0 FP Blank Polarity. + If set the BLANK/ pin has negative polarity. + 1 If set the BLANK/ pin outputs only the FP Horizontal Blank + signal, if clear it outputs both Vertical and Horizontal + Blank signals. + 2-3 FP Clock Select Bits 0-1. + In Flat Panel modes these bits replace 3C2h bits 2-3. + 4-5 FP Feature Control bits 0-1. + In Flat Panel modes these bits replace 3dAh bits 0-1. + 6 FP HSync (LP) Polarity. + If set the HSync (LP) pin has negative polarity. + 7 FP VSync (FLM) Polarity. + If set the Vsync (FLM) pin has negative polarity. + Note: This register is only effective in Flat Panel modes. + + 3d6h index 55h (R/W): Text Mode 350_A (82c455/6/7 Only) + bit 0-3 (Number of blank lines)-1 inserted between text rows + I.e. if 5, insert 6 blank lines after a text line. + 4 If clear lines are inserted. + Note: This register is used if in a 350 line text mode + and fonts are larger than 8 lines. + + 3d6h index 55h (R/W): Horizontal Compensation Register (655x0 Only) + bit 0 Enable Horizontal Compensation (EHCP) + If set Horizontal compensation is enabled. + 1 Enable Automatic Horizontal Centring (EAHC) + If set (and bit 0 is set) EAHC is enabled. + Horizontal left and right borders will be computed + automatically. + 2 Enable Text Mode Horizontal Compression (ETHC). + If set, bit 0 is set and we are in a Flat Panel Text + mode ETHC is enabled. + 9-dot text modes will be forced to 8-bit. + 5 Enable Automatic Horizontal Doubling (EAHD). + If set and bit 0 is set, EAHD is enabled. + If Horizontal Display Width (3d4h index 1) is less + than or equal to half the Horizontal Panel Size + (3d6h index 18h) horizontal pixel doubling will be forced. + 6 Alternate CRT Hsync Polarity. + Negative if set, Positive if clear. + 7 Alternate CRT Vsync Polarity. + Negative if set, Positive if clear. + + 3d6h index 56h (R/W): Text Mode 350_B (82c455/6/7 Only) + bit 0-3 (Number of blank lines)-1 inserted between text rows + 4 If clear lines are inserted. + Note: This register is used if in a 350 line text mode + and fonts are smaller than or equal to 8 lines. + + 3d6h index 56h (R/W): Horizontal Centring Register (655x0 Only) + bit 0-7 Horizontal Left Border. + Size of the left border in pixels -1. + Only used if in a Flat Panel mode and non-automatic + horizontal centring is enabled. + + 3d6h index 57h (R/W): Text Mode 400 (82c455/6/7 Only) + bit 0-3 (Number of blank lines)-1 inserted between text rows + 4 If clear lines are inserted. + Note: This register is used if in a 400 line text mode. + + 3d6h index 57h (R/W): Vertical Compensation Register (655x0 Only) + bit 0 Enable Vertical Compensation if set. + 1 Enable Automatic Vertical Centring. + If set and bit 0 set, the image will automatically + be centred vertically. + 2 Enable Text Mode Vertical Stretching. + If set and bit 0 set, text mode vertical + stretching is enabled. + 3-4 Text Mode Vertical Stretching. If bit 0 & 2 set. + 0 = Double Scanning (DS) and Line Insertion (LI) + with priority: DS+li, DS, LI. + 1 = Double Scanning (DS) and Line Insertion (LI) + with priority: DS+LI, LI, DS. + 2 = Double Scanning (DS) and TallFont (TF) + with priority: DS+TF, DS, TF. + 3 = Double Scanning (DS) and TallFont (TF) + with priority: DS+TF, TF, DS. + 5 Enable Vertical Stretching if set and bit 0 set. + 6 Vertical Stretching.If bits 0 and 5 set. + 0 = Double Scanning (DS) and Line Replication (LR) + with priority: DS+LR, DS, LR. + 1 = Double Scanning (DS) and Line Replication (LR) + with priority: DS+LR, LR, DS. + + 3d6h index 58h (R/W): Graphics Mode 350 (82c455/6/7 Only) + bit 0-3 Number of scan lines between stretch/delete + 4 Enable vertical Stretching if set + 5 Enable vertical deletion if set + 6 If set the value in bits 0-3 is incremented every other period. + Note: This register is used if in a 350 line graphics mode. + + 3d6h index 58h (R/W): Vertical Centring Register (655x0 Only) + bit 0-7 Vertical Top Border LSBs. + Lower 8 bits of the Vertical Top Border. + Bits 8-9 are in 3d6h index 59h bits 5-6. + Note: used only in Flat panel modes when non-automatic + vertical centring is enabled. + + 3d6h index 59h (R/W): Graphics Mode 400 (82c455/6/7 Only) + bit 0-3 Number of scan lines between stretch/delete + 4 Enable vertical Stretching if set + 5 Enable vertical deletion if set + 6 If set the value in bits 0-3 is incremented every other period. + Note: This register is used if in a 400 line graphics mode. + + 3d6h index 59h (R/W): Vertical Line Insertion Register (655x0 Only) + bit 0-3 Vertical line Insertion Height. + Number of lines -1 to insert between text rows. + 5-6 Bits 8-9 of the Vertical Top Border (3d6h index 58h). + Note: This register is only used in Flat Panel text modes. + + 3d6h index 5Ah (R/W): Flat Panel Vertical Display Start_400 (82c455/6/7 Only) + bit 0-7 For 400 line Flat Panel modes these are the lower 8 bits of the + Vertical Display Start (in scanlines). The upper 2 bits are in the + Flat Panel Vertical Overflow 2 Register (3d6h index 6Bh) bits 2-3. + + 3d6h index 5Ah (R/W): Vertical Line Replication Register. (655x0 Only) + bit 0-3 Vertical line Replication Height. + Number of lines-1 between replicated lines. + Double scanned lines are also counted. + Note: This register is only used when in Flat Panel text modes + and Line Replication is enabled. + + 3d6h index 5Bh (R/W): Flat Panel Vertical Display End_400 (82c455/6/7 Only) + bit 0-7 For 400 line Flat Panel modes these are the lower 8 bits of the + Vertical Display End (in scanlines). The upper 2 bits are in the + Flat Panel Vertical Overflow 2 Register (3d6h index 6Bh) bits 6-7. + + 3d6h index 5Bh (R/W): Panel Power Sequencing Delay register (65530 Only) + bit 0-3 Panel Power Down sequencing Delay in 32ms counts. (0-480ms) + 4-7 Panel Power Up Sequencing Delay in 4ms counts. (0-60ms) + Note: This register is used only when the Panel power Sequencing + feature is enabled. Default to 81h for compatibility with 65520. + + 3d6h index 5Ch (R/W): Weight Clock Control Register A (82c455/6 only) + bit 0-5 This register is used in Flat Panel mode when bit 7 of the Panel + Format Register (3d6h index 50h) is set and bits 2-3 of the same + register is either 1 or 2. + The time from Hsync to the first pulse on the WGTCLK is this + value*4 dot clocks. See also 3d6h index 5Dh and 6Ch. + + 3d6h index 5Dh (R/W): Weight Clock Control Register B (82c455/6 only) + bit 0-5 This register is used in Flat Panel mode when bit 7 of the Panel + Format Register (3d6h index 50h) is set and bits 2-3 of the same + register is either 1 or 2. + The time between WGTCLK pulses is this value*4 dot clocks. + See also 3d6h index 5Ch and 6Ch. + + 3d6h index 5Eh (R/W): ACDCLK Control Register (82c455/6/7, 655x0 only) + bit 0-6 ACDCLK Count. Number of Hsync pulses between changes in ACDCLK. + 7 If set the ACDCLK phase inverts every frame, if clear the ACDCLK + changes phase when the number of Hsynmc pulses specified in + bits 0-6 have elapsed. + + 3d6h index 5Fh (R/W): Power Down Mode Refresh Register (82c455/6/7, 655x0 only) + bit 0-7 (82c455/6/7) Sleep Mode Refresh Frequency. + A refresh will happen for every (4*this value)+8 dot clocks. + 0-1 (655x0) Power Down Refresh Frequency. + Refresh happens every xx micro seconds: + 0=16usek, 1=32 usek, 2=64 usek and 3=128 usek. + + 3d6h index 60h (R/W): Blink Rate Control (82c455/6/7, 655x0 Only) + bit 0-5 Blink Rate. + Character Blink Freq = Vertical sync Freq * (Blink rate+1) + Cursor blink freq = Character Blink Freq *2. + 6-7 Blink Cycle 1=25%, 2=50%, 3=75% + + 3d6h index 61h (R/W): Smartmap Control (82c455/6, 655x0 Only) + bit 0 If set enables Smartmap and bypasses internal color lookup table. + 1-4 Threshold for (Foreground - Background) diff + if diff less than the threshold the foreground and + background colors will be spread (See 3d6h index 62h). + 5 Smartmap Saturation value. + If set the result is calculated modulo 16, + if clear it is rounded to min. or max. values (0 and 0Fh). + 6 (82c456, 655x0) Enhanced text if set + (reverses attributes 7h and Fh) + 7 (655x0) Text Video Output Polarity (TVP) if set. + Only effective in Flat Panel modes. + + 3d6h index 62h (R/W): Smartmap Shift Parameter (82c455/6, 655x0 Only) + bit 0-3 Number of levels to shift foreground color + when too little difference (See 3d6h index 61h bit 1-4). + 4-7 Number of levels to shift background color. + + 3d6h index 63h (R/W): Graphics Color Mapping Control (82c455/6 Only) + bit 0-3 Threshold color value for mono output. + All colors >= this value will be set to 1, + all lower to 0. + 4 Use upper 4 bits of 256 color if set, lower if not. + 5 Enable internal color lookup table if set + 6 Write protect internal color look up table if set + 7 Graphics output polarity + + 3d6h index 63h (R/W): Smartmap Color Mapping Control (655x0 only) + bit 0-5 Color Threshold. Used for mapping 6 bit color to 1 bit. + Color values greater than or equal than this value + are mapped to 1, and lower values are mapped to 0. + 6 Must be set to 1. + 7 Graphics Video Output Polarity + Inverted polarity if set, normal if clear. + Graphics video output only. + + 3d6h index 64h (R/W): Alternate Vertical Total (82c455/6/7, 655x0 only) + bit 0-7 Alternate Vertical Total + Note: For Flat Panel modes this register replaces the Vertical + Total Register (3d4h index 6). + + 3d6h index 65h (R/W): Alternate Overflow (82c455/6/7, 655x0 only) + bit 0 Alternate Vertical Total bit 8 + 1 (455/6/7) Alternate Vertical Display End bit 8. + (655x0) Alternate Vertical Panel Size bit 8. + 2 Alternate Vertical Sync Start bit 8. + 3 (655x0) Alternate Vertical Sync Start bit 10. + 4 (655x0) Alternate Vertical Total bit 10. + 5 Alternate Vertical Total bit 9 + 6 (455/6/7) Alternate Vertical Display End bit 9. + (655x0) Alternate Vertical Panel Size bit 9. + 7 Alternate Vertical Sync Start bit 9. + + 3d6h index 66h (R/W): Alternate Vertical Sync Start (82c455/6/7, 655x0 only) + bit 0-7 Alternate Vertical Sync Start + Note: For Flat Panel modes this register replaces the Vertical + Sync Start Register (3d4h index 10h). + + 3d6h index 67h (R/W): Alternate Vertical Sync End (82c455/6/7, 655x0 only) + bit 0-3 Alternate Vertical Sync End + Note: For Flat Panel modes this register replaces the Vertical + Sync End Register (3d4h index 11h). + + 3d6h index 68h (R/W): Alternate Vertical Display Enable (82c455/6/7 only) + bit 0-7 Alternate Vertical Display Enable + Note: For Flat Panel modes this register replaces the Vertical + Display Enable Register (3d4h index 12h) + + 3d6h index 69h (R/W): Vertical Panel Size Register. (655x0 only) + bit 0-7 Vertical Panel Size. + Number of scan lines per frame. + + 3d6h index 69h (R/W): Flat Panel Vertical Display Start_350 (82c455/6/7 only) + bit 0-7 For 350 line Flat Panel modes these are the lower 8 bits of the + Vertical Display Start (in scanlines). The upper 2 bits are in the + Flat Panel Vertical Overflow 2 Register (3d6h index 6Bh) bits 0-1. + + 3d6h index 6Ah (R/W): Flat Panel Vertical Display End_350 (82c455/6/7 only) + bit 0-7 For 350 line Flat Panel modes these are the lower 8 bits of the + Vertical Display End (in scanlines). The upper 2 bits are in the + Flat Panel Vertical Overflow 2 Register (3d6h index 6Bh) bits 4-5. + + 3d6h index 6Bh (R/W): Flat Panel Vertical Overflow 2 (82c455/6/7 only) + bit 0-1 Bits 8-9 of the Vertical Display Start_350 Register + (3d6h index 69h) + 2-3 Bits 8-9 of the Vertical Display Start_400 Register (3d6h index 5Ah + 4-5 Bits 8-9 of the Vertical Display End_350 Register (3d6h index 6Ah) + 6-7 Bits 8-9 of the Vertical Display End_400 Register (3d6h index 5Bh) + + 3d6h index 6Ch (R/W): Weight Clock Control Register (82c455/6/7 only) + bit 0-5 Weight Clock Control Pulse Count. + Total number of pulses on the Weight Clock. + See Also 3d6h index 5Ch and 5Dh. + + 3d6h index 6Ch (R/w): Programmable Output Drive Register (655x0 only) + bit 0 Input Level Sense Selection Mode. + If set bit 1 is used to determine input threshold. + If clear chip detects VCC voltage internally. + 1 Input Level Sense Selection Voltage. + If set VCC for internal logic is 3.3V + if clear it is 5V. + 2 Flat Panel Interface Output Drive Select + If set Higher drive, if clear Lower drive. + 3 Bus Interface Output Drive Select. + If set Higher drive, if clear Lower drive. + 4 Memory Interface output Drive Select. + If set Higher drive, if clear Lower drive. + + 3d6h index 6Dh (R/W): FRC and Palette Control (82c456/7 Only) + bit 3 Enable Frame Rate Control + 4-5 Maximum number of gray levels. + 0: 64 level FRC + 1: 16 level FRC with dither for 256 color modes. + 2: 64 level FRC with dither for low gray levels. + 3: 16 level FRC only. + 6-7 Usage of External Palette: + 0: Bypass + 1: Bypass for 16 color modes, use for 256 color. + 2: Always use + 3: 16 grays for 16 color modes, 64 for 256 color. + + 3d6h index 6Eh (R/W): Polynomial FRC Control (82c456/7, 655x0 Only) + bit 0-3 Polynomial N value for Frame Rate Control + 4-7 Polynomial M value. + + 3d6h index 6Fh (R/W): Frame Buffer Control register (655x0 only) + bit 0 Frame Buffer Enable. + External Frame Buffer enabled if set. + 1 Frame Accelerator enabled if set. + 2 Frame Buffer memory Type. + If set Frame Buffer consists of 256Kx4 VRAM. + If clear Frame Buffer consists of 64Kx4 VRAM + 3-5 Frame Buffer Refresh Count. + 6-7 Reserved. Must be set to 0. + Note: This register effective in Flat Panel mode only. + + 3d6h index 70h (R/W): Setup/Disable Control Register. (655x0 only) + bit 7 3C3/46E8 Register Disabled if set. + + 3d6h index 7Dh (R/W): FP Compensation Diagnostic Register (655x0 only) + bit 0-7 Reserved. returns 0. + + 3d6h index 7Eh (R/W): CGA Color Select + This is a copy of the CGA Color Select Register at 3D9h. + The copy at 3D9h is only visible in CGA emulation mode. + This register is always visible. + + 3d6h index 7Fh (R/W): Diagnostic + bit 0 if set 3-states pins: PALRD/, PALWR/, WR46E8/, HSYNC, VSYNC, + ACDCLK, BLANK/, P0-7, RDY, DATEN/ AND IRQ/. + 1 If set 3-states pins: WE/, RAS/, CAS0/, CAS1/, + CAS2/, CAS3/, AA0-7 AND BA0-7. + 2-5 Test Function Pins. Should be 0. + 6 (655x0) Test Function Enabled if set. + 7 (655x0) Special Test Function. Should be set to 0. + + 46E8h (R/W): Setup Control PC/AT Register + bit 0-2 Reserved + 3 Enables Adapter VGA if set + 4 Enters Setup Mode if set + 5-7 Reserved +Note: This is the same register as 94h. + + + Most every index of 3d6h is used by one one or more chip. + + Bank Switching: + + Bank switching is dependent on Chip version: + + 16 color modes 256 color modes + Chip #bank regs #Banks Granularity #banks Granularity + 82c451/5/6 1 4 64Kbytes + 82c452 2 64 4Kbytes 64 16Kbytes + 82c453 2 256 1Kbytes 256 4Kbytes + + For the 82c452 & 3 the window to display memory can start on + any boundary fitting the granularity of the chip/display mode. + When using 2 bankregisters, the address range available to the + adapter is split equally between the two bank registers. I.e. + A000h-A7FFh uses one bank, and A800h-AFFFh the other. + (Or A000h-AFFFh and B000h-BFFFh respectively if using the full + 128 Kbytes range). + + + + ID Chips and Technologies Chip Set: + + + vio($6F00); + if rp.al=$5F then + case rp.bl of + 0:Chip&Tech 82c451 !!! + 1:Chip&Tech 82c452 !!! + 2:Chip&Tech 82c455 !!! + 3:Chip&Tech 82c453 !!! + 5:Chip&Tech 82c456 !!! + 6:Chip&Tech 82c457 !!! + 7:Chip&Tech F65520 !!! + 8:Chip&Tech F65530 !!! + end; + + + + Video Modes: + + 60h T 132 25 16 (8x16) + 61h T 132 50 16 (8x8) + 6Ah G 800 600 16 planar + 70h G 800 600 16 planar + 71h G 960 720 16 planar Cardinal only! + 72h G 1024 768 16 planar + 78h G 640 400 256 packed Not documented/not all boards + 79h G 640 480 256 packed + 7Ah G 720 540 256 packed Not documented/not all boards + 7Bh G 800 600 256 packed + 7Ch G 800 600 256 packed (82c453 Only) + 7Eh G 1024 768 256 packed (82c453 Only) + + Bios Extensions: +----------105F00----------------------------- +INT 10 - Get Controller Information (Chips and Technologies Super VGA) + AX = 5F00h +Return: AL = 5F If extended VGA control function supported + BL = CHIP Type: + Bits 4-7: + 0=82c451 + 1=82c452 + 2=82c455 + 3=82c453 + 5=82c456 + Bits 0-3: Revision Number + BH = Video Memory Size + 0=256 Kbytes + 1=512 Kbytes + 2=1 Megabyte + CX = Miscellaneous Information + Bit 0 Dac Size. 0=6bit, 1=8bit + 1 System Environment. 0=PC/AT, 1=PS/2 + 2 Extended text modes supported by BIOS + 3 Reserved + 4 Extended graphics modes supported by BIOS + 5 Reserved + 6 Graphics Cursor supported by BIOS + 7 Anti Alias font supported by BIOS + 8 Preprogrammed emulation supported by BIOS + 9 Auto emulation supported by BIOS + 10 Variable mode set at cold boot supported by BIOS + 11 Variable mode set at warm boot supported by BIOS + 12 Emulation mode set at cold boot supported by BIOS + 13 Emulation mode set at warm boot supported by BIOS + 14-15 Reserved +----------105F01----------------------------- +INT 10 - Set Emulation Mode (Chips and Technologies Super VGA) + AX = 5F01h + BL = Operation Mode + 0-1 Reserved + 2 Enable CGA Emulation + 3 Enable MDA Emulation + 4 Enable Hercules Emulation + 5 Enable EGA Emulation + 6 Enable VGA Emulation +Return: AL = 5Fh If function supported + AH = Return Status + 1 If Function Successful, 0 else +----------105F02----------------------------- +INT 10 - Auto Emulation Control (Chips and Technologies Super VGA) + AX = 5F02h Auto Emulation Control + BL = Selection + 0= Enable Auto Emulation + 1= Disable Auto Emulation +Return: AL = 5Fh If function supported + AH = Return Status + 1 If Function Successful, 0 else +----------105F03----------------------------- +INT 10 - Set Power-on Video Configuration (Chips and Technologies Super VGA) + AX = 5F03h + BL = Configuration + 0: Set display mode as specified in the CX register + at power-up. + + CL=Display Mode + CH=Bits 0-1 Scanlines + 0=200 Lines + 1=350 Lines + 2=400 Lines + Bit 7 Performance + 0= Reset after next boot + 1= Set until changed + + 1: Set Emulation mode as specified in the CX register + at power-up. + + CL=Emulation Mode (See 5F01h) + CH=Bit 7 Performance + 0= Reset after next boot + 1= Set until changed + +Return: AL = 5Fh If function supported + AH = Return Status + 1 If Function Successful, 0 else +----------105F90----------------------------- +INT 10 - Return Save/Restore buffer size (Chips and Technologies Super VGA) + AX = 5F90h + CX = Mask State + Bit 0 Save/Restore video hardware + 1 Save/Restore BIOS data state + 2 Save/Restore DAC state + 15 Save/Restore type + 0= Save/Restore All state information + 1= Save/Restore super state information + +Return: AL = 5Fh If function supported + BX = Number of 64byte blocks required +----------105F91----------------------------- +INT 10 - Save State (Chips and Technologies Super VGA) + AX = 5F91h + CX = Mask State + Bit 0 Save video hardware + 1 Save BIOS data state + 2 Save DAC state + 15 Save type + 0= Save All state information + 1= Save super state information + ES:BX -> Buffer to save in. +Return: AL = 5Fh If function supported +----------105F92----------------------------- +INT 10 - Restore State (Chips and Technologies Super VGA) + AX = 5F92h + CX = Mask State + Bit 0 Restore video hardware + 1 Restore BIOS data state + 2 Restore DAC state + 15 Restore type + 0= Restore All state information + 1= Restore super state information + ES:BX -> Buffer to restore from. +Return: AL = 5Fh If function supported diff --git a/16/tweak16/MISC/READ.ME b/16/tweak16/MISC/READ.ME new file mode 100755 index 00000000..ba9b56de --- /dev/null +++ b/16/tweak16/MISC/READ.ME @@ -0,0 +1,66 @@ +This is the second edition of my VGADOC info-pack on VGA adapters. + +Major improvements include new chipsets added or expanded upon +and much better coverage of Hi/TrueColor. + +Also a number of bugs/misinformations have been corrected. + +For each chipset there is a .txt file with the info. + + + + +Also included is WHATVGA, my utility for testing all this info: + + whatvga.exe The test program. + whatvga.pas The generel part of the program. + supervga.pas The device dependend part of Whatvga + whatvga.doc Information and test report. + whatvga.lst The list of all modes supported + + + +I'm currently looking for (among other things) the following chipsets: + + S3 new 928, 801 and 805 + Weitek W5086, W5186 and new P9000 + IIT AGX... (I've got some info, but I sure could use any other) + Tseng ET4000W32 The long awaited accelerated version. + Paradise WD90c31 - the accelerator part + Avance AL2101 - The accelerator part + Primus P2000 - The accelerator part + + HiColor support for any chipset where it is not currently shown. + + + +I'ld be very interested in any information you may be able to supply, +whether as new information, corrections or suggestions. + +Any major contributors will be given credit in future versions. +Please specify if you have special requests as to names or addresses +used (or not used). + + + +While I'll try to answer all queries, experience shows that I sometimes +have trouble keeping up (I have this nasty habit of working 75 hour +weeks). + + + +I can be contacted at the following addresses: + +Usenet: jesperf@daimi.aau.dk + Please note that this is an account + a friend lets me use, so mail should + be addressed directly to me. + Also lets keep the volume down, ok? + +Phone: +45 97 51 21 88 !These are at work, so please address +Fax: +45 97 51 26 21 !any queries explicitly to me. + +Snail-mail: Finn Thoegersen + Nordbanevej 3 C + DK-7800 Skive + Denmark \ No newline at end of file diff --git a/16/tweak16/MISC/SETMODEX.ASM b/16/tweak16/MISC/SETMODEX.ASM new file mode 100755 index 00000000..34d0809b --- /dev/null +++ b/16/tweak16/MISC/SETMODEX.ASM @@ -0,0 +1,87 @@ +; This file was taken from Michael Abrash' XSHARP package, a library +; for programming mode X (320x240x256). + +; Mode X (320x240, 256 colors) mode set routine. Works on all VGAs. +; C near-callable as: +; void Set320x240Mode(void); +; Tested with TASM 2.0. +; Modified from public-domain mode set code by John Bridges. + +SC_INDEX equ 03c4h ;Sequence Controller Index +CRTC_INDEX equ 03d4h ;CRT Controller Index +MISC_OUTPUT equ 03c2h ;Miscellaneous Output register +SCREEN_SEG equ 0a000h ;segment of display memory in mode X + + .model small + .data +; Index/data pairs for CRT Controller registers that differ between +; mode 13h and mode X. +CRTParms label word + dw 00d06h ;vertical total + dw 03e07h ;overflow (bit 8 of vertical counts) + dw 04109h ;cell height (2 to double-scan) + dw 0ea10h ;v sync start + dw 0ac11h ;v sync end and protect cr0-cr7 + dw 0df12h ;vertical displayed + dw 00014h ;turn off dword mode + dw 0e715h ;v blank start + dw 00616h ;v blank end + dw 0e317h ;turn on byte mode +CRT_PARM_LENGTH equ (($-CRTParms)/2) + + .code + public _Set320x240Mode +_Set320x240Mode proc near + push bp ;preserve caller's stack frame + push si ;preserve C register vars + push di ; (don't count on BIOS preserving anything) + + mov ax,13h ;let the BIOS set standard 256-color + int 10h ; mode (320x200 linear) + + mov dx,SC_INDEX + mov ax,0604h + out dx,ax ;disable chain4 mode + mov ax,0100h + out dx,ax ;synchronous reset while switching clocks + + mov dx,MISC_OUTPUT + mov al,0e7h + out dx,al ;select 28 MHz dot clock & 60 Hz scanning rate + + mov dx,SC_INDEX + mov ax,0300h + out dx,ax ;undo reset (restart sequencer) + + mov dx,CRTC_INDEX ;reprogram the CRT Controller + mov al,11h ;VSync End reg contains register write + out dx,al ; protect bit + inc dx ;CRT Controller Data register + in al,dx ;get current VSync End register setting + and al,7fh ;remove write protect on various + out dx,al ; CRTC registers + dec dx ;CRT Controller Index + cld + mov si,offset CRTParms ;point to CRT parameter table + mov cx,CRT_PARM_LENGTH ;# of table entries +SetCRTParmsLoop: + lodsw ;get the next CRT Index/Data pair + out dx,ax ;set the next CRT Index/Data pair + loop SetCRTParmsLoop + + mov dx,SC_INDEX + mov ax,0f02h + out dx,ax ;enable writes to all four planes + mov ax,SCREEN_SEG ;now clear all display memory, 8 pixels + mov es,ax ; at a time + sub di,di ;point ES:DI to display memory + sub ax,ax ;clear to zero-value pixels + mov cx,8000h ;# of words in display memory + rep stosw ;clear all of display memory + + pop di ;restore C register vars + pop si + pop bp ;restore caller's stack frame + ret +_Set320x240Mode endp + end diff --git a/16/tweak16/MISC/VGA.TXT b/16/tweak16/MISC/VGA.TXT new file mode 100755 index 00000000..12129aa4 --- /dev/null +++ b/16/tweak16/MISC/VGA.TXT @@ -0,0 +1,551 @@ + 3C0h: Attribute Controller: Address register + bit 0-4 Address of data register to write to port 3C0h + or read from port 3C1h (Reads only on VGA). + 5 If set screen output is enabled and the palette can not be + modified, if clear screen output is disabled and the palette + can be modified. + + + Port 3C0h is special in that it is both address and data-write + register. Data reads happen from port 3C1h. An internal + flip-flop remembers whether it is currently acting as + address or data register. + Accesses to the attribute controller must be separated by + at least 250ns. + Reading port 3dAh will reset the flip-flop to address mode. + + + 3C0h index 0-Fh (r/W): Attribute: Palette + bit 0 (EGA) Primary Blue + 1 (EGA) Primary Green + 2 (EGA) Primary Red + 3 (EGA) Secondary Blue + 4 (EGA) Secondary Green + 5 (EGA) Secondary Red + 0-5 (VGA) Index into the 256 color DAC table. + May be modified by 3C0h index 10h and 14h. + + 3C0h index 10h (r/W): Attribute: Mode Control Register + bit 0 Graphics mode if set, Alphanumeric mode else. + 1 Monochrome mode if set, color mode else. + 2 9-bit wide characters if set. + The 9th bit of characters C0h-DFh will be the same as + the 8th bit. Otherwise it will be the background color. + 3 If set Attribute bit 7 is blinking, else high intensity. + 5 (VGA Only) If set the PEL panning register (3C0h index 13h) + is temporarily set to 0 from when the line + compare causes a wrap around until the next + vertical retrace when the register is automatically + reloaded with the old value, else the PEL + panning register ignores line compares. + 6 (VGA Only) If set pixels are 8 bits wide. + Used in 256 color modes. + 7 (VGA Only) If set bit 4-5 of the index into the DAC table + are taken from port 3C0h index 14h bit 0-1, + else the bits in the palette register are used. + + 3C0h index 11h (r/W): Attribute: Overscan Color Register. + bit 0-5 Color of screen border. Color is defined as in the + palette registers. + Note: The EGA requires the Overscan color to be 0 in high resolution + modes. + + 3C0h index 12h (r/W): Attribute: Color Plane Enable Register + bit 0 Bit plane 0 is enabled if set. + 1 Bit plane 1 is enabled if set. + 2 Bit plane 2 is enabled if set. + 3 Bit plane 3 is enabled if set. + 4-5 Video Status MUX. Diagnostics use only. + Two attribute bits appear on bits 4 and 5 of the Input + Status Register 1 (3dAh). + Value EGA VGA + 0 Red/Blue Bit 2/Bit 0 + 1 Blue'/Green Bit 5/Bit 4 + 2 Red'/Green' Bit 3/Bit 1 + 3 Bit 7/Bit 6 + + 3C0h index 13h (r/W): Attribute: Horizontal PEL Panning Register + bit 0-3 Indicates number of pixels to shift the display left + Value 9bit textmode 256color mode Other modes + 0 1 0 0 + 1 2 n/a 1 + 2 3 1 2 + 3 4 n/a 3 + 4 5 2 4 + 5 6 n/a 5 + 6 7 3 6 + 7 8 n/a 7 + 8 0 n/a n/a + + 3C0h index 14h (r/W): Attribute: Color Select Register (VGA Only) + bit 0-1 If 3C0h index 10h bit 7 is set these 2 bits are used + as bits 4-5 of the index into the DAC table. + 2-3 These 2 bits are used as bit 6-7 of the index into the + DAC table except in 256 color mode. + + Note: this register does not affect 256 color modes. + + + 3C2h (R): Input Status #0 Register + bit 4 Status of the switch selected by the Miscellaneous Output + Register 3C2h bit 2-3. Switch high if set. + 5 (EGA Only) Pin 19 of the Feature Connector (FEAT0) + is high if set + 6 (EGA Only) Pin 17 of the Feature Connector (FEAT1) + is high if set + 7 (EGA Only ??) If set IRQ 2 has happened due to Vertical + Retrace. Should be cleared by IRQ 2 interrupt routine + by clearing port 3d4h index 11h bit 4. + + + 3C2h (W): Miscellaneous Output Register + bit 0 If set Color Emulation. Base Address=3Dxh + else Mono Emulation. Base Address=3Bxh. + 1 Enable CPU Access to video memory if set + 2-3 Clock Select + 0: 14MHz(EGA) 25MHz(VGA) + 1: 16MHz(EGA) 28MHz(VGA) + 2: External(EGA) Reserved(VGA) + 4 (EGA Only) Disable internal video drivers if set + 5 When in Odd/Even modes Select High 64k bank if set + 6 Horizontal Sync Polarity. Negative if set + 7 Vertical Sync Polarity. Negative if set + Bit 6-7 indicates the number of lines on the display: + 0=200(EGA) Reserved(VGA) + 1= 400(VGA) + 2=350(EGA) 350(VGA) + 3= 480(VGA). + + Note: Set to all zero on a hardware reset. + Note: On the VGA this register can be read from port 3CCh. + + + 3C3h (W): Video Subsystem Enable Register + bit 0 Enables the VGA display if set + + + 3C4h index 0 (r/W): Sequencer: Reset + bit 0 (EGA) Asynchronous Reset if clear + 0 (VGA) Synchronous Reset just as bit 1 + 1 Synchronous Reset if clear + + 3C4h index 1 (r/W): Sequencer: Clocking Mode + bit 0 If set character clocks are 8 dots wide, else 9. + 1 (EGA Only) If set the CRTC uses 2/5 of the clock cycles, else 4/5. + 2 If set loads video serializers every other character + clock cycle, else every one. + 3 If set the Dot Clock is Master Clock/2, else same as + Master Clock (See 3C2h bit 2-3). (Doubles pixels). + 4 (VGA Only) If set loads video serializers every fourth + character clock cycle, else every one. + 5 (VGA Only) if set turns off screen and gives all memory + cycles to the CPU interface. + + 3C4h index 2 (r/W): Sequencer: Map Mask Register + bit 0 Enable writes to plane 0 if set + 1 Enable writes to plane 1 if set + 2 Enable writes to plane 2 if set + 3 Enable writes to plane 3 if set + + 3C4h index 3 (r/W): Sequencer: Character Map Select Register + bit 0-1 (EGA) Selects EGA Character Map (0..3) if bit 3 of + the character attribute is clear. + 2-3 (EGA) Selects EGA Character Map (0..3) if bit 3 of + the character attribute is set. + 0,1,4 (VGA) Selects VGA Character Map (0..7) if bit 3 of + the character attribute is clear. + 2,3,5 (VGA) Selects VGA Character Map (0..7) if bit 3 of + the character attribute is set. + + Character Maps are placed at: + Map no. (EGA/VGA) Map no. (VGA) + 0 0k 4 8k + 1 16k 5 24k + 2 32k 6 40k + 3 48k 7 56k + + 3C4h index 4 (r/W): Sequencer: Memory Mode Register + bit 0 Set if in an alphanumeric mode, clear in graphics modes. + 1 Set if more than 64kbytes on the adapter. + 2 Enables Odd/Even addressing mode if set. + Odd/Even mode places all odd bytes in plane 1&3, and + all even bytes in plane 0&2. + 3 (VGA Only) If set address bit 0-1 selects video memory + planes (256 color mode), rather than the + Map Mask and Read Map Select Registers. + + 3C4h index 7 (R/W): Sequencer Horizontal Character Counter Reset Register. + (VGA Only). + Note: Undocumented by IBM. May not be available in all clones. + Note: A write to this register will cause the Horizontal Character Counter + to be held reset (=0) until a write happens to any of the Sequencer + registers index 0..6. + The Vertical Line counter is clocked by a signal derived from the + Horizontal Display Enable (which does not occur if the Horizontal + Character Counter is held reset). + Thus a write to index 7 during Vertical Retrace can stop the display + timing and allow software to start the next frame reasonably + synchronous to an external event. + + 3C6h (R/W): PEL Mask (VGA Only) + bit 0-7 This register is anded with the palette index sent + for each dot. Should be set to FFh. + + 3C7h (R): DAC State Register (VGA Only) + bit 0-1 0 indicates the DAC is in Read Mode and 3 indicates + write mode. + + 3C7h (W): PEL Address Read Mode (VGA Only) + bit 0-7 The PEL data register (0..255) to be read from 3C9h. + + Note: After reading the 3 bytes at 3C9h this register will + increment, pointing to the next data register. + + 3C8h (R/W): PEL Address Write Mode (VGA Only) + bit 0-7 The PEL data register (0..255) to be written to 3C9h. + Note: After writing the 3 bytes at 3C9h this register will + increment, pointing to the next data register. + + 3C9h (R/W): PEL Data Register (VGA Only) + bit 0-5 Color value + Note: Each read or write of this register will cycle through first + the registers for Red, Blue and Green, then increment the + appropriate address register, thus the entire palette can be + loaded by writing 0 to the PEL Address Write Mode register 3C8h + and then writing all 768 bytes of the palette to this register. + + 3CAh (R): Feature Control Register (VGA Only) + Bit 3 (VGA Only) Vertical Sync Select + If set Vertical Sync to the monitor is the logical OR + of the vertical sync and the vertical display enable. + Note: This register is written to port 3dAh and read from 3CAh. + + + 3CAh (W): Graphics 2 Position (EGA Only) + bit 0-1 Select which bit planes should be controlled by + Graphics Controller #2. Always set to 1. + + 3CCh (R): Miscellaneous Output Register (VGA Only) + bit 0 If set Color Emulation. Base Address=3Dxh + else Mono Emulation. Base Address=3Bxh. + 1 Enable CPU Access to video memory if set + 2-3 Clock Select + 0= 25MHz, 1= 28MHz, 2= Reserved + 5 When in Odd/Even modes Select High 64k bank if set + 6 Horizontal Sync Polarity. Negative if set + 7 Vertical Sync Polarity. Negative if set + Bit 6-7 indicates the number of lines on the display: + 0=Reserved, 1=400, 2=350, 3=480. + Note: This register is written to port 3C2h and read from port 3CCh. + + + 3CCh (W): Graphics 1 Position (EGA Only) + bit 0-1 Select which bit planes should be controlled by + Graphics Controller #1. Always set to 0. + + 3CEh index 0 (r/W): Graphics: Set/Reset Register + bit 0 If in Write Mode 0 and bit 0 of 3CEh index 1 is set + a write to display memory will set all the bits in + plane 0 of the byte to this bit, if the corresponding + bit is set in the Map Mask Register (3CEh index 8). + 1 Same for plane 1 and bit 1 of 3CEh index 1. + 2 Same for plane 2 and bit 2 of 3CEh index 1. + 3 Same for plane 3 and bit 3 of 3CEh index 1. + + 3CEh index 1 (r/W): Graphics: Enable Set/Reset Register + bit 0 If set enables Set/reset of plane 0 in Write Mode 0. + 1 Same for plane 1. + 2 Same for plane 2. + 3 Same for plane 3. + + 3CEh index 2 (r/W): Graphics: Color Compare Register + bit 0-3 In Read Mode 1 each pixel at the address of the byte read + is compared to this color and the corresponding bit in + the output set to 1 if they match, 0 if not. + The Color Don't Care Register (3CEh index 7) can exclude + bitplanes from the comparison. + + 3CEh index 3 (r/W): Graphics: Data Rotate + bit 0-2 Number of positions to rotate data right before it is + written to display memory. Only active in Write Mode 0. + 3-4 In Write Mode 2 this field controls the relation between + the data written from the CPU, the data latched from the + previous read and the data written to display memory: + 0: CPU Data is written unmodified + 1: CPU data is ANDed with the latched data + 2: CPU data is ORed with the latch data. + 3: CPU data is XORed with the latched data. + + + 3CEh index 4 (r/W): Graphics: Read Map Select Register + bit 0-1 Number of the plane Read Mode 0 will read from. + + 3CEh index 5 (r/W): Graphics: Mode Register + bit 0-1 Write Mode: Controls how data from the CPU is + transformed before being written to display memory: + 0: Mode 0 works as a Read-Modify-Write operation. + First a read access loads the data latches of the EGA/VGA + with the value in video memory at the addressed location. + Then a write access will provide the destination address + and the CPU data byte. The data written is modified by the + function code in the Data Rotate register (3CEh index 3) as + a function of the CPU data and the latches, then data + is rotated as specified by the same register. + 1: Mode 1 is used for video to video transfers. + A read access will load the data latches with the contents + of the addressed byte of video memory. A write access will + write the contents of the latches to the addressed byte. + Thus a single MOVSB instruction can copy all pixels in the + source address byte to the destination address. + 2: Mode 2 writes a color to all pixels in the addressed byte + of video memory. Bit 0 of the CPU data is written to plane 0 + et cetera. Individual bits can be enabled or disabled through + the Bit Mask register (3CEh index 8). + 3: (VGA Only) Mode 3 can be used to fill an area with a color and + pattern. The CPU data is rotated according to 3CEh index 3 + bits 0-2 and anded with the Bit Mask Register (3CEh index 8). + For each bit in the result the corresponding pixel is set to + the color in the Set/Reset Register (3CEh index 0 bits 0-3) + if the bit is set and to the contents of the processor latch + if the bit is clear. + 2 (EGA Only) Forces all outputs to a high impedance state if set. + 3 Read Mode + 0: Data is read from one of 4 bit planes depending + on the Read Map Select Register (3CEh index 4). + 1: Data returned is a comparison between the 8 pixels + occupying the read byte and the color in the + Color Compare Register (3CEh index 2). + A bit is set if the color of the corresponding + pixel matches the register. + 4 Enables Odd/Even mode if set (See 3C4h index 4 bit 2). + 5 Enables CGA style 4 color pixels using even/odd bit pairs + if set. + 6 (VGA Only) Enables 256 color mode if set. + + 3CEh index 6 (r/W): Graphics: Miscellaneous Register + bit 0 Indicates Graphics Mode if set, Alphanumeric mode else. + 1 Enables Odd/Even mode if set. + 2-3 Memory Mapping: + 0: use A000h-BFFFh + 1: use A000h-AFFFh EGA/VGA Graphics modes + 2: use B000h-B7FFh Monochrome modes + 3: use B800h-BFFFh CGA modes + + 3CEh index 7 (r/W): Graphics: Color Don't Care Register + bit 0 Ignore bit plane 0 in Read mode 1 if clear. + 1 Ignore bit plane 1 in Read mode 1 if clear. + 2 Ignore bit plane 2 in Read mode 1 if clear. + 3 Ignore bit plane 3 in Read mode 1 if clear. + + 3CEh index 8 (r/W): Graphics: Bit Mask Register + bit 0-7 Each bit if set enables writing to the corresponding + bit of a byte in display memory. + + + 3d4h index 0 (r/W): CRTC: Horizontal Total Register + bit 0-7 (EGA) Horizontal Total Character Clocks-2 + 0-7 (VGA) Horizontal Total Character Clocks-5 + + 3d4h index 1 (r/W): CRTC: Horizontal Display End Register + bit 0-7 Number of Character Clocks Displayed -1 + + 3d4h index 2 (r/W): CRTC: Start Horizontal Blanking Register + bit 0-7 The count at which Horizontal Blanking starts + + 3d4h index 3 (r/W): CRTC: End Horizontal Blanking Register + bit 0-4 Horizontal Blanking ends when the last 5 (6 for VGA) + bits of the character counter equals this field. + (VGA) The sixth bit is found in port 3d4h index 5 bit 7. + 5-6 Number of character clocks to delay start of display + after Horizontal Total has been reached. + 7 (VGA Only) Access to Vertical Retrace registers if set + If clear reads to 3d4h index 10h and 11h + access the Lightpen readback registers ?? + + 3d4h index 4 (r/W): CRTC: Start Horizontal Retrace Register + bit 0-7 Horizontal Retrace starts when the Character Counter + reaches this value. + + 3d4h index 5 (r/W): CRTC: End Horizontal Retrace Register + bit 0-4 Horizontal Retrace ends when the last 5 bits of the + character counter equals this value. + 5-6 Number of character clocks to delay start of display + after Horizontal Retrace. + 7 (EGA) Provides Smooth Scrolling in Odd/Even mode. + When set display starts from an odd byte. + 7 (VGA) bit 5 of the End Horizontal Blanking count + (See 3d4h index 3 bit 0-4). + + 3d4h index 6 (r/W): CRTC: Vertical Total Register + bit 0-7 Lower 8 bits of the Vertical Total + Bit 8 is found in 3d4h index 7 bit 0. + (VGA) Bit 9 is found in 3d4h index 7 bit 5. + Note: For the VGA this value is the number of scan lines in the display -2. + + 3d4h index 7 (r/W): CRTC: Overflow Register + bit 0 Bit 8 of Vertical Total (3d4h index 6) + 1 Bit 8 of Vertical Display End (3d4h index 12h) + 2 Bit 8 of Vertical Retrace Start (3d4h index 10h) + 3 Bit 8 of Start Vertical Blanking (3d4h index 15h) + 4 Bit 8 of Line Compare Register (3d4h index 18h) + 5 (VGA) Bit 9 of Vertical Total (3d4h index 6) + 6 (VGA) Bit 9 of Vertical Display End (3d4h index 12h) + 7 (VGA) Bit 9 of Vertical Retrace Start (3d4h index 10h) + + 3d4h index 8 (r/W): CRTC: Preset Row Scan Register + bit 0-4 Number of lines we have scrolled down in the first + character row. Provides Smooth Vertical Scrolling. + 5-6 (VGA Only) Number of bytes to skip at the start of + scanline. Provides Smooth Horizontal Scrolling + together with the Horizontal Panning Register + (3C0h index 13h). + + 3d4h index 9 (r/W): CRTC: Maximum Scan Line Register + bit 0-4 Number of scan lines in a character row -1 + 5 (VGA) Bit 9 of Start Vertical Blanking + 6 (VGA) Bit 9 of Line Compare Register + 7 (VGA) Doubles each scan line if set. + I.e displays 200 lines on a 400 display. + + 3d4h index Ah (r/W): CRTC: Cursor Start Register + bit 0-4 First scanline of cursor within character. + 5 (VGA) Turns Cursor off if set + + 3d4h index Bh (r/W): CRTC: Cursor End Register + bit 0-4 Last scanline of cursor within character + 5-6 Delay of cursor data in character clocks. + + 3d4h index Ch (r/W): CRTC: Start Address High Register + bit 0-7 Upper 8 bits of the start address of the display buffer + + 3d4h index Dh (r/W): CRTC: Start Address Low Register + bit 0-7 Lower 8 bits of the start address of the display buffer + + 3d4h index Eh (r/W): CRTC: Cursor Location High Register + bit 0-7 Upper 8 bits of the address of the cursor + + 3d4h index Fh (r/W): CRTC: Cursor Location Low Register + bit 0-7 Lower 8 bits of the address of the cursor + + 3d4h index 10h (R): CRTC: Light Pen High Register (EGA Only) + bit 0-7 (EGA Only) Upper 8 bits of the address of the + lightpen position. + + 3d4h index 10h (r/W): CRTC: Vertical Retrace Start Register + bit 0-7 Lower 8 bits of Vertical Retrace Start. Vertical Retrace + starts when the line counter reaches this value. + Bit 8 is found in 3d4h index 7 bit 2. + (VGA Only) Bit 9 is found in 3d4h index 7 bit 7. + + 3d4h index 11h (R): CRTC: Light Pen Low Register (EGA Only) + bit 0-7 (EGA Only) Lower 8 bits of the address of the + lightpen position. + + 3d4h index 11h (r/W): CRTC: Vertical Retrace End Register + bit 0-3 Vertical Retrace ends when the last 4 bits of the + line counter equals this value. + 4 if clear Clears pending Vertical Interrupts. + 5 Vertical Interrupts (IRQ 2) disabled if set. + Can usually be left disabled, but some systems + (including PS/2) require it to be enabled. + 6 (VGA Only) If set selects 5 refresh cycles per + scanline rather than 3. + 7 (VGA Only) Disables writing to registers 0-7 if set + 3d4h index 7 bit 4 is not affected by this bit. + + 3d4h index 12h (r/W): CRTC: Vertical Display End Register + bit 0-7 Lower 8 bits of Vertical Display End. The display + ends when the line counter reaches this value. + Bit 8 is found in 3d4h index 7 bit 1. + (VGA Only) Bit 9 is found in 3d4h index 7 bit 6. + + 3d4h index 13h (r/W): CRTC: Offset register + bit 0-7 Number of bytes in a scanline / K. Where K is 2 for + byte mode, 4 for word mode and 8 for Double Word mode. + + 3d4h index 14h (r/W): CRTC: Underline Location Register + bit 0-4 Position of underline within Character cell. + 5 (VGA Only) If set memory address is only changed + every fourth character clock. + 6 (VGA Only) Double Word mode addressing if set + + 3d4h index 15h (r/W): CRTC: Start Vertical Blank Register + bit 0-7 Lower 8 bits of Vertical Blank Start. Vertical blanking + starts when the line counter reaches this value. + Bit 8 is found in 3d4h index 7 bit 3. + + 3d4h index 16h (r/W): CRTC: End Vertical Blank Register + bit 0-4 (EGA) Vertical blanking stops when the lower 5 bits + of the line counter equals this field. + 0-6 (VGA) Vertical blanking stops when the lower 7 bits + of the line counter equals this field. + + 3d4h index 17h (r/W): CRTC: Mode Control Register + bit 0 If clear use CGA compatible memory addressing system + by substituting character row scan counter bit 0 for + address bit 13, thus creating 2 banks for even and + odd scan lines. + 1 If clear use Hercules compatible memory addressing + system by substituting character row scan counter bit 1 for + address bit 14, thus creating 4 banks. + 2 If set increase scan line counter only every second line. + 3 If set increase memory address counter only every other + character clock. + 4 (EGA Only) If set disable the EGA output drivers. This bit + is used for other purposes in some Super VGA chips. + 5 When in Word Mode bit 15 is rotated to bit 0 if this bit + is set else bit 13 is rotated into bit 0. + 6 If clear system is in word mode. Addresses are rotated + 1 position up bringing either bit 13 or 15 into bit 0. + 7 Clearing this bit will reset the display system + until the bit is set again. + + 3d4h index 18h (r/W): CRTC: Line Compare Register + bit 0-7 Lower 8 bits of the Line Compare. When the Line counter + reaches this value, the display address wraps to 0. + Provides Split Screen facilities. + Bit 8 is found in 3d4h index 7 bit 4. + (VGA Only) Bit 9 is found in 3d4h index 9 bit 6. + + 3d4h index 22h (R): Memory Latch Register (VGA - Undocumented). + bit 0-7 Reads the contents of the Graphics Controller Memory Data Latch + for the plane selected by 3C0h index 4 bit 0-1 (Read Map Select). + Note: This register is not documented by IBM and may not be available + on all clones. + + 3d4h index 24h (R): Attribute Controller Toggle Register. + (VGA - Undocumented). + bit 0-4 Attribute Controller Index. + The current value of the Attribute Index Register. + 5 Palette Address Source. Same as 3C0h bit 5. + 7 If set next read or write to 3C0h will access the data register. + Note: This register is not documented by IBM and may not be available + on all clones. + + 3d4h index 30h-3Fh (W): Clear Vertical Display Enable. (VGA - Undocumented). + bit 0 Setting this bit will clear the Vertical Display Enable thus + blanking the display for the rest of the frame and giving the CPU + total access to display memory until the start of the next frame. + Note: This register is not documented by IBM and may not be available + on all clones. + + 3dAh (R): Input Status #1 Register + bit 0 Either Vertical or Horizontal Retrace active if set + 1 (EGA Only) Light Pen has triggered if set + 2 (EGA Only) Light Pen switch is open if set + 3 Vertical Retrace in progress if set + 4-5 (EGA Only) Shows two of the 6 color outputs, + depending on 3C0h index 12h bit 4-5: + Attr: Bit 4-5: Out bit 4 Out bit 5 + 0 Blue Red + 1 I Blue Green + 2 I Red I Green + + 3dAh (W): Feature Control Register + bit 0 (EGA Only) Output to pin 21 of the Feature Connector. + 1 (EGA Only) Output to pin 20 of the Feature Connector. + 3 (VGA Only) Vertical Sync Select + If set Vertical Sync to the monitor is the logical OR + of the vertical sync and the vertical display enable. + + Note: On the VGA this register can be read from port 3CAh. diff --git a/16/tweak16/MISC/VGABIOS.TXT b/16/tweak16/MISC/VGABIOS.TXT new file mode 100755 index 00000000..40601ba9 --- /dev/null +++ b/16/tweak16/MISC/VGABIOS.TXT @@ -0,0 +1,707 @@ +----------1000------------------------------- +INT 10 - VIDEO - SET VIDEO MODE + AH = 00h + AL = mode (see below) +Return: AL = video mode flag (Phoenix BIOS) + 20h mode > 7 + 30h modes <= 7 except mode 6 + 3Fh mode 6 + AL = CRT controller mode byte (Phoenix 386 BIOS v1.10) +Notes: IBM standard modes do not clear the screen if the high bit of AL is set + (EGA or higher only) +SeeAlso: AX=0070h,AX=007Eh,AX=10F0h,AX=6F05h,AH=FFh"GO32",INT 5F/AH=00h + +Values for video mode: + text/ text pixel pixel colors display scrn system + grph resol box resoltn pages addr + 00h = T 40x25 8x14 16gray 8 B800 EGA + = T 40x25 8x16 16 8 B800 MCGA + = T 40x25 9x16 16 8 B800 VGA + 01h = T 40x25 8x14 16 8 B800 EGA + = T 40x25 8x16 16 8 B800 MCGA + = T 40x25 9x16 16 8 B800 VGA + 02h = T 80x25 8x14 16gray 4 B800 EGA + = T 80x25 8x16 16 4 B800 MCGA + = T 80x25 9x16 16 4 B800 VGA + 03h = T 80x25 8x14 16 4 B800 EGA + = T 80x25 8x16 16 4 B800 MCGA + = T 80x25 9x16 16 4 B800 VGA + 04h = G 40x25 8x8 320x200 4 B800 CGA,PCjr,EGA,MCGA,VGA + 05h = G 40x25 8x8 320x200 4gray B800 CGA,PCjr,EGA + = G 40x25 8x8 320x200 4 B800 MCGA,VGA + 06h = G 80x25 8x8 640x200 2 B800 CGA,PCjr,EGA,MCGA,VGA + 07h = T 80x25 9x14 mono var B000 MDA,Hercules,EGA + = T 80x25 9x16 mono B000 VGA + 0Bh = reserved (used internally by EGA BIOS) + 0Ch = reserved (used internally by EGA BIOS) + 0Dh = G 40x25 8x8 320x200 16 8 A000 EGA,VGA + 0Eh = G 80x25 8x8 640x200 16 4 A000 EGA,VGA + 0Fh = G 80x25 8x14 640x350 mono 2 A000 EGA,VGA + 10h = G 80x25 8x14 640x350 4 2 A000 64k EGA + = G 640x350 16 A000 256k EGA,VGA + 11h = G 80x30 8x16 640x480 mono A000 VGA,MCGA,ATI EGA,ATI VIP + 12h = G 80x30 8x16 640x480 16/256k A000 VGA,ATI VIP + = G 80x30 8x16 640x480 16/64 A000 ATI EGA Wonder + 13h = G 40x25 8x8 320x200 256/256k A000 VGA,MCGA,ATI VIP +----------1001------------------------------- +INT 10 - VIDEO - SET TEXT-MODE CURSOR SHAPE + AH = 01h + CH = bit 7 should be zero + bits 6,5 cursor blink + (00=normal, 01=invisible, 10=erratic, 11=slow) + (00=normal, other=invisible on EGA/VGA) + bits 4-0 top scan line containing cursor + CL = bottom scan line containing cursor (bits 0-4) +Notes: buggy on EGA systems--BIOS remaps cursor shape in 43 line modes, but + returns unmapped cursor shape + applications which wish to change the cursor by programming the + hardware directly on EGA or above should call INT 10/AX=1130h or + read 0040h:0085h first to determine the current font height +BUG: AMI 386 BIOS and AST Premier 386 BIOS will lock up the system if AL + is not equal to the current video mode +SeeAlso: AH=03h,AX=CD05h +----------1002------------------------------- +INT 10 - VIDEO - SET CURSOR POSITION + AH = 02h + BH = page number + 0-3 in modes 2&3 + 0-7 in modes 0&1 + 0 in graphics modes + DH = row (00h is top) + DL = column (00h is left) +SeeAlso: AH=03h,AH=05h +----------1003------------------------------- +INT 10 - VIDEO - GET CURSOR POSITION AND SIZE + AH = 03h + BH = page number + 0-3 in modes 2&3 + 0-7 in modes 0&1 + 0 in graphics modes +Return: AX = 0000h (Phoenix BIOS) + CH = start scan line + CL = end scan line + DH = row (00h is top) + DL = column (00h is left) +Notes: a separate cursor is maintained for each of up to 8 display pages + many ROM BIOSes incorrectly return the default size for a color display + (start 06h, end 07h) when a monochrome display is attached +SeeAlso: AH=01h,AH=02h +----------1004------------------------------- +INT 10 - VIDEO - READ LIGHT PEN POSITION (EGA Only) + AH = 04h +Return: AH = light pen trigger flag + 00h not down/triggered + 01h down/triggered + DH,DL = row,column of character light pen is on + CH = pixel row (graphics modes 04h-06h) + CX = pixel row (graphics modes with >200 rows) + BX = pixel column +Notes: on a CGA, returned column numbers are always multiples of 2 (320- + column modes) or 4 (640-column modes) + returned row numbers are only accurate to two lines +----------1005------------------------------- +INT 10 - VIDEO - SELECT ACTIVE DISPLAY PAGE + AH = 05h + AL = new page number (00h to number of pages - 1) (see AH=00h) +SeeAlso: AH=0Fh +----------1006------------------------------- +INT 10 - VIDEO - SCROLL UP WINDOW + AH = 06h + AL = number of lines by which to scroll up (00h = clear entire window) + BH = attribute used to write blank lines at bottom of window + CH,CL = row,column of window's upper left corner + DH,DL = row,column of window's lower right corner +Note: affects only the currently active page (see AH=05h) +Warning: some implementations have a bug which destroys BP +SeeAlso: AH=07h,AH=72h,AH=73h +----------1007------------------------------- +INT 10 - VIDEO - SCROLL DOWN WINDOW + AH = 07h + AL = number of lines by which to scroll down (00h=clear entire window) + BH = attribute used to write blank lines at top of window + CH,CL = row,column of window's upper left corner + DH,DL = row,column of window's lower right corner +Note: affects only the currently active page (see AH=05h) +Warning: some implementations have a bug which destroys BP +SeeAlso: AH=06h,AH=72h,AH=73h +----------1008------------------------------- +INT 10 - VIDEO - READ CHARACTER AND ATTRIBUTE AT CURSOR POSITION + AH = 08h + BH = page number (00h to number of pages - 1) (see AH=00h) +Return: AH = attribute + bit 7: blink + bits 6-4: background color + 000 black + 001 blue + 010 green + 011 cyan + 100 red + 101 magenta + 110 brown + 111 white + bits 3-0: foreground color + 0000 black 1000 dark gray + 0001 blue 1001 light blue + 0010 green 1010 light green + 0011 cyan 1011 light cyan + 0100 red 1100 light red + 0101 magenta 1101 light magenta + 0110 brown 1110 yellow + 0111 light gray 1111 white + AL = character +Notes: for monochrome displays, a foreground of 1 with background 0 is underlined + the blink bit may be reprogrammed to enable intense background colors + using AX=1003h or by programming the CRT controller +SeeAlso: AH=09h,AX=1003h +----------1009------------------------------- +INT 10 - VIDEO - WRITE CHARACTER AND ATTRIBUTE AT CURSOR POSITION + AH = 09h + AL = character to display + BH = page number (00h to number of pages - 1) (see AH=00h) + BL = attribute (text mode) or color (graphics mode) + if bit 7 set in graphics mode, character is xor'ed onto screen + CX = number of times to write character +Notes: all characters are displayed, including CR, LF, and BS + replication count in CX may produce an unpredictable result in graphics + modes if it is greater than the number of positions remaining in the + current row +SeeAlso: AH=08h,AH=0Ah,AH=4Bh,INT 17/AH=60h,INT 1F,INT 43,INT 44 +----------100A------------------------------- +INT 10 - VIDEO - WRITE CHARACTER ONLY AT CURSOR POSITION + AH = 0Ah + AL = character to display + BH = page number (00h to number of pages - 1) (see AH=00h) + BL = attribute (PCjr only) or color (graphics mode) + if bit 7 set in graphics mode, character is xor'ed onto screen + CX = number of times to write character +Notes: all characters are displayed, including CR, LF, and BS + replication count in CX may produce an unpredictable result in graphics + modes if it is greater than the number of positions remaining in the + current row +SeeAlso: AH=08h,AH=09h,AH=4Bh,INT 17/AH=60h,INT 1F,INT 43,INT 44 +----------100B--BH00------------------------- +INT 10 - VIDEO - SET BACKGROUND/BORDER COLOR + AH = 0Bh + BH = 00h + BL = background/border color (border only in text modes) +SeeAlso: AH=0Bh/BH=01h +----------100B--BH01------------------------- +INT 10 - VIDEO - SET PALETTE + AH = 0BH + BH = 01h + BL = palette ID + 00h background, green, red, and brown/yellow + 01h background, cyan, magenta, and white +SeeAlso: AH=0Bh/BH=00h +----------100C------------------------------- +INT 10 - VIDEO - WRITE GRAPHICS PIXEL + AH = 0Ch + BH = page number + AL = pixel color (if bit 7 set, value is xor'ed onto screen) + CX = column + DX = row +Notes: valid only in graphics modes + BH is ignored if the current video mode supports only one page +SeeAlso: AH=0Dh,AH=46h +----------100D------------------------------- +INT 10 - VIDEO - READ GRAPHICS PIXEL + AH = 0Dh + BH = page number + CX = column + DX = row +Return: AL = pixel color +Notes: valid only in graphics modes + BH is ignored if the current video mode supports only one page +SeeAlso: AH=0Ch,AH=47h +----------100E------------------------------- +INT 10 - VIDEO - TELETYPE OUTPUT + AH = 0Eh + AL = character to write + BH = page number + BL = foreground color (graphics modes only) +Notes: characters 07h (BEL), 08h (BS), 0Ah (LF), and 0Dh (CR) are interpreted + and do the expected things + IBM PC ROMs dated 4/24/81 and 10/19/81 require that BH be the same as + the current active page +SeeAlso: AH=02h,AH=0Ah +----------100F------------------------------- +INT 10 - VIDEO - GET CURRENT VIDEO MODE + AH = 0Fh +Return: AH = number of character columns + AL = display mode (see AH=00h) + BH = active page (see AH=05h) +Notes: if mode was set with bit 7 set ("no blanking"), the returned mode will + also have bit 7 set + EGA, VGA, and UltraVision return either AL=03h (color) or AL=07h + (monochrome) in all extended-row text modes +SeeAlso: AH=00h,AH=05h,AX=1130h,AX=CD04h +----------101000---------------------------- +INT 10 - VIDEO - SET SINGLE PALETTE REGISTER (PCjr,EGA,MCGA,VGA) + AX = 1000h + BL = palette register number (00h-0Fh) + = attribute register number (undocumented) + 10h attribute mode control register (should let BIOS control this) + 11h overscan color register (see also AX=1001h) + 12h color plane enable register (bits 3-0 enable corresponding + text attribute bit) + 13h horizontal PEL panning register + 14h color select register + BH = color or attribute register value +Notes: on MCGA, only BX = 0712h is supported + under UltraVision, the palette locking status (see AX=CD01h) + determines the outcome +SeeAlso: AX=1002h,AX=1007h,AX=CD01h +----------101001----------------------------- +INT 10 - VIDEO - SET BORDER (OVERSCAN) COLOR (PCjr,EGA,VGA) + AX = 1001h + BH = border color (00h-3Fh) +BUG: the original IBM VGA BIOS incorrectly updates the parameter save area + and places the border color at offset 11h of the palette table + rather than offset 10h +Note: under UltraVision, the palette locking status (see AX=CD01h) + determines the outcome +SeeAlso: AX=1002h,AX=1008h,AX=CD01h +----------101002----------------------------- +INT 10 - VIDEO - SET ALL PALETTE REGISTERS (PCjr,EGA,VGA) + AX = 1002h + ES:DX -> palette register list +Note: under UltraVision, the palette locking status (see AX=CD01h) + determines the outcome +SeeAlso: AX=1000h,AX=1001h,AX=1009h,AX=CD01h + +Format of palette register list: +Offset Size Description + 00h 16 BYTEs colors for palette registers 00h through 0Fh + 10h BYTE border color +----------101003----------------------------- +INT 10 - VIDEO - TOGGLE INTENSITY/BLINKING BIT (Jr, PS, TANDY 1000, EGA, VGA) + AX = 1003h + BL = new state + 00h background intensity enabled + 01h blink enabled +Note: although there is no function to get the current status, bit 5 of + 0040h:0065h indicates the state +SeeAlso: AH=08h +----------101007----------------------------- +INT 10 - VIDEO - GET INDIVIDUAL PALETTE REGISTER (VGA,UltraVision v2+) + AX = 1007h + BL = palette or attribute (undoc) register number (see AX=1000h) +Return: BH = palette or attribute register value +Notes: UltraVision v2+ supports this function even on color EGA systems in + video modes 00h-03h, 10h, and 12h; direct programming of the palette + registers will cause incorrect results because the EGA registers are + write-only. To guard against older versions or unsupported video + modes, programs which expect to use this function on EGA systems + should set BH to FFh on entry. +SeeAlso: AX=1000h,AX=1009h +----------101008----------------------------- +INT 10 - VIDEO - READ OVERSCAN (BORDER COLOR) REGISTER (VGA,UltraVision v2+) + AX = 1008h +Return: BH = border color (00h-3Fh) +Notes: UltraVision v2+ supports this function even on color EGA systems in + video modes 00h-03h, 10h, and 12h; direct programming of the palette + registers will cause incorrect results because the EGA registers are + write-only. To guard against older versions or unsupported video + modes, programs which expect to use this function on EGA systems + should set BH to FFh on entry. +SeeAlso: AX=1001h +----------101009----------------------------- +INT 10 - VIDEO - READ ALL PALETTE REGISTERS AND OVERSCAN REGISTER (VGA) + AX = 1009h + ES:DX -> 17-byte buffer (see AX=1002h) +Notes: UltraVision v2+ supports this function even on color EGA systems in + video modes 00h-03h, 10h, and 12h; direct programming of the palette + registers will cause incorrect results because the EGA registers are + write-only. To guard against older versions or unsupported video + modes, programs which expect to use this function on EGA systems + should set the ES:DX buffer to FFh before calling. +SeeAlso: AX=1002h,AX=1007h,AX=CD02h +----------101010----------------------------- +INT 10 - VIDEO - SET INDIVIDUAL DAC REGISTER (VGA/MCGA) + AX = 1010h + BX = register number + CH = new value for green (0-63) + CL = new value for blue (0-63) + DH = new value for red (0-63) +SeeAlso: AX=1012h,AX=1015h +----------101012----------------------------- +INT 10 - VIDEO - SET BLOCK OF DAC REGISTERS (VGA/MCGA) + AX = 1012h + BX = starting color register + CX = number of registers to set + ES:DX -> table of 3*CX bytes where each 3 byte group represents one + byte each of red, green and blue (0-63) +SeeAlso: AX=1010h,AX=1017h +----------101013----------------------------- +INT 10 - VIDEO - SELECT VIDEO DAC COLOR PAGE (VGA) + AX = 1013h + BL = subfunction + 00h select paging mode + BH = 00h select 4 blocks of 64 + BH = 01h select 16 blocks of 16 + 01h select page + BH = page number (00h to 03h) or (00h to 0Fh) +Note: not valid in mode 13h +SeeAlso: AX=101Ah +----------101015----------------------------- +INT 10 - VIDEO - READ INDIVIDUAL DAC REGISTER (VGA/MCGA) + AX = 1015h + BL = palette register number +Return: DH = red value + CH = green value + CL = blue value +SeeAlso: AX=1010h,AX=1017h +----------101017----------------------------- +INT 10 - VIDEO - READ BLOCK OF DAC REGISTERS (VGA/MCGA) + AX = 1017h + BX = starting palette register + CX = number of palette registers to read + ES:DX -> buffer (3 * CX bytes in size) (see also AX=1012h) +Return: buffer filled with CX red, green and blue triples +SeeAlso: AX=1012h,AX=1015h +----------101018----------------------------- +INT 10 - VIDEO - undocumented - SET PEL MASK (VGA/MCGA) + AX = 1018h + BL = new PEL value +SeeAlso: AX=1019h +----------101019----------------------------- +INT 10 - VIDEO - undocumented - READ PEL MASK (VGA/MCGA) + AX = 1019h +Return: BL = value read +SeeAlso: AX=1018h +----------10101A----------------------------- +INT 10 - VIDEO - GET VIDEO DAC COLOR-PAGE STATE (VGA) + AX = 101Ah +Return: BL = paging mode + 00h four pages of 64 + 01h sixteen pages of 16 + BH = current page +SeeAlso: AX=1013h +----------10101B----------------------------- +INT 10 - VIDEO - PERFORM GRAY-SCALE SUMMING (VGA/MCGA) + AX = 101Bh + BX = starting palette register + CX = number of registers to convert +SeeAlso: AH=12h/BL=33h +----------1011------------------------------- +INT 10 - VIDEO - TEXT-MODE CHARACTER GENERATOR FUNCTIONS (PS, EGA, VGA) + AH = 11h +The following functions will cause a mode set, completely resetting +the video environment, but without clearing the video buffer + AL = 00h, 10h: load user-specified patterns + ES:BP -> user table + CX = count of patterns to store + DX = character offset into map 2 block + BL = block to load in map 2 + BH = number of bytes per character pattern + AL = 01h, 11h: load ROM monochrome patterns (8 by 14) + BL = block to load + AL = 02h, 12h: load ROM 8 by 8 double-dot patterns + BL = block to load + AL = 03h: set block specifier + BL = block specifier + (EGA/MCGA) bits 0,1 = block selected by chars with attribute bit 3=0 + bits 2,3 = block selected by chars with attribute bit 3=1 + (VGA) bits 0,1,4 = block selected by attribute bit 3 = 0 + bits 2,3,5 = block selected by attribute bit 3 = 1 + AL = 04h, 14h: load ROM 8x16 character set (VGA) + BL = block to load +The routines called with AL=1xh are designed to be called only +immediately after a mode set and are similar to the routines called +with AL=0xh, except that: + Page 0 must be active. + Bytes/character is recalculated. + Max character rows is recalculated. + CRT buffer length is recalculated. + CRTC registers are reprogrammed as follows: + R09 = bytes/char-1 ; max scan line (mode 7 only) + R0A = bytes/char-2 ; cursor start + R0B = 0 ; cursor end + R12 = ((rows+1)*(bytes/char))-1 ; vertical display end + R14 = bytes/char ; underline loc + (*** BUG: should be 1 less ***) +SeeAlso: AX=CD10h +----------1011------------------------------- +INT 10 - VIDEO - GRAPHICS-MODE CHARACTER GENERATOR FUNCTIONS (PS, EGA, VGA) + AH = 11h + AL = 20h: set user 8 by 8 graphics characters (INT 1F) + ES:BP -> user table + AL = 21h: set user graphics characters + ES:BP -> user table + CX = bytes per character + BL = row specifier + 00h user set + DL = number of rows + 01h 14 rows + 02h 25 rows + 03h 43 rows + AL = 22h: ROM 8 by 14 set + BL = row specifier (see above) + AL = 23h: ROM 8 by 8 double dot + BL = row specifier (see above) + AL = 24h: load 8x16 graphics characters (VGA/MCGA) + BL = row specifier (see above) + AL = 29h: load 8x16 graphics characters (Compaq Systempro) + BL = row specifier (see above) +Notes: these functions are meant to be called only after a mode set + UltraVision v2+ sets INT 43 to the appropriate font for AL=22h,23h,24h, + and 29h +SeeAlso: INT 1F, INT 43 +----------101130----------------------------- +INT 10 - VIDEO - GET FONT INFORMATION (EGA, MCGA, VGA) + AX = 1130h + BH = pointer specifier + 00h INT 1Fh pointer + 01h INT 43h pointer + 02h ROM 8x14 character font pointer + 03h ROM 8x8 double dot font pointer + 04h ROM 8x8 double dot font (high 128 characters) + 05h ROM alpha alternate (9 by 14) pointer (EGA,VGA) + 06h ROM 8x16 font (MCGA, VGA) + 07h ROM alternate 9x16 font (VGA only) + 11h (UltraVision v2+) 8x20 font (VGA) or 8x19 font (autosync EGA) + 12h (UltraVision v2+) 8x10 font (VGA) or 8x11 font (autosync EGA) +Return: ES:BP = specified pointer + CX = bytes/character + DL = character rows on screen - 1 +Note: for UltraVision v2+, the 9xN alternate fonts follow the corresponding + 8xN font at ES:BP+256N +SeeAlso: AX=1100h,AX=1120h,INT 1F,INT 43 +----------1012--BL10------------------------- +INT 10 - VIDEO - ALTERNATE FUNCTION SELECT (PS, EGA, VGA, MCGA) - GET EGA INFO + AH = 12h + BL = 10h +Return: BH = 00h color mode in effect (I/O port 3Dxh) + 01h mono mode in effect (I/O port 3Bxh) + BL = 00h 64k bytes memory installed + 01h 128k bytes memory installed + 02h 192k bytes memory installed + 03h 256k bytes memory installed + CH = feature bits + CL = switch settings +----------1012--BL20------------------------- +INT 10 - VIDEO - ALTERNATE FUNCTION SELECT (PS,EGA,VGA,MCGA) - ALTERNATE PRTSC + AH = 12h + BL = 20h select alternate print screen routine +Notes: installs a PrtSc routine from the video card's BIOS to replace the + default PrtSc handler from the ROM BIOS, which usually does not + understand screen heights other than 25 lines + some adapters disable print-screen instead of enhancing it +SeeAlso: INT 05 +----------1012--BL30------------------------- +INT 10 - VIDEO - ALTERNATE FUNCTION SELECT (VGA) - SELECT VERTICAL RESOLUTION + AH = 12h + BL = 30h + AL = vertical resolution + 00h 200 scan lines + 01h 350 scan lines + 02h 400 scan lines +Return: AL = 12h if function supported +----------1012--BL31------------------------- +INT 10 - VIDEO - ALTERNATE FUNCTION SELECT (VGA, MCGA) - PALETTE LOADING + AH = 12h + BL = 31h + AL = 00h enable default palette loading + 01h disable default palette loading +Return: AL = 12h if function supported +----------1012--BL32------------------------- +INT 10 - VIDEO - ALTERNATE FUNCTION SELECT (VGA, MCGA) - VIDEO ADDRESSING + AH = 12h + BL = 32h + AL = 00h enable video addressing + 01h disable video addressing +Return: AL = 12h if function supported +----------1012--BL33------------------------- +INT 10 - VIDEO - ALTERNATE FUNCTION SELECT (VGA, MCGA) - GRAY-SCALE SUMMING + AH = 12h + BL = 33h + AL = 00h enable gray scale summing + 01h disable gray scale summing +Return: AL = 12h if function supported +SeeAlso: AX=101Bh,AX=BF06h +----------1012--BL34------------------------- +INT 10 - VIDEO - ALTERNATE FUNCTION SELECT (VGA) - CURSOR EMULATION + AH = 12h + BL = 34h + AL = 00h enable alphanumeric cursor emulation + 01h disable alphanumeric cursor emulation +Return: AL = 12h if function supported +----------1012--BL35------------------------- +INT 10 - VIDEO - ALTERNATE FUNCTION SELECT (PS) - DISPLAY-SWITCH INTERFACE + AH = 12h + BL = 35h + AL = 00h initial adapter video off + 01h initial planar video on + 02h switch active video off + 03h switch inactive video on + 80h *UNDOCUMENTED* set system board video active flag + ES:DX -> buffer (128 byte save area if AL = 0, 2 or 3) +Return: AL = 12h if function supported +----------1012--BL36------------------------- +INT 10 - VIDEO - ALTERNATE FUNCTION SELECT (PS, VGA) - VIDEO REFRESH CONTROL + AH = 12h + BL = 36h + AL = 00h enable refresh + 01h disable refresh +Return: AL = 12h if function supported +----------1013------------------------------- +INT 10 - VIDEO - WRITE STRING (AT and later,EGA) + AH = 13h + AL = write mode + bit 0: update cursor after writing + 1: string contains alternating characters and attributes + BH = page number + BL = attribute if string contains only characters + CX = number of characters in string + DH,DL = row,column at which to start writing + ES:BP -> string to write +Notes: recognizes CR, LF, BS, and bell + also available PC or XT with EGA or higher + HP 95LX only supports write mode 00h +BUG: on the IBM VGA Adapter, any scrolling which may occur is performed on + the active page rather than the requested page +SeeAlso: AH=09h,AH=0Ah +----------101A------------------------------- +INT 10 - VIDEO - DISPLAY COMBINATION (PS,VGA/MCGA) + AH = 1Ah + AL = 00h read display combination code +Return: BL = active display code (see below) + BH = alternate display code + 01h set display combination code + BL = active display code (see below) + BH = alternate display code +Return: AL = 1Ah if function was supported + +Values for display combination code: + 00h no display + 01h monochrome adapter w/ monochrome display + 02h CGA w/ color display + 03h reserved + 04h EGA w/ color display + 05h EGA w/ monochrome display + 06h PGA w/ color display + 07h VGA w/ monochrome analog display + 08h VGA w/ color analog display + 09h reserved + 0Ah MCGA w/ digital color display + 0Bh MCGA w/ monochrome analog display + 0Ch MCGA w/ color analog display + FFh unknown display type +----------101B------------------------------- +INT 10 - VIDEO - FUNCTIONALITY/STATE INFORMATION (PS,VGA/MCGA) + AH = 1Bh + BX = implementation type + 0000h return functionality/state information + ES:DI -> 64 byte buffer for state information (see below) +Return: AL = 1Bh if function supported + ES:DI buffer filled with state information +SeeAlso: AH=15h + +Format of state information: +Offset Size Description + 00h DWORD address of static functionality table (see below) + 04h BYTE video mode in effect + 05h WORD number of columns + 07h WORD length of regen buffer in bytes + 09h WORD starting address of regen buffer + 0Bh WORD cursor position for page 0 + 0Dh WORD cursor position for page 1 + 0Fh WORD cursor position for page 2 + 11h WORD cursor position for page 3 + 13h WORD cursor position for page 4 + 15h WORD cursor position for page 5 + 17h WORD cursor position for page 6 + 19h WORD cursor position for page 7 + 1Bh WORD cursor type + 1Dh BYTE active display page + 1Eh WORD CRTC port address + 20h BYTE current setting of register (3?8) + 21h BYTE current setting of register (3?9) + 22h BYTE number of rows + 23h WORD bytes/character + 25h BYTE display combination code of active display + 26h BYTE DCC of alternate display + 27h WORD number of colors supported in current mode + 29h BYTE number of pages supported in current mode + 2Ah BYTE number of scan lines active + (0,1,2,3) = (200,350,400,480) + 2Bh BYTE primary character block + 2Ch BYTE secondary character block + 2Dh BYTE miscellaneous flags + bit 0 all modes on all displays on + 1 gray summing on + 2 monochrome display attached + 3 default palette loading disabled + 4 cursor emulation enabled + 5 0 = intensity; 1 = blinking + 6 PS/2 P70 plasma display (without 9-dot wide font) active + 7 reserved + 2Eh 3 BYTEs reserved (00h) + 31h BYTE video memory available + 00h = 64K, 01h = 128K, 02h = 192K, 03h = 256K + 32h BYTE save pointer state flags + bit 0 512 character set active + 1 dynamic save area present + 2 alpha font override active + 3 graphics font override active + 4 palette override active + 5 DCC override active + 6 reserved + 7 reserved + 33h 13 BYTEs reserved (00h) + +Format of Static Functionality Table: +Offset Size Description + 00h BYTE modes supported #1 + bit 0 to bit 7 = 1 modes 0,1,2,3,4,5,6 supported + 01h BYTE modes supported #2 + bit 0 to bit 7 = 1 modes 8,9,0Ah,0Bh,0Ch,0Dh,0Eh,0Fh supported + 02h BYTE modes supported #3 + bit 0 to bit 3 = 1 modes 10h,11h,12h,13h supported + bit 4 to bit 7 reserved + 03h 4 BYTEs reserved + 07h BYTE scan lines supported + bit 0 to bit 2 = 1 if scan lines 200,350,400 supported + 08h BYTE total number of character blocks available in text modes + 09h BYTE maximum number of active character blocks in text modes + 0Ah BYTE miscellaneous function flags #1 + bit 0 all modes on all displays function supported + 1 gray summing function supported + 2 character font loading function supported + 3 default palette loading enable/disable supported + 4 cursor emulation function supported + 5 EGA palette present + 6 color palette present + 7 color paging function supported + 0Bh BYTE miscellaneous function flags #2 + bit 0 light pen supported + 1 save/restore state function 1Ch supported + 2 intensity blinking function supported + 3 Display Combination Code supported + 4-7 reserved + 0Ch WORD reserved + 0Eh BYTE save pointer function flags + bit 0 512 character set supported + 1 dynamic save area supported + 2 alpha font override supported + 3 graphics font override supported + 4 palette override supported + 5 DCC extension supported + 6 reserved + 7 reserved + 0Fh BYTE reserved +----------101C------------------------------- +INT 10 - VIDEO - SAVE/RESTORE VIDEO STATE (PS50+,VGA) + AH = 1Ch + AL = 00h return state buffer size +Return: BX = number of 64-byte blocks needed + 01h save video state + ES:BX -> buffer + 02h restore video state + ES:BX -> buffer containing previously saved state + CX = requested states + bit 0 video hardware + 1 BIOS data areas + 2 color registers and DAC state + 3-15 reserved +Return: AL = 1Ch if function supported diff --git a/16/tweak16/MODES.DOC b/16/tweak16/MODES.DOC new file mode 100755 index 00000000..1d9df85a --- /dev/null +++ b/16/tweak16/MODES.DOC @@ -0,0 +1,99 @@ +The modes provided with TWEAK range from the obscure to the useful. +This file has some hints and some vital information. + +First of all, a small warning: + +All mode files with an 's' at the and of the name (for example +800x600s.16) use special dot clocks available on my Chips & +Technologies 80c451 SVGA card. Feel free to try them on your card, but +don't expect them to work on a vanilla VGA. + +Modes with a 'c' at the end of the name are chained modes, to +distinguish them from unchained modes of the same resolution. + +Then, some info about modes of particular interest: + +256x256c.256 - The chained Mode Q: + o 256x256 in 256 colors + o exactly 1 page, uses every single byte of the video segment + o 1-to-1 linear pixel-to-address mapping, like mode 13h + o keep (x,y) coordinates in a single word, and use that word as + an offset. (Both x and y fit in a byte!) No more MULs! + o I named it 'Mode Q' for 256-cubed (256x256x256 = 256^3). + +256x256.256 - The unchained Mode Q: + o 256x256 in 256 colors + o exactly 4 pages + o 4-to-1 planar mapping, like Mode X + +The 256-column modes have been provided in several other vertical +resolutions: 224 and 240 lines + +400x600.256 - new, more stable version + o 400x600 in 256 colors (unchained) + o 1 page + 22144 bytes (55.36 lines) + o 4-to-1 planar mapping + o good multisync monitor is still required + +400x300.256 - New square aspect ratio mode + o 400x300 in 256 colors (unchained) + o That means a square aspect ratio if stretched to fill the screen! + o 2 pages + 22144 bytes (55.36 lines) + o 4-to-1 planar mapping + o NOT based on the above 400x600 mode! Uses the lowest vertical + frequency, and should thus prove much more stable than the + 600-line mode. + +360x360.256 + o Interesting mode, which should work on most VGAs. + +360x270.256 + o New square aspect ratio mode + + +Known problems: +--------------- + o The 400x-modes won't work on LCDs and similar equipment + + o They also fail (won't synchronize) on cheap, basic VGA monitors + like the Samsung I used to have. I think your monitor must + support SVGA resolutions of 800x600x16 and up for the 400x-modes + to work. Your card can probably be plain, vanilla VGA though! + + o Don't expect the modes to line up perfectly with your monitor + screen's edges! You might have to adjust the size and position of + the image with your monitor's control knobs. + +I have yet to see a VGA setup which doesn't support Mode Q. Let me +know if you have trouble. + + +Disclaimer: +----------- +I can't guarantee that any of the above modes will be compatible with +your VGA card. I will accept no responsibility for damages arising +from the use or abuse of the files included in this archive. + +If any of the above modes don't work on your configuration, send me +an email stating the name/chipset of your (S)VGA card, and monitor +type. I'm especially interested in any changes you could make to get +them to work! Also mail me comments and suggestions to the TWEAK +archive. I will probably release a new version by the end of the +summer. Current ideas include: + + o A tutorial on tweaking in general, with focus on unchained, 256 + color modes. I ought to explain the significance of all timing + registers, and their relevance for the resulting resolution. + o A program which takes as input a description of a screen mode + (i.e. resolution, colors) and outputs a list of suggested + registers settings. + o A method of linking TWEAKed 256-color modes to Themie Gouthas' XLIB. + o Context sensitive help on most registers and their individual bits + within the TWEAK utility. + o Support for assembler and Pascal output. + + +Regards from +Robert Schmidt of Ztiff Zox Softwear, Norway + +e-mail: robert@stud.unit.no diff --git a/16/tweak16/NAMEDREG.CPP b/16/tweak16/NAMEDREG.CPP new file mode 100755 index 00000000..ed10527b --- /dev/null +++ b/16/tweak16/NAMEDREG.CPP @@ -0,0 +1,52 @@ +/* + NamedReg.CPP version 1.0 + by Robert Schmidt of Ztiff Zox Softwear 1993 + + Defines the member functions of the NamedRegister class declared in + Register.hpp. + Defines the stream operator >> to read named register info from + an istream. (Text mode) +*/ + +#include +#include +#include +#include "Screen.hpp" +#include "Register.hpp" + + +// NamedRegister::printCon() prints the register state to the console. +// If enableFlag is zero, the value is omitted from the display, and +// its place is filled with spaces. + +void NamedRegister::printCon() + { + textattr(enableFlag?REGENABLE_COLOR:REGDISABLE_COLOR); + cprintf("%03hx (%02hx) %24s : %02hx", getPort(), getIndex(), + name, getValue()); + } + +/* + This operator reads the register port number, index and name from the + input stream. (*Not* the value!) Used for initializing each element + in the register table used by TWEAK. +*/ + +istream& operator>> (istream &in, NamedRegister &r) + { + int i; + char *n = new char[128]; + + in >> hex >> i; + r.setPort(i); + in >> i >> ws; + r.setIndex((unsigned char)(i)); + in.getline(n, 128); + n[in.gcount()-1] = '\0'; + r.name = new char[strlen(n)+1]; + strcpy(r.name, n); + delete[] n; + + return in; + } + diff --git a/16/tweak16/REGEDIT.CPP b/16/tweak16/REGEDIT.CPP new file mode 100755 index 00000000..f5cbef62 --- /dev/null +++ b/16/tweak16/REGEDIT.CPP @@ -0,0 +1,70 @@ +/* + RegEdit.HPP + +*/ + +#include +#include "Screen.hpp" +#include "RegEdit.HPP" + + +RegisterEditor::RegisterEditor(istream &ins) + : RegisterTable(ins) + { + prevSel = select = 0; + } + +void RegisterEditor::printCon(int r) + { + // This gotoxy divides the registers into two columns. + gotoxy(40*(r / editHeight) +1, r % editHeight +1); + // Optionally print the left cursor. + textattr(CURSOR_COLOR); + cprintf(r==select ? "\20" : " "); + // Then put out the meat. + reg[r].printCon(); + // And possibly the right cursor. + textattr(CURSOR_COLOR); + cprintf(r==select ? "\21" : " "); + // This gotoxy just puts the hardware cursor where it won't distract you. + gotoxy(40*(r / editHeight)+38, r % editHeight +1); + } + +void RegisterEditor::printAllCon() + { + for (int r = 0; r < registers; r++) + printCon(r); + } + +int RegisterEditor::updateSelect() + { + if (select < 0) + select = registers - 1; + else + if (select >= registers) + select = 0; + if (prevSel != select) + { + printCon(prevSel); + prevSel = select; + } + printCon(select); + return select; + } + + +// RegisterEditor::showBitMask() updates the bit pattern display with +// the value of selected register. This is TWEAK specific. + +void RegisterEditor::showBitMask() + { + gotoxy(42,editHeight-4); + textattr(BITHEADER_COLOR); + cprintf("Bit mask: 7 6 5 4 3 2 1 0"); + gotoxy(51,editHeight-3); + textattr(BITPATTERN_COLOR); + unsigned char v = reg[select].getValue(); + for (int e=7; e>=0; e--) + cprintf( v&(1<> and << to read and write register + info from istreams/to ostreams in *binary* format. +*/ + +#include +#include +#include "Register.hpp" + + +/* + Register::out() + Outputs the Register.value to the correct port/index. + It takes care of handling recognized special cases, like some + VGA ports, correctly. +*/ + +void Register::out() + { + switch (port) + { + // First handle special cases: + + case ATTRCON_ADDR: + inportb(STATUS_ADDR); // reset read/write flip-flop + outportb(ATTRCON_ADDR, index); + outportb(ATTRCON_ADDR, value); + break; + + case SEQ_ADDR: + if (index == 1) + { + // Reset the sequencer if the clock polarity settings + // are being accessed. + outport(SEQ_ADDR, 0x0100); + outport(SEQ_ADDR, value<<8 | 1); + outport(SEQ_ADDR, 0x0300); + break; + } + case GRACON_ADDR: + case CRTC_ADDR: + case CHIPSTECH: + outport(port, index | value<<8); + break; + + case MISC_ADDR: + case VGAENABLE_ADDR: + default: // Default is to write the byte + outportb(port, value); // directly to the port + break; + } + } + +/* + Register::in() + Inputs Register.value to the associated hardware register. + It takes care of handling recognized special cases, + like some VGA ports, correctly. +*/ + +unsigned char Register::in() + { + switch (port) + { + // First handle special cases: + + case MISC_ADDR: + value = inportb(0x3cc); // 0x3c2 is write-only, reading + // must be mapped to 0x3cc + break; + + case ATTRCON_ADDR: // This 1 is odd. First do a read to + inportb(STATUS_ADDR); // reset the index/data flip-flop. + // Then give it the index, but: + // set bit 5! If cleared, VGA + // output is disabled! + outportb(ATTRCON_ADDR, index); + value = inportb(ATTRCON_ADDR+1); + break; + + case SEQ_ADDR: // These 3 are similar. Give it the + case GRACON_ADDR: // register index, then read the + case CRTC_ADDR: // byte from port+1. + case CHIPSTECH: + outportb(port, index); + value = inportb(port+1); + break; + + case VGAENABLE_ADDR: + default: // Default is to read the byte + value = inportb(port); // directly from the port + break; + } + + return value; // Return value of first reg. + } + +/* + The following stream operators operate on Registers in *binary* + format, i.e. they are not suitable for communicating with text streams + like the keyboard or the screen (cin/cout). +*/ + +istream& operator>> (istream &in, Register &r) + { + r.port = unsigned(in.get()) | (unsigned(in.get()) << 8); + r.index = in.get(); + r.value = in.get(); + + return in; + } + +ostream& operator<< (ostream &out, Register &r) + { + out.put(char(r.port)); + out.put(char(r.port>>8)); + out.put(r.index); + out.put(r.value); + + return out; + } + + + diff --git a/16/tweak16/REGISTER.HPP b/16/tweak16/REGISTER.HPP new file mode 100755 index 00000000..d980df08 --- /dev/null +++ b/16/tweak16/REGISTER.HPP @@ -0,0 +1,91 @@ +/* + Register.hpp version 1.0 + by Robert Schmidt of Ztiff Zox Softwear 1993 + + Declares the Register class, members defined in Register.cpp. +*/ + +#ifndef _Register_HPP +#define _Register_HPP + +#include + +/* + xxxxADDR defines the base port number used to access VGA component xxxx, + and is defined for xxxx = + ATTRCON - Attribute Controller + MISC - Miscellaneous Register + VGAENABLE - VGA Enable Register + SEQ - Sequencer + GRACON - Graphics Controller + CRTC - Cathode Ray Tube Controller + STATUS - Status Register +*/ + +#define ATTRCON_ADDR 0x3c0 +#define MISC_ADDR 0x3c2 +#define VGAENABLE_ADDR 0x3c3 +#define SEQ_ADDR 0x3c4 +#define GRACON_ADDR 0x3ce +#define CRTC_ADDR 0x3d4 +#define STATUS_ADDR 0x3da + +// SVGA specific registers here: + +#define CHIPSTECH 0x3d6 + + +class Register + { + unsigned port; + unsigned char index; + unsigned char value; +public: + Register(unsigned p=0, unsigned char i=0, unsigned char v=0) + { init(p,i,v); } + unsigned char init(unsigned p, unsigned char i, unsigned char v) + { port = p; index = i; return value = v; } + unsigned char init(Register& r) + { port = r.port; index = r.index; return value = r.value; } + void setPort(unsigned p) { port = p; } + void setIndex(unsigned char i) { index = i; } + void setValue(unsigned char v) { value = v; } + unsigned getPort(void) const { return port; } + unsigned char getIndex(void) const { return index; } + unsigned char getValue(void) const { return value; } + unsigned char operator++(void) { return value++; } + unsigned char operator--(void) { return value--; } + unsigned char operator++(int) { return ++value; } + unsigned char operator--(int) { return --value; } + unsigned char &operator *() { return value; } + unsigned char operator=(Register &r) + { return init(r); } + unsigned operator() (int rbit, int len) + { return (value >> rbit) & (1 << len)-1; } + + void out(); + unsigned char in(); + + friend istream& operator>> (istream&, Register&); + friend ostream& operator<< (ostream&, Register&); + }; + + +class NamedRegister : public Register + { + char *name; + char enableFlag; +public: + NamedRegister() { doEnable(); } + ~NamedRegister() { delete name; } + void doEnable() { enableFlag = 1; } + void doDisable() { enableFlag = 0; } + void toggleEnable() { enableFlag = !enableFlag; } + char isEnabled() { return enableFlag; } + char *getName() { return name; } + void printCon(); + + friend istream& operator>> (istream&, NamedRegister&); + }; + +#endif diff --git a/16/tweak16/REGTABLE.CPP b/16/tweak16/REGTABLE.CPP new file mode 100755 index 00000000..d09591fb --- /dev/null +++ b/16/tweak16/REGTABLE.CPP @@ -0,0 +1,123 @@ +/* + RegTable.CPP version 1.0 + by Robert Schmidt of Ztiff Zox Softwear 1993 + + Defines the member and friend functions of the RegisterTable class + declared in RegTable.HPP. +*/ + +#include +//#include +#include "RegTable.hpp" + + +RegisterTable::RegisterTable(istream &ins) + { + // Read number of registers (first number in file) + ins >> registers; + // Allocate enough space + reg = new NamedRegister[registers]; + // Read reg. descriptions + for (int i=0; i> reg[i]; + // Get current register configuration from VGA, and use as default + in(); + } + + +void RegisterTable::in() + { + for (int r = 0; r < registers; r++) + reg[r].in(); + } + +void RegisterTable::out() + { + outportb(0x3d4,0x11); // Ensure CRT regs. 0-7 are writable! + int v = inportb(0x3d5); // That is, clear bit 7 of port + v &= 0x7f; // 0x3D4, index 0x11. + outport(0x3d4,0x11 | (v << 8)); + +// outport(0x3c4, 0x0100); // reset sequencer + + for (int r = 0; r < registers; r++) + if (reg[r].isEnabled()) + reg[r].out(); + +// outport(0x3c4, 0x0300); // re-reset sequencer + outportb(0x3c0, 0x20); // Reenable display data + } + +/* + This istream operator >> reads an entire table of Register values + into 'this' table. + Notes: + The stream is read until good() is no longer true. Not good + practice, but hey! + If the read Register's port and index pair is not found in 'this' + table, it is ignored. + In effect, only the *values* in the table may change after >>, + not port or index numbers. +*/ + +istream& operator>> (istream &in, RegisterTable &t) + { + int r = 0; + t.doDisable(); // first disable all registers + while (in.good()) + { + Register temp; + in >> temp; + + int prevr = r; + + //Search for the correct register position: + while (temp.getPort() != t.reg[r].getPort() || + temp.getIndex() != t.reg[r].getIndex()) + { + if (++r >= t.registers) + r = 0; + if (r == prevr) // Have we looped around once? + goto skip; // Register not supported! + } + // Correct register found, now store the value and enable it. + t.reg[r].setValue(temp.getValue()); + t.reg[r].doEnable(); // enable this single register + skip: + } + return in; + } + + +// This operator << sends all enabled registers in t to the out stream. + +ostream& operator<< (ostream &out, RegisterTable &t) + { + for (int r = 0; r < t.registers; r++) + if (t.reg[r].isEnabled()) + out << Register(t.reg[r]); + return out; + } + +void RegisterTable::doEnable() + { + for (int r=0; r> (istream&, RegisterTable&); + friend ostream& operator<< (ostream&, RegisterTable&); + }; + +#endif \ No newline at end of file diff --git a/16/tweak16/SCREEN.CPP b/16/tweak16/SCREEN.CPP new file mode 100755 index 00000000..c232bdde --- /dev/null +++ b/16/tweak16/SCREEN.CPP @@ -0,0 +1,138 @@ +/* + Screen.CPP version 1.0 + by Robert Schmidt of Ztiff Zox Softwear 1993 + + Defines some primitives for handling the screen, some screen + buffer pointers, and the functions that handle the single + temporary screen used in TWEAK. + +*/ + +#include +#include +#include +#include +#include +#include "Screen.HPP" + +char palette16[16]; +char palette256[768]; + +// editHeight and editWidth hold the dimensions of the editing screen. +// Not everything is formatted according to those horizontally, but +// vertically it should work fine. + +unsigned editMode, editHeight, editWidth, editSize; + +// Now for the screens used in TWEAK. + +// This one points to the standard VGA text screen buffer. textscr[80] +// addresses the first character/attribute pair on the second line +// if the current mode is an 80-column one, for example. + +unsigned *textScr = (unsigned far *)MK_FP(0xb800,0); + +// graphScr points to the standard VGA graphics buffer, being 64Kb. + +char *graphScr = (char far *)MK_FP(0xa000,0); + +// setBiosMode() sets the given standard BIOS mode. + +void setBiosMode(int modeno) + { + _AX = modeno; + geninterrupt(0x10); + } + +// getBiosMode() returns the current BIOS mode. + +int getBiosMode(void) + { + _AH = 0x0f; + geninterrupt(0x10); + return _AL; + } + +// The following two functions saves and restores the temporary screen. +// The tempScr buffer is allocated and destroyed each time. + +void tempBuffer::save(void) + { + if (temp) + delete[] temp; + if (!(temp = new unsigned[editSize])) + { + cout << "Out of memory for swap screen!" << endl; + exit(1); + } + memcpy(temp, link, sizeof(unsigned)*editSize); + } + +void tempBuffer::restore(void) + { + setBiosMode(3); + textmode(editMode); + if (temp) + { + memcpy(link, temp, sizeof(unsigned)*editSize); + delete[] temp; + temp = NULL; + } + } + +void getPalette16() + { + for (int c=0; c<16; c++) + { + outp(0x3c0, 0x20 | c); + palette16[c] = inp(0x3c0); + } + } + +void setEgaPalette(char *p) + { + inp(0x3da); + for (int c=0; c<16; c++) + { + outp(0x3c0, c); + outp(0x3c0, p[c]); + } + outp(0x3c0, 0x20); + } + +void setPalette16() + { + char egaPal[] = {0,1,2,3,4,5,0x14,7,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f}; + setEgaPalette(egaPal); + for (int c=0; c<16; c++) + { + outp(0x3c0, 0x20 | c); + outp(0x3c0, palette16[c]); + } + } + +void getPalette256() + { + outp(0x3c7, 0); + for (int c=0; c<768; c++) + palette256[c] = inp(0x3c9); + } + +void setPalette256() + { + char egaPal[] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; + setEgaPalette(egaPal); + outp(0x3c8, 0); + for (int c=0; c<768; c++) + outp(0x3c9, palette256[c]); + } + +void preparePalettes() + { + int m=getBiosMode(); + setBiosMode(0x13); + getPalette256(); + setBiosMode(0x12); + getPalette16(); + setBiosMode(m); + } \ No newline at end of file diff --git a/16/tweak16/SCREEN.HPP b/16/tweak16/SCREEN.HPP new file mode 100755 index 00000000..569039e1 --- /dev/null +++ b/16/tweak16/SCREEN.HPP @@ -0,0 +1,50 @@ +/* + Screen.HPP version 1.0 + by Robert Schmidt of Ztiff Zox Softwear 1993 + + Declares some primitives for handling the screen, some screen + buffer pointers, and the functions that handle the single + temporary screen used in TWEAK. + + See Screen.CPP for definitions and documentation. +*/ + +#ifndef _Screen_HPP +#define _Screen_HPP + +#include + +#define REGENABLE_COLOR 0x0e +#define REGDISABLE_COLOR 0x07 +#define CURSOR_COLOR 0x0f +#define BITHEADER_COLOR 0x04 +#define BITPATTERN_COLOR 0x0c +#define TESTHEADER_COLOR 0x09 +#define TESTSTRING_COLOR 0x0b +#define PROMPT_COLOR 0x0a +#define ERROR_COLOR 0x8d +#define HELP_COLOR 0x4f +#define INFO_COLOR 0x0f + +extern unsigned editMode, editHeight, editWidth, editSize; + +extern unsigned *textScr; +extern char *graphScr; + +int getBiosMode(void); +void setBiosMode(int); +void preparePalettes(); +void setPalette16(); +void setPalette256(); + +class tempBuffer + { + unsigned *link, *temp; +public: + tempBuffer(unsigned *l) { link = l; temp = NULL; } + ~tempBuffer() { if (temp) delete[] temp; } + void save(void); + void restore(void); + }; + +#endif \ No newline at end of file diff --git a/16/tweak16/TESTPAT.CPP b/16/tweak16/TESTPAT.CPP new file mode 100755 index 00000000..730d1090 --- /dev/null +++ b/16/tweak16/TESTPAT.CPP @@ -0,0 +1,440 @@ +/* + testpat.cpp version 1.6 + by Robert Schmidt of Ztiff Zox Softwear 1993 + + Defines the member functions of the TestPatterns class declared in + testpat.hpp. + + 1.1 + Fixed a couple of bugs in the text mode test. On some computers + it would overwrite data in the C000h segment, if RAM had been mapped + there by QEMM or something similar. + + Modified June 13-14, 1993 by Peter McDermott + The 16 color test pattern has been changed. Now it puts dots from the + upper left hand corner to down the top and left of the screen to the + edges. There is a longer, white dot every 100 pixels. Also, a color + bar is displayed across the page. + + 1.6 + Added support for the mode autodetecting scheme, and for VGALIB, + my mode independant VGA graphics library, to provide more + intelligent test screens. +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include "misc.hpp" +#include "screen.hpp" +#include "vgalib.hpp" +#include "testpat.hpp" +#include "detect.hpp" +#include "screen.hpp" + +extern char *graphScr; +extern unsigned *textScr; +extern unsigned editHeight; + +// These are the text strings identifying each test to the user. + +char *TestPatterns::string[TestPatterns::tests] = + { + "Graphics autodetect", + "Text screen, 16 point", + "Text screen, 8 point", + "4 planes, 16 colors", + "1 plane, 256 colors", + "4 planes, 256 colors" + }; + + +void color16(unsigned char color) // Peter +{ + // load set/reset register with color to be displayed + outport(0x3ce,color<<8); +} + +// following is a point routine for 16 color mode +void init16() // Peter +{ + // default drawing color is white + color16(15); + // load set/reset enable for all display planes + outport(0x3ce,0x0f01); + // load map mask register for all display planes + outport(0x3c4,0x0f02); + // load function select correctly (logical OR) + outport(0x3ce,0x2003); + // set to read mode 0 + outportb(0x3ce,0x05); + int ModeReg=inportb(0x3cf); + outport(0x3ce,ModeReg && 0xf7); // make sure we're in read mode 0 +} + + +void point16(unsigned int x, unsigned int y) // Peter +{ + outportb(0x3d4,0x13); //get screen width in words + unsigned width=inportb(0x3d5)*2; //convert to bytes + // load bitmask register with correct value + outport(0x3ce,(0x80 >> (x % 8) << 8) | 0x08); + // load the latch register with the data already in display memory + _AX=graphScr[y*width+x/8]; + // calculate the position in memory of the pixel to be written + graphScr[y*width+x/8] = 0x00; +} + + +// TestPatterns::run() puts the selected test onto the screen. + +void TestPatterns::run(RegisterTable ®Tab) + { + unsigned a,c; + unsigned long offset; + + regTab.out(); + + outportb(0x3c4,0x02); //get write plane enable + unsigned plane=inportb(0x3c5); + + outportb(0x3d4,0x13); //get screen width in words + unsigned long width=inportb(0x3d5)*2; //convert to bytes + + // Now select the correct initialization method: + + switch (testNo) + { + case test4x16: + case test1x256: + case test4x256: + // All graphics modes: clear the screen, but take care of + // write enabling all planes. + outport(0x3c4,0x0f02); + memset(graphScr, 0, 0xffff); + graphScr[0xffff] = 0; + outportb(0x3c4,0x02); + outportb(0x3c5,plane); + break; + + case testText16: // set 8x16 font + _AX = 0x1104; + _BL = 0; + geninterrupt(0x10); + goto commonText; + case testText8: // set 8x8 font + _AX = 0x1102; + _BL = 0; + geninterrupt(0x10); +commonText: + // Just blank the text screen. + memset(textScr, 0, 8000); + } + + switch (testNo) + { + case autoDetect: + ModeInfo minfo(regTab); + GraphicsAPI *g = minfo.getGraphicsAPI(); + if (!g) + { + setBiosMode(3); + cout << "This is not a graphics mode. Either: -" << endl + << " - Use TAB (->|) to select one of the two " + "available text screens," << endl + << " - Base your mode on one of the BIOS graphics " + "modes, by pressing B and " << endl + << " typing a graphics mode number, for example " + "0x12 or 0x13, or" << endl + << " - Load a graphics mode file by pressing L and " + "typing the name of the file." << endl << endl + << "Now press any key to return to the editor." << endl; + getch(); + } + else + { + g->setColor(0); + g->wipe(); + int width = g->getVirtualWidth(); + int height = g->getVirtualHeight(); + int colors = g->getColors(); + char txt1[40]; + int i, j, maxTick = max(width, height); + + if (g->getColors() == 256) + setPalette256(); + else + setPalette16(); + + for (i = 2; i <= maxTick; i += 2) + { + int coord = i-1; + int color, length; + if (i % 10 == 0) + if (i % 50 == 0) + if (i % 100 == 0) + { + color = 15, length = 10; + itoa(i, txt1, 10); + } + else + color = 14, length = 7; + else + color = 13, length = 5; + else + color = 9, length = 2; + if (i <= width) + { + g->setColor(color); + g->vLine(coord, 0, length); + if (length == 10) + { + g->setTextJustify(GraphicsAPI::RIGHT, + GraphicsAPI::TOP); + g->putText(coord, length, txt1); + } + } + if (i <= height) + { + g->setColor(color); + g->hLine(0, coord, length); + if (length == 10) + { + g->setTextJustify(GraphicsAPI::LEFT, + GraphicsAPI::BOTTOM); + g->putText(length, coord, txt1); + } + } + } + + int middle = width/2; + int line = 30; + g->setTextJustify(GraphicsAPI::HCENTER, GraphicsAPI::TOP); + g->setColor(10); + g->putText(middle, line, g->getLibID()); + g->setColor(12); + g->putText(middle, line+=12, "Physical resolution"); + sprintf(txt1, "%d x %d", g->getWidth(), g->getHeight()); + g->setColor(15); + g->putText(middle, line+=9, txt1); + + g->setColor(12); + g->putText(middle, line+=12, "Virtual resolution"); + sprintf(txt1, "%d x %d", width, height); + g->setColor(15); + g->putText(middle, line+=9, txt1); + + g->setColor(12); + g->putText(middle, line+=12, "Page resolution"); + sprintf(txt1, "%3.1f x %3.1f", minfo.xpages, minfo.ypages); + g->setColor(15); + g->putText(middle, line+=9, txt1); + + int hPalSize = width - 40; + int vPalSize = height - (line+=22); + int palSide = sqrt(colors); + int hPalPix = hPalSize/palSide; + int vPalPix = vPalSize/palSide; + hPalSize = palSide * hPalPix + 1; + vPalSize = palSide * vPalPix + 1; + for (i = 0; i < colors; ++i) + { + g->setColor(i); + int x = width-hPalSize+(i/palSide)*hPalPix; + int y = height-vPalSize+(i%palSide)*vPalPix; + g->bar(x, y, x+hPalPix, y+vPalPix); + } + + int basex=0, basey=0, bdirx=0, bdiry=0, quit=0; + while (!quit) + { + if (kbhit()) + { + int key = getch(); + if (!key && kbhit()) + key = getch() << 8; + + switch (key) + { + case 0x4700: + basex = basey = bdirx = bdiry = 0; + break; + case 0x4800: //UP + --bdiry; + break; + case 0x4b00: + --bdirx; + break; + case 0x4c00: + bdirx = bdiry = 0; + break; + case 0x4d00: + ++bdirx; + break; + case 0x5000: //DOWN + ++bdiry; + break; + case 27: + case 13: + quit = 1; + break; + } + } + basex += bdirx; + basey += bdiry; + if (basex > width-g->getWidth()) + basex = width-g->getWidth(), bdirx = 0; + if (basey > height-g->getHeight()) + basey = height-g->getHeight(), bdiry = 0; + if (basex < 0) + basex = bdirx = 0; + if (basey < 0) + basey = bdiry = 0; + + g->setBase(basex, basey); +// bdirx = bdiry = 0; // for debugging + } + delete g; + } + break; + + case testText16: + case testText8: + + // Fill top line with the sequence "0123456789" lt grey/black: + a = 0; + for (c=0; c8) + { + a=1; + ++offset; + } + if ((++c)==width<<2) + c=0; + } + while (offset <= 0xffff); + getch(); + break; + case test4x16: + +// This is Peter's 16-color test. The original test is commented out below. + + init16(); + color16(15); + for (a=0; a<(width*8); a+=10) { + if (! (a % 100)) { + color16(15); + point16(a,1); + point16(a,2); + point16(a,3); } + else + color16(2); + + point16(a,0); } + + for (a=0; a<600; a+=10) { + if (! (a % 100)) { + color16(15); + point16(1,a); + point16(2,a); + point16(3,a); } + else + color16(2); + + point16(0,a); } + + // draw 16 color bars across the screen + + for (int x = 0; x < (width-2)*8; x++) { + color16(x / ((width-2)*8/16)); + for (int y=10; y < 190; y++) { + point16(x+8,y); }} + +/* + // Original 16-color test + // Fill first 32 lines with thick vertical stripes alternating + // between black and the color selected by Write Plane Enable. + for (c=0; c<(width<<5); c++) + graphScr[c]=0x0f; + + // Fill the rest with various bit patterns, in all colors. + for (a=0; a<256; a++) + { + outportb(0x3c5,a); + memset(graphScr+(a+40)*width, a, width); + } +*/ + getch(); + break; + } + } + + +// tellTest() puts the name of the current test at the correct position on +// the edit screen. + +void TestPatterns::tellTest() + { + gotoxy(42,editHeight); + textattr(TESTHEADER_COLOR); + cprintf("Current test: "); + textattr(TESTSTRING_COLOR); + cprintf(string[testNo]); + clreol(); + } diff --git a/16/tweak16/TESTPAT.HPP b/16/tweak16/TESTPAT.HPP new file mode 100755 index 00000000..7171bf92 --- /dev/null +++ b/16/tweak16/TESTPAT.HPP @@ -0,0 +1,38 @@ +/* + TestPat.hpp version 1.0 + by Robert Schmidt of Ztiff Zox Softwear 1993 + + Declares the TestPatterns class which is further defined in + TestPat.cpp. +*/ + +#ifndef _TestPat_HPP +#define _TestPat_HPP + +#include +#include "RegTable.HPP" + +class TestPatterns + { +public: + // testType declares the possible types of screen patterns to test your + // wonderful modes with. Note that 'tests' is there just to provide a + // constant equaling the number of tests. + enum testType + { autoDetect, testText16, testText8, test4x16, test1x256, + test4x256, tests }; +private: + static char *string[tests]; + testType testNo; +public: + TestPatterns(testType t=autoDetect) { testNo = t; } + testType operator++() { if (++testNo==tests) testNo=testType(0); + return testNo; } + testType operator--() { if (--testNo +#include +#include +#include +#include +#include +#include + +#include "Screen.HPP" +#include "RegEdit.HPP" +#include "TestPat.HPP" +#include "detect.hpp" + + +void helpWindow() + { + tempBuffer swap(textScr); + swap.save(); + window(5,5,editWidth-5,33); + textattr(HELP_COLOR); + clrscr(); + window(6,6,editWidth-6,32); + gotoxy(1,1); + cprintf("TWEAK 1.6á by Robert Schmidt - Ztiff Zox Softwear\n\r" + "Quick reference help screen\n\r" + "\n\r" + "Up/Down/Home/End: select register\n\r" + " Backspace: enable/disable register\n\r" + " 2 hex digits: set register value\n\r" + " -/+: decrease/increase register value\n\r" + " F1-F8: toggle register bits 7-0\n\r" + " F9 or 'S': save register set to file\n\r" + " F10 or 'L': load set from file\n\r" + " 'M': select BIOS mode to work from\n\r" + " TAB/Shift-TAB: select test screen\n\r" + " ENTER: show test screen\n\r" + " 'H': show this help window\n\r" + " ESC: Quit TWEAK immediately\n\r" + "\n\r" + "The mode heuristics shown are NOT perfect. It is practically\n\r" + "impossible to foresee what your screen will show. Use the\n\r" + "values given as guidance, or hints.\n\r" + "\n\r" + "When viewing the autodetect test screen, you may use the\n\r" + "arrows to scroll over the virtual screen. Press ESC or ENTER\n\r" + "to leave.\n\r" + "\n\r" + "For more information, see the TWEAK.DOC file.\n\r" + "Now press the 'any' key to return to the editor.\n\r" + ); + getch(); + window(1,1,editWidth,editHeight); + swap.restore(); + } + + +void prompt(char *p = 0, int attr = PROMPT_COLOR) + { + textattr(7); + gotoxy(42,editHeight-1); + clreol(); + textattr(attr); + if (p) + cprintf(p); + } + + +int main(int argc, char **argv) + { + // Initialize the register table with descriptions and all. + RegisterEditor regEditor(ifstream("TWEAK.DAT")); + TestPatterns test; + + int parentBiosMode = getBiosMode(); + preparePalettes(); + // Set our default editing screen, and get its dimensions + setBiosMode(3); + textmode(C4350); + clrscr(); + text_info *ti = new text_info; + gettextinfo(ti); + editMode = ti->currmode; + editHeight = ti->screenheight; + editWidth = ti->screenwidth; + editSize = editHeight * editWidth; + delete ti; + + tempBuffer swap(textScr); // Establish the temporary screen buffer + + unsigned char quit = 0; // Non-zero when a quit command is + // initiated. + int key; // The last key pressed. + + // Build the editing screen: + + regEditor.printAllCon(); + gotoxy(42, editHeight-20); + textattr(HELP_COLOR); + cprintf("(Press H if you need help)"); + + ModeInfo minfo(regEditor); + + // Start the main keyboard polling loop: + + while (!quit) + { + test.tellTest(); + regEditor.showBitMask(); + minfo.show(); + regEditor.updateSelect(); + + int key = getch(); + if (!key) + key = getch() << 8; + else + key = tolower(key); + +keyentry: + switch (key) + { + case 0x4700: //HOME + regEditor.setSelect(0); + break; + case 0x4800: //UP + --regEditor; + break; + case 0x4F00: //END + regEditor.setSelect(regEditor.getMaxReg()); + break; + case 0x5000: //DOWN + ++regEditor; + break; + + // Function keys - toggle single bit in selected reg. + case 0x3B00: //F1 + case 0x3C00: + case 0x3D00: + case 0x3E00: + case 0x3F00: + case 0x4000: + case 0x4100: + case 0x4200: //F8 + **regEditor ^= (1<<7-((key>>8)-0x3B)); + break; + + case 0x4300: //F9 + case 0x4400: //F10 + // Handle file operations (save/load): + char fname[63]; + int save=(key==0x4300); + + // Prompt for filename. + if (save) + prompt("Save file name: "); + else + prompt("Load file name: "); + gets(fname); + if (strlen(fname) == 0) + { + prompt("File operation canceled."); + break; + } + + prompt(0, ERROR_COLOR); // prepare for error + if (save) + { + ofstream out(fname, ios::trunc|ios::binary|ios::out); + if (out.bad()) + cprintf("Error creating '%s'!", fname); + else + { + out << regEditor; + if (out.bad()) + cprintf("Error writing '%s'!", fname); + else + { + prompt(fname); + cprintf(" written."); + } + } + } + else + { + ifstream in(fname, ios::binary|ios::in|ios::nocreate); + if (in.bad()) + cprintf("Error opening '%s'!", fname); + else + { + in >> regEditor; + if (in.bad()) + cprintf("Error reading '%s'!", fname); + else + { + prompt(fname); + cprintf(" read."); + } + } + } + + // Update screen to reflect changes (if any). + regEditor.printAllCon(); + test.tellTest(); + break; + + case '0': case '1': case '2': case '3': case '4': case '5': + case '6': case '7': case '8': case '9': case 'a': case 'b': + case 'c': case 'd': case 'e': case 'f': + // Input hexadecimal number: + gotoxy(40*(regEditor.getSelect()/editHeight)+38, + regEditor.getSelect()%editHeight+1); + ungetch(key); + cprintf("%c \b", key); + unsigned char newValue; + cscanf("%2hx", &newValue); + (*regEditor).setValue(newValue); + break; + + case 'h': + // Help: + helpWindow(); + break; + + // Alternate file I/O keys: + case 's': + key = 0x4300; + goto keyentry; + + case 'l': + key = 0x4400; + goto keyentry; + + case 'm': + + // Select a BIOS mode to work from. + int baseMode; + prompt("Base BIOS screen mode: 0x"); + cscanf("%2hx",&baseMode); + swap.save(); //save edit buffer + + // Set the selected mode, and grab register values. + setBiosMode(baseMode); + regEditor.in(); + swap.restore(); //reset edit mode and buffer + regEditor.printAllCon(); + prompt(); + cprintf("Got registers from mode 0x%02x", baseMode); + break; + + case 8: + (*regEditor).toggleEnable(); + ++regEditor; + break; + + case '-': + // Decrease register value: + // Note that * (dereferencing) is overloaded for both + // RegisterTable and Register! Pretty fancy, but hard + // to read! + -- **regEditor; + break; + + case '+': + // Increase register value + ++ **regEditor; + break; + + case 13: //ENTER + // Test the screen mode. + swap.save(); + // Clear the text screen, so the user can see something is + // happening even if he chose the wrong test screen. + clrscr(); + test.run(regEditor); + swap.restore(); + break; + + case 9: //TAB + // Select next test pattern: + ++test; + break; + + case 0x0F00: // shift-TAB + // Select previous test pattern: + --test; + break; + + case 27: //ESC + // Quit TWEAK: + prompt("Really quit [n]?"); + if (toupper(getch()) == 'Y') + quit = 1; + prompt(); + break; + } + minfo.detectFrom(regEditor); + } + + // Reset BIOS mode detected at startup. + setBiosMode(parentBiosMode); + + return 0; + } \ No newline at end of file diff --git a/16/tweak16/TWEAK.DAT b/16/tweak16/TWEAK.DAT new file mode 100755 index 00000000..e13336e1 --- /dev/null +++ b/16/tweak16/TWEAK.DAT @@ -0,0 +1,30 @@ +29 +3c2 00 Misc. output +3d4 00 Horiz. total +3d4 01 Horiz. disp. enable end +3d4 02 Horiz. blank start +3d4 03 Horiz. blank end +3d4 04 Horiz. retrace start +3d4 05 Horiz. retrace end +3d4 06 Vertical total +3d4 07 Overflow register +3d4 08 Preset row scan +3d4 09 Max scan line/char ht. +3d4 10 Vertical retrace start +3d4 11 Vertical retrace end +3d4 12 Vert. disp. enable end +3d4 13 Offset/Logical width +3d4 14 Underline location +3d4 15 Vertical blank start +3d4 16 Vertical blank end +3d4 17 Mode control +3c4 01 Clock mode register +3c4 03 Character gen. select +3c4 04 Memory mode register +3ce 05 Mode register +3ce 06 Miscellaneous register +3c0 10 Mode control +3c0 11 Screen border colour +3c0 12 Color plane enable +3c0 13 Horizontal panning +3c0 14 Color select diff --git a/16/tweak16/TWEAK.DOC b/16/tweak16/TWEAK.DOC new file mode 100755 index 00000000..ade4bd5e --- /dev/null +++ b/16/tweak16/TWEAK.DOC @@ -0,0 +1,1054 @@ + + + + + + + TWEAK 1.6á - Mold your own VGA modes + + by Robert Schmidt of Ztiff Zox Softwear, 1992-93 + + + This program and the accompanying source files + are hereby donated to the public domain. + (for whatever that's worth...) + + + + + + + +(Sorry for not page-formatting this doc. The headers can be found by +doing a text search with your favourite editor.) + + +Contents: + +WHAT IS TWEAK, ANYWAY? +SUGGESTION BOX +DISCLAIMER +A QUICK PRIMER +WHAT HAS TWEAK GOT TO DO WITH THIS? +A COUPLE OF RULES +A TUTORIAL +EDITOR REFERENCE +FREQUENTLY ASKED QUESTIONS +THE TWEAK FILES +USING TWEAK MODES ON YOUR OWN +THE INCLUDED FILES +THE 'MISC' DIRECTORY +CREDITS +BIBLIOGRAPHY +HOW TO REACH ME + + + + + WHAT IS TWEAK, ANYWAY? + + +TWEAK is an utility to ease the work of twiddling with the registers on +a standard VGA compatible video card to produce and explore new, previously +undocumented screen modes with weird resolutions. You will want to +purchase a technical VGA reference to get the full potential out of +TWEAK, but I included some files to get you started (see the section +on the 'MISC' directory). + +TWEAK.EXE is the main executable. This version is not compatible with +any versions prior to 1.0, so if you want to use files created by +version 0.9x, convert them with 09TO10.EXE. + +Stop press! In the subdirectory XINTRO is an article which serves as +an introduction to programming in Mode X (320x240 with 256 colors). +Make sure you read this if you're new to tweaking and Mode X! + +MODES.DOC describes some of the more exciting 256x256, 400x300 +and 400x600 256-color modes! + + + + + SUGGESTION BOX + + +All suggestions to enhance or modify TWEAK are welcome, especially bug +reports/fixes. So are donations, for that matter. See e-mail and +snail-mail addresses at the end of this file. + +Please send me any changes you make to enhance TWEAK or to make it +compatible with other compilers or video cards, and I will start +including conditional sections for each supported compiler. +Do *not* re-release the changed source without my permission. +Well, how can I stop ya...? + +Any suggestions and contributions will be credited in subsequent +versions, although I can't guarantee that your ideas will actually be +used. + + + + + + DISCLAIMER + + +I don't think this is neccessary in PD stuff, but everybody else does +it: + +The author author of this archive has used his best efforts in +preparing it. However, the author makes no warranty of any kind, +expressed or implied, with regard to the programs, data or +documentation included with the archive. The author shall not be +liable in any event for incidental or consequential damages in +connection with, or arising out of, the furnishing, performance, +quality, or use of the programs, data or documentation included in this +archive. + +Phew. + +Some time ago, putting illegal or unsupported values or combinations +of such into the video card registers might prove hazardous to both +your monitor and your health. I have *never* claimed that bad things +can't happen if you use TWEAK, although I'm pretty sure it never will. +I've never heard of any damage arising from trying out TWEAK, or from +general VGA tweaking in any case. I did receive a mail from a person +whose monitor failed producing the correct colors, after using mode +X. + + + + + + + A QUICK PRIMER + + +You never heard about neither documented nor undocumented modes, you +say? Well, to begin with: Your VGA card has a number of registers +that control the way the card works. That is, how it is going to +translate the data that programs put into the video memory, to the +signals that produce text and/or graphics on your monitor. + +The standard interface to a video card on all IBM compatible PCs is the +BIOS, which consists of several device independant routines for setting +screen modes, moving the cursor, writing text, scrolling blocks of text +etc. The BIOS also takes care of setting the appropriate registers at +appropriate times, for example when changing screen modes. That way, +programmers have a consistent interface to the VGA, and usually won't +need to tamper with the registers directly. + +A screen mode specifies the resolution of the image you see on the +screen, i.e. the number of pixels (dots) horizontally and vertically, +the number of colors, and wether the screen should be capable of +showing just text, or if graphics are allowed. These things are +controlled by the VGA registers, and the BIOS contains a number of +predefined tables of register values for the standard VGA modes we've +all come to love and honour. Mode number 3, for example, is the 80 +characters times 25 lines (80x25) text screen that most people use +daily. Mode number 19 (or 13h in hexadecimal) is the 256-color 320x200 +mode used in most popular games supporting the VGA. + + + + + + + WHAT HAS TWEAK GOT TO DO WITH THIS? + + +Well, some people, me included, are of the 'power-hungry' breed. We want +to exploit the full potential of everything we get between our hands. +We think that the one 320x200 256-color mode supported by all standard VGA +BIOS'es is for wimps. Some guy came up with the idea of modifying the +register configuration, to achieve greater resolution and a different +video memory layout. + +TWEAK grants you direct access to all the most significant registers +that control such things as resolution and colors. You may have thought +that your VGA was limited to 320x200 when it was displaying 256 colors? +Well, all VGAs are able to support no less than 400x600 in 256 colors. +(The problem is with the monitors, which might not be sophisticated +enough to support the relatively much higher clock frequency needed to +output that many pixels. My monitor flickers and rolls occasionaly.) + +Most newer VGA cards' BIOSes add several enhanced modes not supported +by the standard VGA defined by IBM, for example text modes with 132 +characters on each line, or graphics resolutions of 800x600, 1280x1024 +and more. Such cards are usually referred to as Super VGAs. To make it +possible to produce such resolutions, video card developers has had to +add new registers to the set of registers defined by the VGA. TWEAK is +generally not able to support such extended registers, meaning that you +will not be able to tweak a Super VGA any more than is possible on a +standard VGA. Extensions that are provided by utilizing undefined bits +in the standard VGA registers are supported however. The included +Chips & Technologies specific 132x*.twk files are examples of such. + +The main reason for not including Super VGA (SVGA) support is that +there are so many different SVGA standards. Nearly every developer has +their own standard. Also, I can see no real reason for wanting to tweak +any SVGAs, as the resolution dimensions they offer usually are far +superior to the VGA's resolutions. With tweaked VGA modes there's +a much higher propability that they will work on most VGAs and SVGA, +than tweaked SVGA modes. + +If this is the first you have read about VGA registers and the BIOS, +TWEAK.EXE and this documentation alone is not enough to get you going. +You will need, and probably want, a somewhat technical reference to the +VGA, which explains all standard VGA registers and the meaning of every +contained bit. Although TWEAK doesn't support it, you'll probably want +a reference which also contains some discussion on Super VGAs, just for +your convenience when you want to program serious applications etc. If +you're of the adventurous breed, check out the VGA.TXT and VGABIOS.TXT +files included in the .\MISC directory. + +You see, tweaking the VGA is not as simple as putting the horizontal +resolution in one register, the vertical in another and the number of +colours in yet another. Several registers has to be set to cooperating +values that work together to acheive what you want. Single bits has to +be toggled into the correct states, even before you can see anything on +screen. TWEAK simplifies this process by letting you do this +interactively, and by letting you test your register set at the touch +of one key (ENTER, actually). The pre-TWEAK process was to make a small +program that set up the registers in the way the programmer thought +would work. If it didn't he had to edit the program source file, +recompile, and re-run. Not seldom, the PC crashed because of some +*really bad* register values, and a full reset was required. + +TWEAK let you save and load register sets to and from files, and let +you select any video mode supported by your BIOS to work out from. +It supports text modes and graphics, 16-color and 256-color. Monochrome +modes and CGA modes (4- and 2-color), however, are not supported, +because they use another set of I/O ports, and because few people are +really interested in them. + +As of version 1.6, TWEAK further simplifies the VGA tweaking process by +providing instant feedback on the register values, in the form of a +live mode heuristic, i.e. a detection scheme tried to figure out what +type of mode your making, the number of colors, its physical and +virtual resolution, the number of pages (both horizontally and +vertically). + + + + + + + A COUPLE OF RULES + + +I'll be the first to admit: TWEAK isn't much of an editor. The screen +is boring, there is just one simple help window, no undo command, no +file pick lists etc. In short, TWEAK is not meant for people not +knowing what they are doing. I strongly beleive that nothing can be +damaged from the use of TWEAK, but for starters, I'll recommend the +following precautions: + + * When loading/saving, take care to check that you selected the + function (load or save) that you want, before typing a filename + and pressing Enter. Also verify that the filename you type when + saving is the filename that you want, because TWEAK overwrites + any existing files with the same name without asking for permission. + + * If, when you press the Enter screen to test the screen mode, + nothing appears after 5-10 seconds, press Enter again. If you're + not immediately returned to the editing screen, reboot your + computer by pressing the reset button. Keep in mind that some of + the test patterns, especially the 256-color 4-planar one, can be + slow to put into the video memory buffer, so be a *little* + patient & tolerant. + +That last rule is present to prevent that the monitor is exposed to crazy +sync timings for too long a time. And I repeat, there usually never is +any reason to panic, even if your monitor makes strange sounds +('tweeeeee' for example, or 'flick-flick-flick'). Press ENTER, wait for +a couple of seconds more, then reset your computer if the edit screen +doesn't reappear, and try a different approach. + + + + + + + A TUTORIAL + + +To start TWEAK, change to the directory where you have put the files, +and type TWEAK at the DOS prompt. Well, now you're in the editor, and +you can see the following things (you might want to print this tutorial +so you have it on paper): + + * One (possibly two) column(s) of VGA registers on the form: + ppp (ii) Register Name : vv + where + - ppp is the port number + - ii is the index into that port, if applicable + - vv is the selected value for this register + All numbers are hexadecimal. The current register is marked by one + arrowhead on each side of the line. When you first start TWEAK, + the current register is the top left. + + * A bit pattern display showing the bit pattern of the 8-bit value + contained in the currently selected register. + + * The bottom line tells you which test pattern is currently active. + + * You will also see the mode heuristic which usually makes a good + guess at what mode you have at the moment. + +When executed, TWEAK starts up by reading the registers of your current +BIOS mode, so that you have something to work with. This is usually a +text mode, 80x25 for example, so you'll probably want to set a graphics +mode for more interesting results. + +Now try the following simple tutorial: + + 1. Press H, and a red window should appear, describing all keys + available for use in TWEAK. These will also be described below. + + 2. Press M, then type the number 03. Notice that you don't have to + press ENTER. You have now selected BIOS mode 3 as the basis for + you explorations. Notice also the information provided by the + mode heuristic on the right. + + 3. Press TAB until 'Text screen, 16 point' appears at the bottom line, + if it doesn't already. TAB selects which test pattern to use, and + you have now readied the 16-point font version of the text screen + test. + + 4. Press ENTER. You should see a screen with numbers along the top + row, and various characters and colors down the rest of the screen. + This is the text test pattern, as it looks when viewed in mode 3. + Press ENTER to return to editing mode. + + 5. Now press F10, and type '40x12' and press ENTER. This loads the + file '40x12' and uses its contents as the current register set. + Notice how the mode heuristic immediately changes. + + 6. Press ENTER again. A screen similar to the previous test pattern + should appear, but the characters should be twice as wide and twice + as high. This is a tweaked VGA mode, which is not supported by the + BIOS. It looks a little odd, as the bottom line is cut in half, + making this a 40x12.5 text mode, in fact. Press ENTER to return. + + 7. Press F10, type '360x480.256' and ENTER. Take a look at the + mode heuristic again. Press TAB until the text 'Graphics + autodetect' appear in the bottom line. + + 8. Press ENTER. This is a well known tweaked VGA mode that has even + been used in commercial games for the PC, but it remains + unsupported by the BIOS (and it probably always will). If the + screen rolls, try adjusting your monitor knobs. If you can't get a + steady picture, it probably means your monitor isn't capable of + handling the horizontal resolution of 360 pixels. + + 9. Try using the arrows to scroll the virtual screen. + + 9. Press ENTER to return to editing, then press ESC and 'Y' to quit + TWEAK. + + +The last graphics display might not have been especially pleasing to the +eye. First, if the picture was rolling uncontrollably, you might think +that TWEAK is of no use for you, as your monitor isn't good enough. +However there are still interesting things to try out. There are +tweaked modes 'available' with a little lower resolution that are almost +guaranteed to work on your monitor, and which are of great interest to +games programmers for example. The file 320x240.256 contains the +register set for the infamous Mode X, which was 'discovered' and +documented by Michael Abrash in his monthly columns in Doctor Dobbs +Journal. + +Following points 7 onward above, see if you can load Mode X into the +editor and get the test screen going! + +Mode X has the following interesting properties: + + * The pixels are 'perfectly' square. That is, if you try to draw a + circle with aspect ratio 1:1, it will look like a circle (unless + your monitor is adjusted to some extreme). The BIOS mode 13h + (320x200x256) has pixels that are a little higher than they are + wide, making 1:1 circles look stretched vertically. + + * The video memory is divided into 4 planes, each of which contains + 64 Kb. By setting the Write Plane Enable register to the actual + plane, you can address the full 256 Kb of video memory through the + 'tiny' address space of 64 Kb from 0xA000:0 to 0xA000:0xFFFF. + Thus, you can have more than three full screens in video memory at + any one time, making you able to perform animation tricks as + page flipping, and to do fast 32-bit video to video transfers. + +This was just to get you going, and others have written tons of text on +drawing stuff (lines, circles, images) in Mode X. The rest of this +part will deal with the commands available in TWEAK. To get more +information about VGA programming in general and registers and Mode X +in particular, check out the reference list somewhere at the end. + +Stop press! Read the article in the XINTRO subdirectory for an +introduction to Mode X. + + + + + + EDITOR REFERENCE + + +This reference applies only to version 1.0 of TWEAK or later, although +*most* keys are supported by the included version 0.95 too. + +Select the register value you want to modify using the following keys: + + Up selects previous register + Down selects next register + Home selects first register + End selects last register + +Use these keys to modify a register value: + + a 2-digit, hexadecimal number : sets the register to the given value + '-' decreases the value of the register + '+' increases the value of the register + F1 ... F8 toggle bits 7, 6, ..., 0 of the selected register, + respectively. + +Use these keys for testing the set of register values: + + TAB [->|] cycle among the available test patterns, to find the + one you think will suit your custom register set. + Shift+TAB cycles in the opposite direction. + + ENTER sends your custom register set to the VGA registers, then + writes the selected test pattern to the video memory buffer. + +Some other important or useful actions: + + Backspace toggles the active state of the current register. If a + register is inactive, it color is grey instead of yellow. + When you test the mode (by pressing ENTER), inactive + registers will *not* be sent to the VGA card. Also, they + will *not* be saved to the file when a Save command is + executed. This feature is included to enable you to ignore + registers that doesn't affect your screen mode. For + example, for most practical uses, the Color Compare register + can be deactivated. + + 'M' prompts the user for a 2-digit, hexadecimal number + specifying a standard VGA BIOS screen mode number. Note + that TWEAK does *not* support true monochrome modes. + The VGA is set to this mode using INT 10h with AX=mode + number. Then all relevant registers are read from the + VGA into the editing set, and you're returned to the + editing screen. + + F9 or 'S' prompts the user for a file name, then saves the register + set to this file, overwriting any pre-existing + file by the same name. Inactive registers are not saved, + thus there are no longer a fixed size to TWEAK's mode + files. + + F10 or 'L' prompts the user for a file name, then loads the register + set from this file, if it exists. Registers that are + supported by TWEAK, but that are not included in the file, + will be deactivated (greyed). + + ESC quits TWEAK, if you answer 'y' or 'Y' to the 'Really + quit?' question. Make sure you have saved your work. + +Pressing just ENTER at one of the two file name requests will cancel +the file operation. + + +There are currently 6 available test screens with TWEAK. Numbers in +parentheses are all the standard VGA BIOS modes that display the test +patterns correctly: + + o An autodetected graphics screen test. This will detect *most* + EGA and VGA graphics modes (of course no monochrome modes), and + display a pretty screen containing: + + - axes along the left and top borders visualizing the resolution. + - text telling you both the physical and the virtual resolutions, + and the number of colors. + - the entire palette available in this mode. Note that the + palette is *not* set, so the colours are not guaranteed to be + the normal VGA palette, except in 16-color mode. + + The following keys are available in the autodetect test screen: + + - arrows scroll the screen across the virtual area + - ESC returns to the editor + + If the mode being edited is not a graphics mode, a text screen + appears with some helping hints. + + o 2 text test screens at 0B800h + - one using the normal 8x16-point VGA font (0, 1, 2, 3) + - one using the 8x8-point CGA font (normally used in 43/50-line + modes, but none of those are defined by the VGA BIOS. Check + VGABIOS.DOC for the function to load a specific font in your + own programs.) + + o A screen for 4-planar, 16-color modes at 0A000h (0Dh, 0Eh, 10h, + 12h) + + o A screen for 4-chained, 256-color modes at 0A000h (13h) + + o A screen for 4-planar, 256-color modes at 0A000h (None supported + by BIOS) + +See the source (TESTPAT.CPP) for descriptions on how the test patterns are +supposed to look. Generally, if it looks good, it should be correct. + + + + + + FREQUENTLY ASKED QUESTIONS + + +Q: I'd like to study the register configuration for a screen mode + supported by my (Super-)VGA. How do I get to it? + +A: The 'M' key lets you select a BIOS mode to study. Note that you + will need to know the mode number. Note that TWEAK does not + support any SVGA-specific registers. + + +Q: None of the tests seem to produce sane results. The screen + a) goes black, + b) rolls or + c) the program crashes. + +A: a) - Make sure you tried ALL 5 tests. + - Set the Color Plane Write Enable register to 0Fh. + - Note that Super VGA modes are generally not supported + (though they *might* work). + b) - The timing/sync registers are not set correctly/in sync. + See your VGA reference for more information. + - Try adjusting the knobs on your monitor. + c) - I know some (S)VGAs completely hang the system if + unsupported bit combinations are fed into the Misc. + Output Register (0x3c2). This is one of the most useful + registers, however, so experiment with care, and take note + of what values causes the crash. + - You may have hit a major incompatibility/bug. Send me a + mail, telling me what kind of hardware you're using. I + will probably not be able to fix it, but an incompatibility + list will be emitted with the next release, if any. + + +Q: How about a TSR to save the current register configuration from + any program? + +A: I've considered this, but haven't had the time. A hint, though: + Get CBOOTxxx.ZIP from simtel or any mirror, in .../msdos/sysutl. + This program lets you break out from most applications, + *without* resetting the screen mode. A typical session: + - Install CBOOT. + - Run FRACTINT (a fractal explorer package, supporting lots + of tweaked modes), and select the mode you want to 'grab'. + - Press ALT+SHIFT+B, and the CBOOT menu pops up. + - Press '7' to reset interrupt vectors. + - Press '6' to 'properly' exit from FRACTINT. + - You might not see it, but you should be at the DOS prompt. + - Run TWEAK directly, which will start up with the current + register configuration. Now you're off! + From programs (games) which assume total keyboard domination, I + currently cannot help you grab modes. + + +Q: I'd like to use tweaked modes in my own programs. + +A: Provided you have produced TWEAK files corresponding to your + modes, take a look at the example files for different approaches + to using the mode files. The examples are in C, but are simple + enough, so translation to Pascal should be a breeze. + + +Q: - What is the register which makes x do y/sets a to b/etc.? + - Is there a BIOS call to do x? + +A: First check the VGA.TXT and VGABIOS.TXT files in the MISC + directory. If they don't help you, please consider buying a + technical reference to the VGA. That would please you and me. + + +Q: How do I make a mode with resolution x times y with z colors? + +A: - See the sample *.TWK, *.256 and *.16 files provided with + TWEAK. Not a great lot, but you might be able to work out + something from one of those. + - Get FRACTINT or SVGABGI, and use the method mentioned above to + 'grab' modes from these programs. + - Learn what each of the VGA timing registers means. + - Experiment! That's what I had to do. + + +Q: I can't find this MISC or XINTRO directory! + +A: Make sure you unzip the TWEAK archive with the -d option, which + is needed to extract subdirectories. I.e: + PKUNZIP -D A:TWEAK10 + If you didn't use -D, the files in the MISC directory are mixed + in with the rest of the TWEAK package files, all in the same + directory. + + +Q: I have lots of files with modes that I saved with version 0.9 of + TWEAK... + +A: Use the 09TO10 utility to convert them. Run 09TO10.EXE with no + parameters for a simple help screen. + + +Q: What do I need to rebuild TWEAK and/or the utilities? + +A: You will need Borland C++. I used version 3.1, but it might + work as far back as Turbo C++ 1.0. I included a Makefile to + make rebuilding as painless as possible, provided you have + BCC.EXE in your path, and it knows where to find headers and + libraries (usually it does). I know some of the sources + produce warnings, but feel free to ignore them. I did. + + +Q: What do I need to use the mode files produced by TWEAK in my own + programs? + +A: If you want to use the TwkUser module, you'll need a C compiler. + I don't think I used anything Borland specific here. + Otherwise the file format is pretty simple, so you should have + no problem making similar functions/procedures using any + language (assembler, Basic, Pascal, Prolog...). + + +Q: Where can I find more information on tweaking the VGA? + +A: See the Bibliography section below. Michael Abrash's articles + in Doctor Dobb's Journal from a year or so are probably the best + sources. Join the rec.games.programmer newsgroup. There has + been some discussion on tweaking there, especially mode X + (320x240x256) and how to optimize code for this mode. + + +Q: How can I ever repay you for making such a great utility? + +A: Easy! The cheapest way is to send me a cool postcard with some + (readable) words on it. I will of course accept donations too, + even though TWEAK is public domain. See the end of this file. + + +Q: PKUNZIP refused to unzip the TWEAK archive! + +A: I guess you decoded this DOC file by hand, then... well, make + sure you transfer in BINARY mode from the ftp site, and in + BINARY from your user account to your PC. + + +Q: I can't find my question in the Frequently Asked Questions list! + Does this mean I'm stupid? + +A: It might. :-) However, I just thought up all these questions + myself, so if you have a suggestion for more FAQs, don't + hesitate to let me know! I promise I won't laugh... + + +Q: The mode heuristic tells me I have the mode I want, but none of + the test screens works, not even the autodetecting one! + +A: The heuristic is far from perfect. It does NOT verify that the + timing values you are using are sane - it merely checks the + registers determining the logical resolutions. The best advice + I can give is to get a VGA reference and try to learn what the + horizontal and vertical timing registers do. TWEAK is less + intelligent than you (hopefully)! + + + + + THE TWEAK FILES + + +The file format used for saved files is pretty simple. The files will +usually be bigger than the files saved with TWEAK 0.9, and version 0.9 +files are *not* readable by version 1.0. This is undetectable by TWEAK, +because of the simple nature of the files. (No headers are present!) +If you try, there's a fat chance that your computer will hang. + +Here is the format: + +offset 0: WORD - port number of first register +offset 2: BYTE - index of first register +offset 3: BYTE - value of first register + +offset 4: WORD - port number of second register +. +.etc. +. + +Pretty simple, as you can see, but also flexible from TWEAK's point of +view. This makes it easy to add new ports if neccessary. The file size +is not constant, as registers that are disabled at save time are not +written to the file. Divide the file size by 4 to determine the number +of registers in a file, or just read to EOF (as TWEAK does... :). + +Also note that the VGA registers use varying methods for access. For +some registers you just send the value directly to the port (ignoring the +index). For some you send the index to the port, then the value to the +port+1. For still some you have to ... Rather, refer to the source +code for all the how-to's... it's not difficult, just inconvenient, and +it hinders really general storage of register addresses and their values. + +Use the 09TO10.EXE program to convert from version 0.9 files to version +1.0 files. Run 09TO10.EXE with no parameters for information on how to +use the utility. + +I have selected the following standard of file extensions for +TWEAK-files, but these are just suggestions for my own convenience: + + o *.TWK are text modes + o *.16 are 16-color graphic modes + o *.256 are 256-color graphic modes + +Note that you'll always have to type an extension in TWEAK if you want +any, as TWEAK neither assumes anything nor provides default extensions. + +I have also started addint a 'c' to the name (like in 256x256c.256) if +the mode is chained, i.e. uses linear addressing like mode 13h. I add +an 's' if the mode is specific to my Chips & Technologies SVGA. + +Make sure you read MODES.DOC! + + + + + + USING TWEAK MODES ON YOUR OWN + + +The Register and RegisterTable classes used in TWEAK.CPP might be a +little huge and clumsy to use in your own programs, where you probably +just want to set the registers according to a linked-in array. +Therefore I have provided a simple C module for the following functions: + + o Reading a file saved from TWEAK into a dynamically allocated + array of registers. + o Setting VGA registers according to the contents of an array of + registers. + o Setting a single register. + +The types and functions are declared in TWKUSER.H, which should be +included in every source file using these functions. The definitions +are contained in TWKUSER.C, which should be compiled under the wanted +memory model and linked together with your program modules. You are +free, in fact you're encouraged to modify the TWKUSER files to suit +your own needs. In their present form, they just provide enough +functionality to get you started. + +A couple of simple examples are provided - the second one is easiest to +follow, and I think you will prefer that one: + + o EXAMPLE1.C - demonstrates how to use a TWEAK-generated file + in your own program by loading the file at run-time, and setting + the VGA registers according to the file contents. The mode file + has to be available at run-time. + + o EXAMPLE2.C - does the same, but now the TWEAK-file is converted to + a C-includable file by using the TWEAK2C utility. Thus, the contents + of the TWEAK file is linked with the program as global data, and no + external file is needed in addition to the executable. + +Both programs set the VGA to the famous Mode X, 320x240 in 256 colors, +then fill the screen with some colors. + +Note that since the files produced by TWEAK does not keep any +information on what BIOS mode they are based on, you are responsible +for setting the palette used. Keep in mind that you need to set both +the EGA and VGA palette for 256-color modes! The easiest way to +accomplish this is to set mode 13h before outputting your register +settings. + +I would very much like to provide similar Borland Pascal examples, but +as I don't have Turbo/Borland Pascal available at the moment, I'm just +going to skip it at this time. If *you* feel like porting the TwkUser.C +and .H files to a Pascal unit, please do. It should be a peice of cake. +If you mail the result to me, I'll probably include it in the next release +of TWEAK, and in any case you'll be credited for your contribution. + + + + + + THE INCLUDED FILES + + +This is a dump of the 4DOS compatible DESCRIPT.ION file included in this +archive: + +320x200.256 Planar 320x200x256 +320x240.256 Planar 320x240x256 (Mode X) +360x480.256 Planar 360x480x256 +400x300s.256 Tweaked C&T SVGA planar +400x600.256 Tweaked VGA, req. good monitor +400x600s.256 Tweaked C&T SVGA planar +432x600s.256 Tweaked C&T SVGA planar +800x600s.16 Standard C&T SVGA BIOS mode +40x12.twk Standard VGA BIOS mode 1, double scanned +80x43.twk Standard VGA mode, needs 8x8 font +80x50.twk Standard VGA mode, needs 8x8 font +09to10.cpp Version 0.9x to 1.0 conv. util. source +800x600.16 Tweaked VGA, req. good monitor +example1.c C source for EXAMPLE1.EXE +example2.c C source for EXAMPLE2.EXE +makefile Type MAKE ALL to update TWEAK project +namedreg.cpp C++ source defining NamedReg. members +register.hpp C++ header declaring Register & NamedReg +regtable.cpp C++ source defining RegisterTable +regtable.hpp C++ header declaring RegisterTable +screen.cpp C++ source defining screen functions +screen.hpp C++ header declaring screen functions +tweak.cpp C++ source defining TWEAK's main program +tweak.doc Documentation for the TWEAK archive +tweak2c.cpp C++ source for the TWEAK2C utility +twkuser.c C source defining som usable functions +twkuser.h C header with TwkUser.C prototypes +register.cpp C++ source defining Register members +320x240.c C file created by TWEAK2C +c&t.dat Text file: list of supported registers +256x256.256 Planar 256x256x256 (Mode Q) +256x256c.256 Chained 256x256x256 (Mode Q, chained) +testpat.cpp C++ source defining TestPatterns members +testpat.hpp C++ header declaring TestPatterns +256x240.256 Planar 256x240x256 +360x270.256 Experimental mode +400x300.256 Planar 400x300x256 - great! +detect.cpp C++ source for mode detected module +detect.hpp C++ header for detect.cpp +misc.hpp Various common routines and macros +tweak095.cpp C++ source for TWEAK version 0.95 +vgalib.cpp The mode-independant VGA library source +vgalib.hpp Header for VGALIB.HPP +regedit.cpp C++ source for the RegisterEditor class +regedit.hpp C++ header for REGEDIT.CPP +descript.ion Descriptions of all files +tweak.prj TWEAK archive BC++ 3.1 project file +320x400.256 Planar 320x400x256 +360x360.256 Planar 360x360x256 +360x400.256 Planar 360x400x256 +376x564.256 Planar 376x564x256 +tweakold.dat Data file: list of supported registers +132x25s.twk Standard C&T SVGA BIOS mode +132x43s.twk Standard C&T SVGA BIOS mode +132x50s.twk Standard C&T SVGA BIOS mode +132x60s.twk Ultravision C&T SVGA mode +modes.doc Document on Mode Q, 400x300 and 400x600 + +The only files required to run TWEAK are: + + o TWEAK.EXE + o TWEAK.DAT + +The register definitions have been moved out from the executable into +the external .DAT file, to increase flexibility. You might edit the +TWEAK.DAT file as you like to include support for any registers you +might think of. Remember to update the number in the first line to +reflect the number of defined registers. Note that if your new registers +are not on one of the ports supported by TWEAK.EXE, you might need to +modify and recompile the TWEAK sources to accomodate the new port(s). +See REGISTER.CPP. + + + +Some words on my convention of naming files made by TWEAK: +---------------------------------------------------------- + + o The general name format is XXXxYYY.CCC, where + XXX is the horizontal resolution + YYY is the vertical resolution + CCC is the number of colors supported, except for text modes, + which are named *.TWK. + o An 's' after YYY specifies a Super VGA specific mode which I grabbed + from the BIOS of my Chips & Technologies Super VGA. These modes will + probably *not* work with your card unless it's C&T compatible! I've + had reports that most of these modes even crash some sensitive + machines/VGA cards. + o A 'c' signals a chained 256-color mode, much like mode 13h, as + opposed to unchained modes like mode X. + + +The Makefile & sources +---------------------- + +See the Makefile for all dependencies between the source files. It's not +very complicated. + +The following makes are defined in the Makefile: + +make tweak: makes the TWEAK executable. +make oldtweak: makes the TWEAK095 executable. +make examples: makes EXAMPLE*.EXE. +make utilities: makes 09TO10.EXE and TWEAK2C.EXE. +make all: combines all the above makes. + +The Makefile is Borland C++/MAKE specific, and uses bcc.exe for all the +work, with one reference to TWEAK2C.EXE. + +When studying the sources, note that TWEAK was started as an experiment +in object oriented programming with C++. Thus the entire project may look +a bit pompous in its use of classes, overloaded operators and such. +Bear with me. At last I provided the TwkUser files to help you get +started with something down to earth. + +In their current state, some of the source files produce a couple of +warnings. These can be ignored. I do. + +Also note that TwkUser.* and the examples are C (but C++ compatible), +while TWEAK and its utilities are strictly C++. + + +The utilities TWEAK2C and 09TO10 +-------------------------------- + +The following are dumps of the help screens from there programs: + +"TWEAK2C version 1.0 + by Robert Schmidt of Ztiff Zox Softwear 1993 + Converts a TWEAK version 1.x file to an #include-able C file. + + Syntax: TWEAK2C + All parameters are required." + +"09TO10 version 1.0 + by Robert Schmidt of Ztiff Zox Softwear 1993 + + Converts TWEAK version 0.9 files to TWEAK version 1.0 files. + + Syntax: 09TO10 " + +For both programs, the following goes: If the file to be created already +exists, the data contained in the file on disk will be overwritten with the +new data. + + + + + + THE 'MISC' DIRECTORY + + +In this directory I have included files from other sources than myself. + +READ.ME +VGA.TXT +VGABIOS.TXT + I found these files in an archive assembled by Finn Thoegersen + of Denmark. I beleive VGABIOS.DOC was taken from Ralph Brown's + interrupt list. VGA.TXT lists VGA registers and their purpose, + but as I never used either VGA.TXT or VGABIOS.TXT, I can't + guarantee their correctness. The complete archive containing + similar info on most popular Super VGAs can be found on + garbo.uwasa.fi in /pc/doc-hard/vgadoc2.zip. + +CGA160.TXT + A post grabbed from some newsgroup, discussing tweaking on the + ancient CGA adapter. I think 16-color 'graphics' on a CGA + sounds pretty interesting, so I included it for your enjoyment. + +SETMODEX.ASM + Michael Abrash's code to set the VGA in the infamous Mode X. + Provided as an example of how programmers were used to tweaking, + before TWEAK came along... :) + + + + + + CREDITS + +Alphabetically: + + o Michael Abrash for doing so much work on Mode X and PC graphics in + general. + o Ralph Brown for the great work on the Interrupt List. + o Peter McDermott for an improved 16-color test screen, and valuable + sugestions, he also inspired me to make the autodetecting test + screen. + o Kai Rohrbacher for helpful bug reports and info on working modes. + o Finn Thoegersen for the MISC\VGA*.TXT files. See MISC\READ.ME + o Yaniv Shaya for inspiring me to make finish version 1.0. Good luck + with your project! + + + + + + BIBLIOGRAPHY + + o George Sutty & Steve Blair : "Advanced Pogrammer's Guide to the + EGA/VGA" from Brady. A bit old perhaps, but covers all *standard* + EGA/VGA registers, and discusses most BIOS functions and other + operations. Contains disk with C/Pascal source code. + + o Michael Abrash : "Power Graphics Programming" from QUE/Programmer's + Journal. Collections of (old) articles in Doctor Dobb's Journal on + EGA/VGA, read modes and write modes, animation, tweaking (320x240 + and 360x480). His newer ravings in DDJ covers fast 256-color + bitmaps, compiled bitmaps, 3D graphics, polygons, texture mapping + among other stuff. Check out the XSHARP library available on all + simtel mirrors! + + o Ralph Brown's interrupt list is a must for every serious + programmer, containing, among 1 million other things, a VGA BIOS + interrupt reference. Available for anonymous ftp from + oak.oakland.edu in directory /pub/msdos/info as inter*.zip (Usually + 3 files, around 330 Kb each), and on most serious BBSes. + + o Richard F. Ferraro : "Programmer's Guide to the EGA and VGA video + cards including Super VGA". I don't have this one, but heard it's + nice. The Super VGA reference makes it attractive, though that is + no help with TWEAK. + + o Richard Wilton : "Programmer's Guide to PC & PS/2 Video Systems" + Less technical, more application/algorithm oriented. Supposed to be + good. + + + + + HOW TO REACH ME + + +I welcome any suggestions for further improvement of TWEAK. I also +accept donations if you think it's worth it, or if TWEAK has in any way +helped you out with a tricky problem and you'd like to show your +appreciation. I will personally e-mail subsequent versions to people who +donate $5 or more. Make checks payable to Robert Schmidt personally. + +Postcards from all over the world are fun to get. Please, if you +contact me by ordinary mail, use a postcard with some photos from the +place you live on the front! I appreciate that a lot. + + + +Internet e-mail: robert@stud.unit.no + +(I guess this should be reachable from Compuserve and other networks +too. I don't know how, though.) + +If you ever join the IRC service on the Internet, direct a /msg Buuud +for a chat! I'm on pretty often. + + + +Ordinary (snail-)mail: + +Ztiff Zox Softwear +c/o Robert Schmidt +Stud.post 170 +Norwegian Institute of Technology +Trondheim +NORWAY + + +Good luck, and remember the most important bit is to have fun! + diff --git a/16/tweak16/TWEAK.EXE b/16/tweak16/TWEAK.EXE new file mode 100755 index 0000000000000000000000000000000000000000..ab11b368e119301b1bebb0fc110f080513ecf3bd GIT binary patch literal 66496 zcmeFadwf*Y)jz!Fl9|cOWHJdMAW8^GMkJ6T5l|8^DxP?2jL=SqO7K>1ZPkXEgtjml zI#!q*z+0<`J}rp07Of2$bpVSY2?>`*2`F;0ia~M4gBZDFLNd&GziXc}lSu$=pWpL* z-sg{sD|61i@3q%nd#$zC-sgw6G-!UqzR(F!=YR^p^?+f32X!wR_iJA?UJZCo^P+Jv z;OBt30ImK-<4f8vjH@+Y7=H{n%)T(L1l$d{3Q!0*5AcZY3*$A~Y!d^V)MT3u0rmpg z00zM4EZejL&;a-&;8DP@0ha@Y1HRB)WBMgP3;2dzW7-V(GvHCcuK^DNt^*VTHtOy- z{Q~d+;3Mt*rk#LBz>9z<06xG^0A+y70l9z_fULRS^cmm-z$U;8fZqe|0E_~>$L=?s zFy3#H022XY0hYsy=I_W)Y~h3UXO;8MT@z&OAd zz-T}=-~zx6X@7BB-)1b7e*(M!cpdN>U@c%1U<2SSKntJ|@E%}0U=Lsy;1j@pz*m67fDS+x;27X2 zAPVRK7|>rWzy>e_G6Cs;s{qphQvs6!69IXEu>c2P6d(&Q4DcY}0l+(u&6YRhH;8-1?)7p_!Sqy~*jct|(;&1qxSh?d*s()AQh#Hupl=(w z-o`fkfQ59LtN@$THqxJUE3iF>1@!!7E?(|nfh7KN7hZnC0tWtaFJA6v0hY6L`||x8 zT$;9#Bbrb|&X&wu(S;FN0X-h)DvwEcyi0jB;PGC1+!0_J@gwn*f=^xNIlNcME}NtF zCe6gJ3%1VFi<`yWz9xfosNf^l`Qm;=Q@3S<%jl5jYK>B}LoUP5-<#^0TEq}ugw=7` zy_!mcqxN2nQotAID4uOv`Yg6#8p~Ur^@KL~l^oD9!rYe-U-S*%L$l|I z_STe6Y&hImmwkBE;q2LM+V@KXH>9qdpno8x(lGlg%JdY`(%#@V$+O?ja+U>Vu*qv| zEU5uMcD8!8W%3#`TeZqE`2{0ex^3dt<@*AcPFina@BUtkK^ngF8m+HYU(|6t;HJ?~ z-vip%i$5!*U22fDypD~syc`qAvD`3@<;s{bb&TfB2*=bU*D%MTX_rlLcRIu$YrQ?w z++SYpJ^ZORTJF|dJ-5Pgz;*YJ$_xJC9&I^LV`xhot#!>ja42t|VVic}!Mwd$+qBPp zdhic*T32DTLAva~p;p7=7RL5Xf84S@gLOnj+vAo+pIwo<=+qTD_jwd4%m0i;hVlAt zz^#oota!?w^|)p7k}Lxok@aKoi0_DLBT#d|hor1k=r-tDg`NjeT7^gpo}v$=xHAws zb0k8KnGt%>fzV^-z@<6s&1{RayKQ7qM{i(y&K75+ZDc^3V;iyIV<1f}(3P=zA$#=T zG+l<<9B@-)8zS4L9Gcu}$i}eXXB2*xA6WgO#V>SIBXkS&zLIWj+oT7(MWK80NQ0K; zH#{qTF^4Fg29dXP!59>RMr{1O7UPt+Wk}mdUlWGtBx>PrXiDCeGEBJtC@qsHuXGVKRdwcs=i+bc5*S!ThT_#UK+vS2@y0LANCmLYZ zwrLh2>K7ttQlxFlgI1o~+%~B~-!=)!Ol_Cr2^kO{mBxyV79rgt*e!z1B3NCS1-lof zw@o@~+2+!hJt<7CnOWS<+(LC z%xU6{pWrMrh=Og}7*=HnjA4Gkh9=cIP2P@Ay*+~465i{v=Qbc%O13oABn31~O7`|# zwKOl zb7_l;UI~;4uY{5{f!vaKP~DZUgu={ADRgz?*YXC;MFU)!sLVCb*L!-wgJ`Cu!L2DO z*jsa_uXjw%91wJBU_#z2>ov@kTsL9u)$Yi84F0QNwdS=qxV!4|)?O)fBAc!xQn0xy zC3my9Rkycp!tu2?xH4~W4f1*n%$9 zl**O8RvNyxws|cT?mjgjpfkj_WqRGO=N;ac%{To1Ml@9hsrdvKFD2wFo_$ z7U2|ry8&TLrV|W*j$!SYbhK@XC)hS^6Z5_sm1W_CTxFK4OtMp7UT$evs0%G(E1v3V z^16*(i|3|j-2Z$^F0n4SuQ1nTEFABi6cu`-!YK;+asRwtPmji(>GhmqE_>m1E<<67 zD@ihhKGlS>v}g`1%yUgFyu3QMa6;up<0h;quDNuH5PVmICCvk+D_dY!kWnf-4ZdcB zTyg^F3PqVuj=J{qrf9{m-xKjyMRVoCYh3!mpSWidF6Q*dg^H}qsL)NZR}6@~yn6V! z36(=uJhK7)=+Jd9l4lI^?8%ogQX1(!{e*#y=t42Br0}O*6=AU=VmYud3C)u36HB7v zW?ie-6V|va_$#|dQ~1z;EE8G;bQ%~q+A4HLYcR)y=%$uQmxxWi-t;Qn#&o9JoV!DJ zs;%I`pxA0@a1B|g4ezDp?|uDji;PO9o|1HJQ@43Ny_jHN7|kA=SaHIk8Q$zk7b}iA z{KG@bS^vIKcjpzBxF0$*__jj9J)4(hY@1|Aw@P*Rv00_RoSF2J!Yke5&kP=hf%GeOWJ3vhEwv zHjSnwHDZp!>+Q}mEL6;kCCkhV%^rI|t`RHr4l#LTNz^e?(=OrPp*;D|$(B^hV9WWI zw!(c$(hxKwNlJ5Ec#UZqn4;d{&FMrl#^)bs|EzsCm?iMvHtCDD%RN19(?p@i`+2c9 zQUu-?Npe}e5sgbLP1q2vk#aW3HB$Bl4Xc|Vme?%YYINa!SNcwksnV?ltJLu|U1in+Xh;w#-L*WbX?flx~#S6dD& z$Z4AtX)CDeM4xoMWfL1tuU%Hvxn9q(XdZBCAwM zmC9K^8v>@|clJQ~m|2<-xvO<>gYobV)+&hHR^^QLAf2s%ot~B`fffwKOa6I~(D6!dPFk6~Dm~Dh1QxJnfw$ z3k}2wUuQI|H1`TqLN76_s|XH;p2HK3`6eT~u(SPe`{A}pk2F}@gUY{oNo|+f4qDw> z>HhX0UM{nJj<|W4k$Fd~AO`ihE8&@?^o5%fo--1jvl5=iBs@=~=Pn`1>q5QL8>|&` z8nv`O%2kG7p3Em?bA`d-yF%|yMV~Oo=4Q4{BMAjlox+pQ($4$_o)VH27NA#WbjvYh=N&kn*73H zzw>jHY7uO1&d80;6;`yv2o{8OStM~SJsx9MV>;2645aAhm32@Z`7*88?gH_Xb=uvB zMdh@&30c@=SuQL_3oqqgg#whBwJI%P-r(XD}_%%j`T#^ zrqv3vw?wv*2-#NP=~^Oy%RU$tg)Y(A9ZNg?wv=p?1hicsX5E%T4G;yB=rs5jf0gNf zCYUK3Zc90S#_Bue_XB6%V;&Qh9l)@&?J6I`!COU$be>4r&nbZA+JXlw_A} zx243Yk^dOX^r3p@4k7sk-^y9H+wid9Tl^XMt&gO$!N_Hjv+lOZS@%KQ)Fa09Z8<2x zK$HL`jw%ho=M`$80Yeal)FK3rYDn)apJx~M?moD?qidgcvwgQ@*}cOXvOk&Mu)AYN zJi-3m!QEde2@YABlmxqW2X`242FtdE*6{9dyRS*(YiH6AbWQX0iyE1|HndK^>kIA4 z+TiY>ZfEV5oK$v}L^G_aUuYDxX zzC!GjQo^73q7!ODt%h-S$Uu{87(}5M0{}JYoxyixu_YD~U^B!DL)*wFbG%HQ0i&SU zU>wB?ldpGl^=;l>ZDkqOIzBWD)45P@b+janFUBbB#V9PR`s9%PiQHY`<4=T-PhOHC z95PFt^h(c|nwzKe4yAxT#-SGlgGDg8zyM5ml#=pyp&UOkJA+bIe8%s|EI&($ANMus z?9;62=Gq|ab)0l+5ABx9bvtT51`YWRr53ciwFONiZaHZl>YF{Le)F)=#1v&cE3m{) zEM{SEc{xpNJbu$#9#iG94)WN!eX;F`rTNXV9$p+xrMVPHVx>|>R{a$m_tq_h`w>7s zblAD4RossyfiFTDR}W*-`H%;?1UcJfax_o#33h#xL!6dn#FMtk5D}}a%LSW*^v?$i zb6h`P@r*3=^wY@}j9p=o=TG(iz0t05=RajWF#iJYyYxJGV9J_~&{H}k@2r>#(<7}a zXmve5K&R*l{YDq6fmNjoCL+Psg6271UE!~?K4Xy=oLBo_jrNJMuXk{jE_9WSi>6PW z_e|(6Idr2AOM^z*?fYiJVh^;k1=~o!`cflwN$(=YB(29^z4QkDYNfw=?~y;1{*32r zX*DF&++9F}#`R$8NqWt_oHa1Tt+(*n?ZM$uG~h|9 zKHH^z>Xp#gXvm`N>jT973xzH$FGvY<7gVW&gA%#hm<$uutW>{)MT$6qlzUIlf0Q&{0PV8HE; zSL<2rPO*EPZud9qjha#0cYR^{=^n?ch0xdv=eWke^l;EIHKY1~!;9As9j}gUbbY4X zxpRx}BZh?0t?m<2d+0R=3g&%BE7cY+ij*vveU^rnKMlD_xBDp7wqw^9k36vF>8D&K zWU{+VQY!yV=0!BDmHvJvZiIrWu7yeht1@UB*nohlya79$n8K2JpB ztB5co*f3Y2`%ie!poGzJeOB( z8}xoXp>nMEw7GJK_v^IEZ0~79rP=#+c4a1>=B0VJm|5F(i`2k| zprS~%LM`}(VuCWgJ2$0Eqj7%<8N<83o#~!0`-Nn-Iw46d~FDt@>K9(^r_01pO(x|hwriKItTT*Cs1yXWMZFr z%D19V&D$sCJstk+nZ?^-7zz*C{7m{D_sx`k%vsVuiuAh%Hdg%TX|G4_6ZE(;8sSEp z46&jIMgu7mlnA4M7IOXv4B9+84Y72OGVtq@Sb;5)I`1-ZU;Cj}EP9NIn>S=|wX$XL z!!}ucOZu6uG#)YAzu05DlJZqpp9w4&mapE zKU0*atN;o^@;Mhl^<4FclK1vl-rvOY{zl1*h9>6q^1LG{FVPkh5MPfB#ROwHthN!m zM0?4KsdpvQOHwwh-Sohh>2sttsc8?&32A*t(rHQWf^fto9k(ttLc2^zCuLrUgatde z;Rv4)(Q`e!IO-6~B7ULA4~2>A>+Vb`713HAT@$sSi71URnYy85ouyD-FTuF=WIVMNN3UmH8(P@JcIbOq{8U(j>=>!8ta=n%9?$AN* za(2S<2Xnb79PR9~FC-DK;bi#v_wJNx9Ij&H1}77LEcn93vVh4Ek1J%=e%b zjMv62yCB(gMBP{l@vtw7ae%S!hcK1K#suTjsi*NNVy^RiLMMjKkXzB|s5P#@XmD}* zn3SxD)wzUi;2f)js_8=AEa%f{hn^)d12eMGEQdY9e#;(Zi`k3pC1%hVHKR2-nqLkV zhp!x7KYZu#Plta!{Pb{J*6^(HSp``y4{sR$PlVOB1huTT@dNv#2l4ReLH*+wWfWbs zmWX}Pk*66^C#D-(9h1;*2+cbGeQgO88h&zAQ%`*+l9(_R0 z?arj1(lWWqO02_4+au`gR~n@djpyjHO%KS%Tgq>Ra7vG`cZ;4#bCrS1sOgYV)6`OH zz7GCbmV%)#bpEPNtkpTL!$_RJ&0lg1_Reg!q~s*_>tq;bA!SNh$Ey=R7k7$#y;8Qf z_x5>%YX5jcny+^V2Hc?PAQ}h6U~I2gRMx zvk&STH9|Kw4Jhw(i-j&2&fiRo>k4JcsKXAU^rDg|)1al_gv#Z&O_KR-Gr;~vNV~s9 zILVecd-HcKarP*!l=|yHH52Q{g+dgXLG&+7<4T5jjH1jE6e_(b zU|^-eT`9aRs27uZD6CeNU7oby;fTXKZM<7^U2eNa=XV~XHpxS$Sy^)99DU`Yf69;>0()r%Vd{>e;GTWVo zfhfA+2H%6nvYE2h{z*sDG6N0xzYK7h)G<4@NH1nd| z?Ya9Mwfe&GE>mGPgo#`?B<0|g$aOa?-hRl4^y4BOr|_7byU+1zY#!=@BO)E0mIIz- zaR=&1Mv~AEu}ftDDJj^u#IY|KRon+k*;wI-PB`lDCm|8Y%vfCPXib7LVS`rMxg7R9 zPoyp3)c4sh zK=u{c`jH*khqJ%RzI$ZasQQr~jQsJ1Pw;=2WKYQk3tRP88rEp1{`&A&rK{Jc-2$t$ z({R165fdtNW7?cXJsCxON3_neRRN@gEh9@T(I2`6HX2ymA_d`jW^wbin3SEm?$fj{ z?A9NDNh;W|U$?Yj>4AbKS6a`Jom(q=@n>G|OT8W6N+S{i{@N?`mqE3?5I7wK)>{m^D|JWx_x=-M3ElRlmuUT(2wAp7%2MUYaAH89(Pj9n(d+n|(1LEd7ma`cX2C_1YFQ4Kgugk}g0&O0nss!TGYeVKyq9{sxKF>q`F>S;&>}W48W@CLexWXH z)tmIYE{$)ig2K#@T1nPYx50+zl?G0YFAaK+V5eiwjtwnol5WF}H0Uy_pV#_}*oK{H z^+jzXL)QK9@`?YKSCIMO7}u2L`gx7=W0%d_;T)4&`{@qmt1j#+-73GJnZHs!6Z9E0gIa_R2p zdzSB2q#rQ35 zwQN_h?n(uSht4NLbHE#I3jL(JK}=oGWVC4kxCU4Vbb zU!rZ8D*MugBxa|C^s`sm&Fi!UdruR(2#I+Gm@KYq#9m$Z@>cQN+)jsoGN_WUWhfx#n3#Cn7ObP9#65gKl=Qm2vuO6n*h5w7;AoZ%9LKa{g8dm4 z#UP5RF?nm|kHMDNR6@P$3Ki!?9OqMGI7i8%4M&W&R@$nK;%?L?jSOBTOBVz;N2MV% zOKrizD5{gJv+y{ango=`5saE?lSIg!{A=cGxniAR_tApM-D&Q0j6KAcHOoMfA|u0w zfVjhA<`Yb8(ZThypbnkXn<3=~ZRgAj>4nImJvkKZ{H(F+fEKUh=uJ z^Al@A@YjbcKkTcVwvdAN9jJr`|liOIWJ*4q9CvBaR4v26{3f(i0egj9~4YFn39eLhU>Qw^`BRi;lh)TLEh zYn^iKw_G-v9^cs}VN>)NAX1enn-12XUI)CA5by)gUT$j<2}Kvchf%Jwl{te`PR_() z6b-(hg&@>^P$Sr20JeHaPEbq$d>qa!^)>BTN=12Jo}luma4Pl2?H zZ3Eh99}1Qu6NF%~QNqSsX|Szh&W;%3K%7bSmbQ^A6sb{`$Z=M)4xhd6}f zxq>0Cl($*EHh4uBz50hl8>b>?r9Rs7I>crZLP*r(by8c}_q_MUNxOephggj24-Ke?5u0 zVCIIwDL%oVC3W959O-qWe3Saf6+Q`-ztf2xKz8|Kjo8m~vMLC{5-s9=o>=BQwb3I?yoW}G-h0#weuq%Aj8GcmfZhHQ_AD!t#hepM=@Ngcp5bvitLi4bnl( z8RJ!JVSvzF{pi7o4W|wbe)YO>qg<)_QH8g;jo!jhZtbhrS-P4Ye>`-_d*!4(z%RcxtK>)WCy$LxbWuCMdqtBwUs%d?8; zv4|ealMMiU`szs9nxC@OEPc&GY;`nk4NloOwCUgp_18lVSuVhXq>?X728fZj{c|>7 zk3iJ4#2dL@C4zJQ_E@>1v-4<$2LxVA%PPf@f#6l2(nPN{MjISUjE>r34LuZV@Ptzm zc+%oY$Dec<_7PxB281T#d6fEWp0lG~2W_wFTd}bzcw8nH_!?MXZe!7o;ODYp4yeui zn;L}HW0k*7E-}j`Civ`Hwk^1U&*%cd?75QGkOc*NY8MDr&n3jOH!m0qmX|A-7K~bA zgF!?*{i7dWGp$<;}) zKftx)ZKYE00kZP|bxu@j5ln6q8u|_k)$=hBi_;4P1N=i|89RkELcS~5f}0)TVl7tW zq1fNC5m7XvOcS_M4Rc&xW_ACP61Ey4Fek>l@8prUA<&GiB&&pHw6p>j3#|_ECbT>CO7UAMl>$ZMv-yp=jpA0ZlU`9_5p!S7W6)o*%!)-6zDqoF zj+6p(54FpCh1snU#Ld@Xi8~@?APDxU{-KZ>ZlIKuCWWetN&c6@IS0amf^G#_!7HQB!U~t>jFL1!=nMWJ z3gkr2gY(!x|FKOOEKWOFe2=qOo5OU|n9dDuMF7u&&eISJjQ^)iRA2G*EVPGAq9oT+mTaenEHQy#1=HsxYu^!G_v2FX;F{8wtL~u#I z9^I%nC^ z{WvVJr3$+~w)Rlu_)GINFD~D&w22H@pwKcTfR7~>x!Qvfa>{k-4<)a?4xYZR%+su$ z%hO>kv6rA*7+@VvSyDfJY875Unb*yQmnVF%P zgGTkpgZRGYRIRvQE5T5u0apjE`3sLf`pia8Z<4qexX@P3Bt`%XLAo7AA zAPKzN1I$jA4{^_;4!PU1bEcAC=`7RSV%aHv+J4CYOf)rN@xta(od)9@-i$3ebDcK4 zSvc!FlQk(=t4izc&Aqm zF}uw4lLEQnYK<}-fG<~=`~T}gKhTiSk*5hcG*me9KF+YvjR^Z_S4g%o3u=$ zaHNNbV-jC7(*o~MN_&$MLB0s@b@;!(d2d4a@7KH+;rcE zf$Q1%iR+mXOR84JZj380*?ke^;vCF<0S$guz?xnfU-<68F+CI5p?ic9S4j-CubivY zXqQbb1p<&R^mTMqrNRO+y|V&vA>y<4HrW4^f#MsEqQ?Xa2Q43bEL?fgC@$f^#Yf#v zTTyBYUPPH_DNV|62yN0RiuXsMbr^`4K%)zdQ4o%*cR=c^G0eL^hIs>F{?(HlQJW|W z2?q)5eLwstv4o!!?dZ1Z!4baj#yA`o8q1p@8g;D;98{&-3PN$@LVENY zr3|Gz$d=0+0OFb|Clo4I+prkZX`l~!e9a&u64-RDL>8JFYv?_U=fB$C8Ruy43)mk~ z+UsQ@*t&mBMe@~hrc_MNvT3i#&EAp6msQ~h71^$Qd_VJ+A|*%UFg23G9<4{ zBNDn66T!&nkNVN`BFt^&@L+7`m$%b-lVl1$E6V+-xy{QIWH4VXA)_m zuwPPPw;JIpaC&V)FHR^uDUIT3!u!r|D7{%p^vU~3#M`y#F;akT&Fy_g5z<5BWKvsT zz_N)|c12tuZN+Wz$=VvjqNrShgWTXD-(m~Qp3dB|l1Xhft%F9(jm%ivgEtXz2e{`6Hy9!XJ5D=)DLH0R=A`Y0jDl}_9Xa8qU0aIyk zqLRQ_hLeM4F+8yW9$e(Vm9?~C`Cf=0I8StjNRr<`;*}o6YmV^bPlR_~t4Je@jx2{? z7;M-DxR(T%i;zo9^FOdksKh&uc-2T;d7^5{CfA@oHcSig@7suwV$nr7XAmQ8iv1c3 znkn=dqXf!P6buU52Meg*c>;C7Ix4y0KHgk$0%v$3FD?;I6`E-wiU36^kSOs~E1YsH zG2(gIqm?p*#ry-gJADTjPI1nF&uEXARTlD?s!0B>+)g<1IWxJC@DSAwgJX*;ovS*a zTIps~nu|)Wp&W`!CLNi?w4N{bFGOsC!{2Bp%wv^sfkS7qIVP792!OR_Vc7z^|V&0KNw+UOPXVI=>+Rok;v_kpvVG_hSq^q8vL1KhOTi8?VE6jct(jBH+0R|p?$-M2#*pm zVd$E?p-cB}aH%JOEIVC;xF|^*HAt3|j)EnI6fYnJxva)hz$?8QDfVT>QoM&0G|2H3 zU2@e4qdAC3VHIFq4H$M(5!%K2rXEH(=eJ4P7yd3fiLjD zPlxls2?)$XU=I)6-aqg?9{45&@@!f1WY-WB`11IKkRA$oIx*xu3VDP=@*6g=Y&a*# zlX=*vaR?*4BL2`evJqtTrFemIF-k!rv)VD#Vi+^jHH0Wcz*u*4xNHQUwMCojER$f99I*S-XRE-@4^LGVD*P!RhyMl>H@plDXIrP4R z=plx{Qxu{EC|QDi0ZN%4^#v%S^9PKMLDdb3dx;~k7N^57W5>D%!wfJ4jLj^aiAbo& zQ-GyE?GS3J!8m5DDo84=*TozW6E4n^y@#0PTW>IRHg=vTD^O&={m(}B=P6*?el@oK?z zglK<#w{ME8N9Wu_0+TuM{cI~1H99xP7qvP_6)GZ=FH}~}R%3d4ymUBmD0Sd(9)BLk z;M$-iG9E=G@uPdF{XU{??ARvhwHPnV{CK&=Ilg9ik|PFnkymBxDV}1wgHRg}?|V{) zHJY#f2Du_KuP`k2cf|XArZD<7bmt>uW` zD%^qvhH@(MTvKB?4lS$mPbKEDu*iZ=$K>c3sXbh1yBJbF5jqrCn9U&ETZ&EYOMD(P z*%OnoPj1FuIE_C96PX*B6k@&o6lNinq6-~j(wj=XF)AO;b&^&5wHV&?q%~k#Of%6A z9-JqXgQ7|_6vi^LMv$!*rn`7zEbF?RAd;CN8C?remx`4m=q+Jf35-7spr_lA%1+&Y zcS#AP2W6@j6lYdu)NaPk8x=-8m(NIvo9M*i4A|$=VV_H{ZRg4~=?IinF3ti966PJ* zg(<>E3;{=q-A1xfg{Eo3EjZ?x%f~|Psg{LXa6HkP!Vp;mxgv$>!!593rKd2M7ask{j&W#s9t_U-8As!MrD_FC7z^N)7|#X$#-!f>D(owc|M)|k z1g{?TuME^1BjXbzhF~XL2V&TDrNyYyrQrA(2>m3+y9SeEwy(#ONK%q5zf0VM15^v6C`FytvDs!;R3)xI zD0EGIIrl;#cH;PSjykpMSPMvVruE?TNemif)n6(uHldp|q`0G7g49->hlNDFcva7h9nRiQL>)#fwk3k>Dg@uB+#p8BSCKQf~2 z8$yptd(=W4+a;`bV^q`!nytXdw~&x9CTGTW%T}jkDa&4?|*~;K^p!S_#aZ) zLvO0%dNyjo-heLjJMuf@eGrS!mMFaU*_mn=i6jH>4j5;-IvXUA1&IA#fahWAc#%-Z zN1`v9CsU(GQBUFn73W5tD7L@iLIBQt#)hVE^@3@V57Sb0n9kO8%mr)|8XV1Yv-q|{ zXl{I|gL1czHcge)jttb)BEB3bOV^t39=dKNS|wTR{`T~v@7z{UZjY`NQ>0X#AnQ5T z?)1T|t_#hOc{I^@q%S3xtDrThRQ%ip#93m+#2@1EUm)HJ&f!VyBlwN|4GSf4)7Bp55nVnkGTC80GePIN4;GQQ} zNiJjZ6k3=Z`vQy87#AIp!7_dk`T~iY)|`H=sD@?9YH3tAWAuCqt5}!{!cg}N z;u0o?;XXbL*T2&@48OuKTtuZ7B@9CmZGBEvLe&Ae@PhJkU=^oHQ$Se?W{Jk)gkX(g zDUDHG92-w-&<+)!FO$|$_^OK4y7c%^^h1BVl`n4m_glH}{O@VyJ*Uss%1%(m_qI|Q zy#^4BmGzC}K;q#mGpM$ncQ&AQ_MP;BWO5M<$E1G8@%JmV4Dx#dNfpH=L&q>4)lak! zzLh{y)TnB?uTeiG@=^$7X>8}W}ms_LtI zXsqsd1Bs*fYRs5l5ZIqp)<-f;@U_6@1V^2QB}0plQIrR%>5YV~5qgsJS$-5##K5&`K?m1W#+TDmg}|-+V2ZZfKA+A5%rVnQzE9I<7c}PsT(K- zy$>7^?%ssnr~?90o|A^LI6LyXfIRr&gdT!D9s)$9PkO+S zYS-Yi_m&sFP8VGM#{X_tEA8j(D)qpG9@P8`y;a5*+h5<^+eb5~x8yd?$BD+C#+Hz( zhmde|3NDqwGw$>89W9e|zM~TqEaPa#Z(mP9#Q*4MKa_e-6i{Q*G1_y^GTMoZV-Yrg z4P4QV80fJ#IJ_TDU_&8I zw>XP?@8RSESLX&(^+=~K5z_~ue)4~#wOWrWU+7vqx=2tl#Tvl+xu_gpTPq;RD^uhf zauC3#vtl$-u7A6O3c^wslS9tr(*MS?Su5CA6yW~Xdx1*a^T4-I%_W}M{dzfY75J|5 z&o&=n9wLW6(sHqnD!a!kox;&@x4FO>!A#XD24HSXO2C|+_7Z83X=_|j)l?&Zie0(F z+;2ChPd0)Sdk>dlfBLsRkut8{Oy`84XqnUF>do|+JUatyPE~K9>zzft8UO9s6o*9h z<{+2&KUZa^V4om5Q1De+x#hKgzmtf)Z#n=8Dm4XP?W-xS)tt4a9guAM@vf^A zv>G-@F@5L<4bZ5l?g#qU?YdEIuu08i9TaCTe}#I{PjZiUbg}hJ+%J1M0rynX)926= z>}pLJiaUU6v%2pLJt1D(d1t9@#K79Po}hB0fqWT;IpWKMuz!@mG~Q1^Clm~+92RFK z)e?L)HpO#V*%2G6#Ue;MPh1}PXWycn35E-1jbqNDCwdcKrOoOpy@cVcg<70=(@<40 z(QeX@q>*Z*vJ{OtbhUw&hlc zTmP4vGXT|hQ*+dQa0LfE{u#2O+Hge??cb_!}OIY(#zPfXPFseJ?Z z+Sw-RN}T$U5|6>_158gl1iyU=ORVa=0eKRFx&vd24G8!Qzfytf{<+f7q^Yzc{Kk!ivPWU{~gBvVv`!N*riTbzZ5Q|P%1Zl#dQ(B zQ5G{+sjLES#ysg+x9)I^LiSuvYb9t#-F8!%K~WnhN8>T$!aYQjjY?CTMaP|>7DN@b zpt!(eTX>~XdKS!|qbf7eHf4_ta!b5fnM#s@x)E3qCHZUr!xFLPW^$`(I<~EOBgaDO zR%tr}ZB54z|KT687DjmsqiA8eq~WcCv=eip7q=?ar=x}cwr2-5@U?^n_URKYeDZ?G zV8$SrieZ*dTm~NaBMDUfB-SznDGDBFkq=Gm7h*8E5YUODGaL{s*m=OIPCCI9Ur%^# zv^T9RKiG~}_Qi3M)}2(~G`qOy(YGf3^ACK1QBBsyd)b$|+zc`s&nS^T?NS7w3 z2I?M;gd&I8FiS}vH=*2$OIC{YK2JJUGPS7K@h6_GSj(HMmTp&*K>ntJsR9IXd#%6h z0+cii`$pLA!c#V?%u=%r7U|n!8B_y&$!*lQjQ)8?Bgd#1V&WalKpE+XvEvtxXNn_; zTIRVsIutoFd0C1p1%JfK!L<~ky#CXUc2;>3^(+VOqj;9n+1yOrng` z#SZcyLU)OJX%#^R{8hL;Ztdl9nTX3k=+JE9=J9nRUN2UmGG)fV@E;q!xEHLF?840X zgDy1uY7jX-um05_5wGE0;hm0=Wp>9%&~t*CCmhu#+}0c%`Cqtili$H)#^0GF3H|+f`XC0ET_DgX z4st6soUP%zus9%z3vjkPi%+?sKEKcj4l9^7^mbGybQTCls=pD1Be_Cnu5eT%kjy9w zxPl9pp&GQ(m5Ft~^t@6xzL$s3!_gI19dIYyUHuba;=pFZX? z^2?_s58XYj+zKr_dmtlLsxK8?vD=~%E~QA?_$y+5$nSbaMEsIyxuOftlM=!&R-SqI z@PzQRgmAhf+E5ET=I_$*;rNbAqNm{!4}MAXrPwE-goi$ zSRg*z^*f}00PGDSh`Q3*0$zm8AA~aCiVJGx*98R_D-B$9Jp?q;o>zWy7iBTcEL~Z7 z8-K#e2CqU0WVovfgv0ZwY1I_)=ffr9+&}Nc%IB{`@#PRQmk7tXw0Rs?k!az+Pn9P+ zK&|}qom4&-dd0c=<#6}K_46&oGR$<)gnCxyUPC1nsVzoXV6%{EiuFo71*n~0sYOyW zTFtm0chbkq$S?!MPRr00-44+RxplpfZTu7CBo~d5+(RHa8!m?Bi!(5}p+R?4L8^`( zr3!lS)@U{E(Hoj^7p3MKHMXAN_LPJ0n?dk5JWBVCG(m~Pc<_fZ-CLBZ!_r8v;*f6? zc7#z>-lacMD;so;x+Yz-?mgWHx;?rv>?!=4!7BMb5ClXOo;ucpDVqL0DC9l(hth*3 z#X2c}KzBB5)=3?_J;h2%LwFCxAy-K|)OIu}(K-cf{Tmc!U$Iddi~0`@QmG(v2cbJg zKgt`S1P7}5py322rz|Cgfw3DYSPNQ&LqW{1P3axJY)pFqJ8ao$M9TLS`8!W*du z7uO0AmHhj5v=h?AJ;6sM1|~R!J0o$AaMBwRO?4~V+(ckF2SrU1jdWiQZp+0rvS^m# zD)=4E>i&OgR`!u^bZ< z4kX7;x~`m4MFeA~E<-p3-^}l#TS$lj%`#v+e?u~^pSwl36Ng3N34@(d(ot64%pRjV zJp@X4d9}XgJ!P6;JxWR7Xo@K8M2QM1pS8r5jqF8SB^fX3Lp4{~h7WXgX-7AFs5^rF z&2Hb9HDW8x*3v*4yT#Io*l$qqWz>S^5o$Yid%^jz5-B$BvscIZSNATMW?eS!{#Mr> z6Pl}Z5}mnMQ(g|oEbbc9f^A{?+Dn3~&B|Gt7YPmisvZf>R%StLaa>-kufcbq3aWZ= zx_K_m!o=3mmn$Of4+aKfMoh(~mY*;s2Hd}>mSR(E-+()7=|W}d$}S}w z525ZzcMr_Vk@Q0f#dRxS^BCui$!um=!a&c)x`S1h-+luQ4yF;I1$&8rbFlP;dD4rU zvFSuN=azK}4lsUZP6|&ABwc(tkb9y551TnPVU(!x+@f>&P5PP+j{0*XV`nD2K^^mW zX@pg?a=T1oB^;|()!PlUEgErcqmoJ7Ia}9wi)4=%{wlxPMg5>k%qE9f(toPCvZ-pi z=8Aq>V3t#Ub?UE46YG3`EfinC8&J?_g~n7I8rT;^M<|TzaU}gZpd<7vjO(Q>`MbiC zJ2J1DDXLE!#$b9v^q7uQW!Mu)MMYfp;#=pJR~ukTsUxB6bwrSmrEUV8eQIbhtItsg zE+|MWBv$=^h9tp?sWzo=?x#AHUfOUiHq?QZoaUloUc(EX8XHDdOw6-nqIXb3Bao zfwA#!knLW@XyC0l4k;ZR;sW`7>8!DIR8#W^1AS*ioMBK2o-V_~#K9LtB1R_VWMQJ$ zGaNdtEs5;z_-!LZ=beP$ws;M=BMcwcVhcZvEdXHfZMYE}(oB77n;pZU&??m?!Y9L0 zY={};xR||Cku6sr&TKyz7fgx8bHNm6GV>IV`>a5Oj@IJf?8@yAa4}bTiE`-}dRytr z`(b1*R|-TrK^xK;^sayj+_*2!4kP#o_sKK<$ISRYhn{;B$gA`2gt=z zo)Rl3v1p|i6vFRVz+c$FW9(v3UAB2M$-ICg;=Uz|cMih$pzRBSJORm+;3ApwF76Q|4MBB6lnTJD zIkl*a9&zzMwt(yl4yn?+b3-e>o^}*WH+jQ0-H|1a92_LzgX_8l-^LagyK|Y)iMo#T zud5SvU5mOlY>nlwMP8I~G?u?lKd=SEr@^HIg9z6hr^|5^T*h~+@$w5y-)} zNUXPX^)9W`gVc2zSH5)DmKeOB8KFh(?xs3ZOpNDf34eoo1M#K0uXK&gS$i2)0epi< zJWDW~Zq(&?(UF&N1B5Dbgux_%pJrX1_UMK!O3S+XSN<%{^yAzHhC+}q|-{GWdqV{l&E?#=A&~;S0D4^U=dz4Fqjdk&67 zerFJ0Qx=8879j{bOpb>;0Ie4Xs zXfKS{NY$MYomeBPL#2tCsYYLmwxFsRUe14l`{nj$a~s>c{X*lrS#+wF7ODO@s60Yu z|IjnZLtkD#lRhAZGr0pR3}8L)A4=J?0z-ABzE-Q)ipaC%>YoF9lLN{yAtWm>PNxp@ z%6Dh*C6~mu{#mIqg%o_P$>*x=Ty4Dcd)l~FuG;>;--_bzY(?87VHN-O{2y+_SJ{Q< zmFF39R-g>n!FTA1{#5)7{cqw2l#;X;x05&cS~JB~(YZBur{B3r6k4F-w-pGT@%pE& z{2jK?K{P8D!6N4u-Vud{XTzR%{K5uN*rYrKMB$zAgByxa9DfSnX%p#IkZu!+hel3p zp*%<}I=AOK8+51^tboGA#_)pyYKe0bg{~EawK^eCDhjXagbknpOyU9a?M6^P?%{7) z@Jy@l7M;?lr$4XLpE~;U8hGJE&C1*UzxKX9E~+a3|I7n3!|8@3Io?gu|hJx4iTn*Vxf`lt67J{{%7m2veht&l1}Y``&MN!Cx?P3j3p z58%iY+S96y=PXM}a-Nf9;Wi#JEuF>bkE5|*r}So~(KWJ49O~A{w@@WP&}2Q{w}v%x z4d3Ir$?5k6?A(N-kMJon)CbSgzu@I8|E5081xdBQmG8 zMOm)GFubVF3L}G#f*SX2_*$bI=Rtybt|Bu&cy#al1_^rfWiURP!35jEC%ji6Ao1me$m)yRa);DQf+)J5v=ZZoA6G>?f}(a|mq3*Mp%SJaYvy z!8jhc;;LeL3z>cQRm{Knh>VvP>4kG8UY^B^WZ0{Q&_4Pq#6s{Ye33DBBknQw)?VX- z%=#;;eUEjsOyHZ9eD(^&Bfe#Cs5llm(F+O>6-O#Bd@?tvx8%2Y0u+vIJd~2bWe=*Y zzpJx+LT7f$=oy0(sG8Y68I*n6oqq&3(1{tJ-~)b6Ii!F5$}&1PJuD600R}4cPgkG? z+|ctOE0(;LPbjtz-Tm?-q+55u*rDFKm3M1CyQ~lv#n@~%hdsdNvH2`D(~xPHV3=u` zW0-G9H!L?irAiJ=4lE7Q8IKsJsphBx`5!G0K%>%k%1>$^S&34erSYjvs)KyK^6X-t z`q)|TpQBaYKMz$Ynw6cuf<1vUy$XKi1WuDV&U~B6wF5I)$il8wZvdWlQz(bXk-bO+DUXKScpdr#_4M<5h^aF zq}VV<60sgy`zm74(CBSPrl`51_U5Vn(kIn0Wip2{aa2|};EArT_Y;+RS>#A?EXyL6*STMpA$_Gkq+1X} zX%tlEmY+b{+^0-Gq#q&G8kHZ?pQgIhCsjX4qhv_c1|Rz=kP;kEKFA@J8BJzlxE0QH ze{mhu_G_noPOhHrqZLluX(B~+T6A@wQUoWmE5aOkj->Yy#67Z=Zvqfg>FGsuEY^NY4M%K$I{4~M*4^%)gn?)&0#z@ z>9H$y-x~7Hj@JS|pwM4f4)v6B6sn^;9wJ#QENrIgm>oiVD+X_DhVM;jEul9k7?^ag zjMaIBRSngg_a&)2e@4B?)MeOg41JoaFMhtpMr;t7m4bQaq-eV;Eno9PS2gZ&T{vuA zM!zC?W2m87fq$r}P6|w|9%V?a9_GV5EmvX>CKzt)d=Z6Xxl&i zyAP`2163rJleFAL_Jg!G0#jI8V&X2cV&&pblrg99HkEUg|p;Ln;*!z;uU&yZOS zc$F;L5gSpFFrBPwabPvxxB+LyY#dKbRz-eE0cL8n_kXB#E7Z3_tpx-$z-)(dAYI*9 zu%o=Ab&GG~Vk8LW3FO$uf0jVDg|pzZgHZc4R58&KUK)uf^wp?b1=Ozuc{oi@!_C<4 z8W05k#J)BOnkjcJ?I?`o_9?KXLUxo5K7B={L$NC}T404Gl(GpmTZ}i)W(u;A!*PTh zkLPJ53pYw3pq&u_6hcoqgj_;Lq6cRZyoRiKv9Y|^P9)>SV)_KTV$`R@S05<7VETuX zy5Rvk>=IzS%>%`2n^5O!F_T_{j;nLEKoBAyZfu8&T;REg(%|yaR#qH@L@J92!#h%H zUQ}6Hc>{znbR&Vhl=1>0q!#D7AQM8d3}m|xNLWJ-lKH|v zow_~2E1B!Fy9$&J3lIitYBACoHKY*j3))10hMn(W9a1)^>=O$n(EO!nNZDI{Sd}h9 zHmsX{8=VHD$JSFelQdEOj!dzvqm-WfK`v1^VXhb2B*@;terW$t*2+Z@TbUtQZ*p~oyDpOO0zAY4c6EeF?>7?L|+M?H^ zT{=;FxQ6-`)X<@a%kv(5&VxysZ=#`e&9Dp|2qhptCWMS(cQ!+X0j$yY7=B&~6{9fH z5-HG&_wWVpiXy(2uXN1?h8vdV(8heqNQzD*ltVS4MnP<4ijmefnd6w4is4W3 zl@Uh>5(eQrBEGl@VEk} zG*R>fa#Uk~SbEdi0FG9S6o%pngfD{^2HT+=&%BS}>H=jwRSCekTX4m7Fr}#C z5&H~xri4~A@39sRMNlnqtK7ZFxbb%mz#oA3aoazpc>=6lQ`2ssc22jS+6jHBz1?qC z(`$bsb9WyyRHlW35}OA1X%|G^J~8?e3eA|vf%75yQUwandQBP*Eox?qd@9dAIg&8+ z4_X>DOdU%72^kvZYWdgDF_F*#LL&W*O<)OTM@kc@<%5LM1m3&>DV)#Ac$k``n)5k~ zhWpel&4}zfHHUnB`|l#GKWE?2bm|CnU&{d#Yy3<+7fV6J#4XsR5FDhv2_J{S?x2^C z`@vp08{|>+#b9J@@jbqd5{yjPQfR2?zWOjT0u^TN_A_(bJ}qbFuwxx@EDX@78TeU2 zlfS5b4BelG7(VIaPupNF>|+{4gOGn3gh7fG)C~pB?tK`ce0L)AoCVAl{pH zwxQpf`UTXJx^(TL7nVKDR|NWn2lu{#@i4^6radzCjlF@y?tOb$9s#mFjs3jvK2w~3 zR>%MEQTd*CG&A}KGpjq(_6DR@f2P5xOykDRFb&tC$RGIb#Zk^T38FQQz2T|VH9t*7 z9~;1Kqx$$ygW4bk?}cUVO@b~#YTt_)@J)i~dzZZfZyIzS`o_HxHw`*dVQJYr_@+V7 zQhv2pn_7MNrw}$n;m12>`ha6!0C-$O3yi@eUPY0VcBeFj2o8&^aBlsG50DK^8m0Kj zyNtju9H;ImeoQ4hBC+i{l5{{>g1qsu7wx-@^Hr2LY*%~>c3$Fpj?x|(l!%T%RLuYI zDKz=u^HddWYex`7QX~wV98?Ut$Wl%ODetSBc*h>jXpz0KmWLdK^w=4m3vv>epts6l zNwNoe>2tEj;f#y%mGp&#tF!!!3gaaIOhWP7r#r@d1IbrO%6nMF2GNtx(SXLpOO(F~ z@OvtgXukJ5uNhgwzpth(EpGE%AbC?-Oz9A&w$GJa+HgBhhA0ONWKBZe6!Q*pY``}9 zDmxb)adZT;^U^7*wolZ<8KQz7beiZ=6}T}%`26)8o1lLSh)-7HGEku$C_a+Nc9=Ad z@mEEYaHDTJw=hTf${x^wX(w&=4g^e#4achKQz5r}~6oibAEs&`Q~sYqoYOzIfBalE-$tWT$X1 zN&fWUa}#uPvIcNxxc&%sM=(lhawhT223Gp}(Y1j`0;SJo% zl~f##^B5>>a8SBBC|zrx)sgX#lftLU;gkA@+v1T|V!Ey<+IpL?M4OndEsC^;3rp0A z>FOe*RVPFy4lYs)SJL;Z#7*(<=@<^my!ME+r*alfmgvIDhbrk=X{u1FeOBBR;@+lO zoGzT^Z_B)oJZ!zRp$i}#!)|3b!@F7f_<+}2nQRlR~jz=mgu~V335LV#iilmZXQ{E+SCOS(D=Dml@}^cyi5KiV)=J^Td3=TtI2iJ)mWd=v%ucwz%sRcm_{41Tpck_8?i)JP~>X% zM}UkkJ?<#%Qkk_;%hgfyv{8sKggo$7t;=)FQ{SG^^J7F^#Oa97Bfk95z>MwoyDQr& zzo>LqeqPyC`Bh~Lmeo02dEJJTk`_X1O|7MiNn>HuT%X1r17K=uuM|+YQ9-*|ulvp6B*J3AYDdG41B!)FB<)k7YkZmGt|eYeHnPI+n^X z*9eWmM=wZ6s#Qry3{g@1DCj}=aVAp|i%O4JTQ`&#koyqnWEx1wsVAMJ4+0l-_-eY@D|{|^+AU!Y z8xDA7LZQ0dqH);5G%3Lmg`p8%9->-cJ_&t=CtHjCSli0KBn={Z^ueBN*6ZQPR%==# zI?IoduFsRL^S^{rI$y{@q%%@F*~5G^O}LC{9>wp#R#dl&r z_R5rN&vNh21KpV#Q12!9)=1)h12(9&Tne&Wv_IlrqT$5coP8B7QphlLLtaO-#K$*+ z-GH%cLk}qTG?DLlIBQCOM>MQ9*OJe>v1=_IOeoU{McT73Y!w!$ zh2e>v)+gbsGG|IUY_kq3x3sGqX&ua5dNC^FQdCN7RAF0jHck-`YK7in z%qUzg#{5xKTlr}afr>FVMtxj>k zDI%pcqOh$bhbnV0>IARMRjLe;j4E^0Pf3(=wJ(`b%2jiXC*$g^mi8f*4oxR#@7Cg{ z5>wi&x0K_n_5qgma7%}|^iottYg9^Gai;riCL9DLgfc3HY9N=QfY0l4)!gBO9Xf4Z zin%kYG3ukJ){+9jCD-GY^1Q1mrR35}5gDx!DQzW7sT$5G7YYyndmF({`JeYQ?88NQN7gkv&v zk>!^FoUe@1)`*O@k{L+n5$__gvnA&&xcQh2h&gm$w6jm!-|Zq+q^bU^+TXYDafaiyGx9#%|-I#RqiaJxsVi z7&iZD;)?F{v^24%!#mGVt_x;3#c+j_T6~ZAH;>eY5xh1U?&AS<$&eJJZ!o+fAv$9k z7?ZWae6_2qKtB^hU!$w3ytAiZ*y4qNuTf~b<~rqRPf2Vo9B9$Bx=sl$!6{w3h9R&~ z8f-~yEl_P=_V89uySYJgnXnRZDB?u7`RLX?d>q=gXD>s?>tyPr87j^6ndnAvc#%B3 z2lz*33`y8mp~PS=Hk1sO7S5KYE-3DFWp}$;Sstq4L*94TeD~d1=(S(Y5h!+sc0khwa%Oa?8$_H@alUj=!pEz+^|wC(Sj| zOF}=n%r*fiUp%auCA*(xz%hwsw*)O!2QAgwzmm_ z*oICJJP~ru-etQ_9y9Wdb}>Zi>&$ZUm8J=q>=&1A6%)jK?%mQciw=G z(?G|pp+JZ9%}vs3DXkp`W~m7@XEh7BF*(8CjJm>KSZ)AP%BSGC+VW!Ty&kx$%pTBw zSY-=S*Eo(dY_LJnk*jfLxwEu%{Dv+sD;exMQ}3=n>1u}1cc$`0#W8n9icmezPE>WkM+g)c|C(I|+r)&w19E4YMY6hLzP4hiu408@`=(@LhVuX#T(j_T&_}jVM6bV~sTtU??vn>3 z&jAdyhqoL=<5mg98ev{QC z)Jk76H@2hxj7zF-Hr7>M!Lh7ApzX?%so!OsW$g8Sq+4kL5OtmA28Dq8!=+#u54XJE z;sq*Ryv?}8==#`vRA>?olH9JBwhLGA5jJrDUH}6szu2_Kc8kVz_u2Zy$S^nrCdk3$v1s%t}}#RpmkFTW#kHsuNN_{g-E71)_?Bu47Tp0%&U!|5)ALKOH32@I|75vk6&wRP1t~>!l2aOC$ zPWng6F9kW%(*6F?x@djqa9`+fbnR(0MkyYa3b;`^eA9L0zq$Bo1?BdPYs*0yHa#Ut zr!b+XTc`NHxiL9-&zWm)Je?f8n>+kaFAG zT#cKS8qvZkl6BPD=Bq10oZwg&?A%<`tiHia5Fa;|t;I-OQ)&~I>&!JlM@zIW$<>Ux zZqU(E16uMiSN)j|K9x3}GB)oEjtSK;$F*SFo#-iTgVgiTcWQ0J9M=MELp&!j##={7 zVQ;Bo>W$4CoZd3>2A*?o8?~q#Mk%KB1 zR%Qq~S{908hN95#aN1;P7zJcT57A}*7X%3PcF^HOh9<77K z1f>2Wj9il>1Nyw*!c`+4x-NYye7sEx!_WILcETp9I8Sh%+FXOTprh*pF}FQg-sF8t z1v0!99(2?mys_ymb~akl(#&}VNaP_0dWDJ=x{73lLez3OHe@82VDmvWF_ldKZKiNA zBi;^gJn0}VQ84Cqz^eoZ6K3g^;v zj^Jr!_W{9{n;eM(-lrP*x$$6tx9mN}BCbU=MYtl|>%<)#vjaU}0Ip*m88r>8 z{0sI7m#=?~p4_m)$tC8r^o@|p!C6Tq<52Pc;uRmV-y|N4kO5F*VftEtE!c6*VAGpV z63z#FsA31uZqe2e@%ad807i2QmeSM}7Hvg_uA486rtrgJRPGpnaSf6bMl^ICZOUW)z}{kmXbLWWvM(c-&eC_xHo)?Q;9 zQQp&979w;AP7L=Sn;Xh&!!2dOJ{6ejv~=0^-CsclMT12c$xv6MXe-im(Drdn3bZFi zA%h7iYK)OC6r(67B0MxXjPM}i&&;rZQs3xLF}a?@7t?hXS~7opt*1rFz@j7l2hXgJ z57*5^c>SsX9pXblP?5nZQq&cN+KN(LEshecvtVmK>gRaZ8LitJ+@7r)6U?@23bo?M zYeG*?imr6sQbJLsWzblQQEdLcZ#Bz*z;|E65->$d5SD5a1iLN)ipj~aTiG!-A4oVfL_IM#TV4C}?#OJt9aU_Ml zIH>x!2p!(z6z}zj;n&3t9`UGGJm+=#cZuZlnfCyU0J7`Rkuxyx5~D7_reKCbe(uNh8FGn=W&- zO~r{d2HJ_CE?8=!y$b9B;uEtyeHEYi ziVuoZkm-Ur;zv?B%oi1+oa96qBF4~W{2S^{4Myt2KW_BVEKXGP60qli1SoF)vAo#O zQl^Ji;=qqm3>8tHY|x0QT_EYa!PO~)Q^k2)sj=U!q;wLa_Fgi@SQ7dCQD$(?a_juG zh14~YGdoW-)ZF;S@*RGNg8~|LRaJ>&BP=nv*=uZ8({PH9$g^EW^8Ndd2IbG zUkeL|`-y#Ibdb-RDgEr`QZDm~=~oFo9byIby*PHtTT`0eXT4)KW~ItP!|dW8Axrv) zdM<2t6GD{v8fF%|Ayoq};kQ-~yfsyv*oAfv6CQD=52;Z0^qEv}2KK|XTE<5JdAvW7 zczps7d)+zbx!AdK4d<_jsq-;=Y?`#(rquAhH!tqP#)AC1e!>yvtN8vW&tdgZzPM7y zfI+5LqqCtiV1H4#Z_4)}W8Rb=>6V{LH5hZvUI;a}Zrl1Clq$ec*=7G+LyW&7jUgq! zq6S+3V_N#6g^N>#tKw7a!_l{i*;n{H;&57On)vK@Fx1>!*wdT(y(^pT!D;E~;+}6| z2#T!-yTvEIBTgE^S4HIEK=6oKo{Kn&XBoj?(l*#k9IK?^!{-aCuy>J)hP z;ft+(kRtYJx76XBQINlKjd5XWc?ntxBm=cwBmU22_xlVUNu@#J-EDQrx)IF%M@$Ti zY_t6;&Am4Eh#y|w*i)X1LZ7=B3nSF-%8VXIm)4f3&ggcW)o;q^c1Z;T5O2E@kD&eK zIhv)>sz|ry$pG>7PDvwf=&a1>u9xa1X$rhmwgG6)k6qsAp}Z;0LM4q@(TQ1}P|MS* zH+puYrKXFYf5#I$&Z?kX!`kuq4DY5DMqbFbPE-$|DpN!8WGmNgCY9Vv6O)8}OgJ^C zST8nT7EbR|?PpKt8yAX0yOuewsqCQ(#gt;d9L&m6 zrq*~%?P7f^n8!Ow%^dL>cEy2Ns1}TQ&yW8{hh=P`TO4;8_1at5vEztv^6k%1c@FgWDJZPMsNIb2qc*OxTY z5(>L3hE~i|R}^b2mgs;Nxj&(0vva8n_paKfeXbn}!Q;k;bHujE%o}Y9SPJzo4G-1l^&P!Mu(TslJzNCldk`&r>3|~eNGumu=dr!wo|>^p`zdB zX%{oR<_6h`Uoq7y9K(~G$zH6$w2Sw9j|2Mv{P1od1}pvbAJM|8b1!=@kX_j=T>uvq z>-N4Nwf=F$+ao?0Q8&UhqH#p~h|?oB#&yT##^=RX1XYG_4(_QNLoiH z$D}RMMmBbKfKDG@H|u)EIXK-50^BOyMAp@vx^U6rXbjal;o_udhH>qf#EfTZbE}cC*{>_TQfzO55d&&C~CcSIdk`ixC_^jM+pz9n zZf`$`E*p`3(NY<IkL?#UGsD7cX=tez%Q#%snMPzxw6_9UJK;=w`GZ3Af+Y ze#Bs3Lafdm`DmLaMf<+uqp*D*(eL<*+N z0+8-2(?$;-7ftSR4Va@{<3u-sWsg@Ox`~%UEfMS$Ri5?jTdsY z6ydq@TJ$DHC^Nn<@L*0THo28o>*ey=Zo;;EjrSEb+vB{UbWh{H;Pz{=`hA*)76Ch_ zIKHhjid*+M6*`IMzvp6v|NV!~{_ktu$~(XnM_=N?FxPX4f9mSi zA=1S5BYN9iAlh`bG>WP%1Z>pq!7fE-+THJ}gdTzg#qIGs3H$EfsIfKjV`G%hR7ioX|(Ul{3mFr*>mY{=D+fY3pqw})Ee{&edfZW}u|e#n3GSk^d~ zVMSDc!5Vi@L_|2nryaTjxnoq$opG+XH{<>i*A#a#?!a&s^L0Yy zMi%${4r=hPJr$?WF2TFQ6vs)ABOn2@&?7VS>!vvQm6QkmIDccDTy7^{wZ%9p2T@)3 z`n>$<9p4UjT-Vr_*6HqLYF3B7D{D=iZW6O^q^5%PQec@%7NSF$`LySxOqDWatI|Wf-VzTu zakB2F)P>Q5hQExnmqQ^geN*PRTxL8{*%I^3_?Gs=2AewA^oxVGuwcjU7>hYL#bgf| zj&V1(46o$a=?3cFx%<-*lPaQ<*raE4GgyD%CwUW+fEDHP=?{9Q`CQ&lNawn!d%v2ov+FuSjSz6W4HGRoeZ-Hu$^foIQ4)?gdfgVnYe6f1?<1_1|84ZsiijaTqJ zgyTE5s;Q>xB$8oU7Vk9sKp4_NlOIG-opM(-U86ECQ=#Ug(!i=F_dXR0q|z^Nm#@y< zD7yPBhrBZT`b*Yu`yD6-9-PkZ-!ty)L+u3S{sjTxuArb(pe^X!ILO2(qpEhx_31!y zQ!9t#p!5(un?NaqHC=b4To0>i%7e4pk$wFNcb-n`;UsF|zt@TA1izAjE3c;@kkAJWoxFZnx;wHdWV=Lbdp%SD5AH^3u|& znzOdJsrnZCfJu(~bxd6nNW}D7)Y1x!1hv{K$1K(FD{#_8%E`0vog{Zdc%UC*c*LR! zO~T+Z392Q$QpYBZEV_e4zH!I^DUpYz@^D;@p4hZroH!&PzOh0pF7^)3cyPt%Qv!pw(X4OloU#VVD4OR!LL)2ZVX*zJp;X*?^`WD0U+ZQHye^skl zwnCrr;O9z9mmiPlF&)Vm-to7W)vPj}u}|+g(|*`t6Wi-!4!iGA9WK_jI}LWjGtLcX zS?d;Oe0zYyu9_V$412muN|u&B8=Z!kk1l;n z>^>%b0EY3Lfu7za#{OoC!)BQBE1Nd<`6&k5#HRblvMNXDScdEp#47_U=Q6j#C9*wUYxSY zp1?DGWh|q7r}2D4#iwC-X{`F1iaU7*VX@N;pkP(g=ne&QR_%iiKKS|HCNv0G1C$E7 zDh3%CM7e9yX|xqNVP*U{_ELeyu5sD|tm>x>PToo`Ijc_IAJ3{zC&aT?5+I^F&O5lz z`14g7T>=|(f71B#uO^^eL~zo$_x`gN77523XCa&usy@~`K5KlsZPEKx@r#~m7(YnQ z7754852+U&UT&0)sTE4k$hYQZ=B+Z#G@DIhOf&P>uD9kqzS?FQci(;EOuoRmdA8gH zHY=wvXH}Ld%WBQHh8U+mmX~i`lbLH;Yt4V$nz_bg%d)P?$;-6m&Hlg#vq-sni;6K&1ZO`z9w&nR@>;`CX?s1R8^aLqfwA*lni#Y}1;o zHTl-{rtEyHsh}uxt*Kz8H7hG`1jAZIUC12V8Mq5@Z^T`Nd$u)m?dqJB1*S~9Eq_&( zEo-HXEy-GEQ&NsLjhkdzo1c?+gYUhH=S0(5pgXI8$6J}7n{O>(<7B_lrtx=AGAVw& z@%nf!S)Eg0!hc@A&6H^Z(q%~20FDHcDLKcsI?FoQG=_nYOAE40OQz2-jT&=*@f{{x zzNsK97oeK*^RlSgh-tDF<(o1KGjnn?AIrsCZygFoQw}pSk;VFayVXSbBVpgPGv+Q> z+#dkc=&|+Sg{*>toV>?PGfc!(%w#gz)~_Xx8{jqN+1EUlWgX2ipS3P?&04@PcHOw~ zCQt&;38Ud4Fy`fFuKG#h>>R}ITiiTeoKh53E-!P9zoHa7fu-aZ$>1UCdeakG>j^8? zESue$M=nZ~wJOJ!Z%tsStJfFgtORSLHu<@B;%FAP%CycDw~D3ZSZ((HL8+OKXZ4FZ zAz@rL#il2=E3#U%@@znGfo-yhElE$F{(xy*!lZAg0*ms21e~+n)P^20a~Ro1Z1FVM&`;V3f5+>%$jV<$|I`ZwJN88Q@?-I@hD=QX;seS zIkp1I&4$9|tW1TOx%Mo7hH|!J?lMm{t;#~n0n6N#lP5d=Q5ws*F_wEL1MQDL4nq1f ze+=cB?in-IpTFfkVu#xo-wr4;3;V<*m_Rh5tS_=<+*lrY9wO%w(@>mjYyO&kv1Eu% zx6h|6U(Sq(;ygDb_HU=(#0-~hS+=9!!|YrvqHwyfOsMD`_MSPu2- zEV~tSrapRDN)qScu;xzWoVp{Xb*HQ2G(%`V?tjYvuQkylcM&DPE zKoF*{MsQ(H7Hao6Z(qG#W?%e_rUKEUuQ%C!1!Q7~DJmce1B`q?kYAW(tUfz zEgwYVAevSZMsu@PC9q@~a81;zY=p_%;|gvcp?DTqbNcw1=+%~$=Szaj@@`ClTvqk^ zq3va>(O^1B=6m%XqKPTZF;@#A1`tBeU5UbbKwfKyFx^{l>1t=)8_C$|Alp{fzka z;k*@?{n02qJ1Z~CnzPd68#P(l?CHHP6UXqu5JTn|KJ0ORW;0i3=Hvly82I{nFU?zd z^MEgdjs&WMj|4{Ij=?<^_x-r%;m*bVB<}6HBY_X#u7G<7Zaco4dmHx&+#)*?c&qA2 z;6%-lz&6|o+9QF>a5v-L9B?G?zme`ElyLy*{@rpO#W#FE$Nd`ae^$VU$N8E`QBXG>FNDXt~+7A#)O zQu!~kav(;?SJ%3p(~ z%VuTCGXvj*0dme*wg5eNc5Z$VTbj2@aiwNjZ8;F7axoB*PzvF3WljMJTZ?UwR7}~K z_FNmYU@+%>9G9x)*$2pmA%-BH#+Ye3V;{|6?8#XyX{d#zI%l(3+g!)?ArF}T^5Hz@ zXt`&-bNbAe_OCVXdh^JOIZ0pq;dAfY;p+|^OKN$>?KnF7{cXFZZ#i}C#V)CI_rjTV zTSNcwrJJduzkbR_QIoc=6}0l>X8+R!b{IRRJFrYsb2Kx;W)dDEtJkW$_jpF z1r6gMD}mkk^oY-YIET>B2)g`leupZl|E2a{ihm@(d|KbWPdUO6ei?3ZQMd{C`QN<; zz$U_XGZu&i)V^0PbpJ*iXWsX6zz&0ky^_gl-Kfhh@o1rH4NbmI*`2FYlS1}OD zRFA6hr+r!d@;^zFL7JwDEBp})dSV)aQxAw(;JOEJVZSp z6etK&%i%nbg^$X!=jPr4tEos;76;ztGd6TSRv1#D6|q9azlgDO zYp`zcZ^U(|{+-xU(-<3vo1VYNO`CM);eHG^xi!mh&M=-$4>7hK?n$tx90)hP-w8Lp zKaZPs$DNORI&N~G!F>Yv)ojLcac4Zvn20C6FM^xiYj7u{*3aW6EDXW+o<1yWg5Mp$ z0Ab-1+=PXHCvFY$LKcj7R6|IgMHl(*4p=a1mOkCMz_?@-{ju;4>IBt76n?|!-A=z1 t6F~IvfwS>z8Z?)D-a-ec3V&k``J|K2f3E*v;6E7n4+j2&f&Uc@{9kWJv_b#? literal 0 HcmV?d00001 diff --git a/16/tweak16/TWEAK2C.CPP b/16/tweak16/TWEAK2C.CPP new file mode 100755 index 00000000..78b22b77 --- /dev/null +++ b/16/tweak16/TWEAK2C.CPP @@ -0,0 +1,58 @@ +/* + TWEAK2C version 1.0 + by Robert Schmidt of Ztiff Zox Softwear 1993 + + Converts a TWEAK version 1.0 file to an #include-able C file + defining the equivalent Register array, which is directly + passable to the outRegArray() function defined in the TwkUser + module. +*/ + +#include +#include +#include + +extern "C" + { + #include "TwkUser.h" + } + +main(int argc, char **argv) + { + if (argc < 4) + { + printf("TWEAK2C version 1.0\n" + "by Robert Schmidt of Ztiff Zox Softwear 1993\n" + "Converts a TWEAK version 1.x file to an #include-able C file.\n" + "\n" + "Syntax: TWEAK2C \n" + "All parameters are required.\n" + ); + + return 0; + } + + Register *table; + int regs = loadRegArray(argv[1], &table); + if (!table) + return 1; // loadRegArray provides error message + + ofstream out(argv[2], ios::out | ios::trunc); + + out << "#include \"TwkUser.h\" // get Register definition" << endl; + out << "Register " << argv[3] << "[] =" << endl; + out << "\t{" << hex << endl; + + Register *reg = table; + while (regs--) + { + out << "\t{ 0x" << reg->port << ", 0x" << int(reg->index) + << ", 0x" << int(reg->value) << (regs?"},\n":"}\n"); + reg++; + } + out << "\t};" << endl; + + free(table); + + return 0; + } diff --git a/16/tweak16/TWEAK2C.EXE b/16/tweak16/TWEAK2C.EXE new file mode 100755 index 0000000000000000000000000000000000000000..a8b8092843eae54662a576a4aede9333a0702273 GIT binary patch literal 24448 zcmeHvdwf$>_U}$|a*`$?gi;D3hVY7Lu_ASfQotgZ`kE3!Qz}xdP@p5UOq#SXLMgw@ z1=3ThGIM=!=K|;1!u-T z?&r?uehjQ+pZ#2Wt+m%)Ywdmd!-s1$U=H9x zz@vai080Q10m}hP0V@DLz)t}+fK`B}0Cj*3fad@|2W$cS0`NP)i+~+~mjS7muN7bd zhyX1hiu{X!F2EVUDZrP2sVJKS$OcRRWCCskH~}L8cEC_TI^a&g9Kg4T?f2Q=Q{a0F zd{2SzDZq9^kp|PB);5gaKSIjXGRZ!U)gRurn$?LXJRWGV1&*H%+E=o=j*KtgXc6k$ozm3F z!djVWD~xY2tuu(HSB1{6@^Zea(1kB(q`&G82kk+OwUKRof@K`4Z)&)=VE>5uonKt6 z?~uN@)QC=+c(bgg%zE)@?HlV-cD-lHc)#cD_Q2HFbZM1&HB(nJoj142P&2if*}W4R zHFI9qvi&2xH#RJm?62vNax~oix`wg_=WctN-Hk!+!GnovGGqglGED>9KQx%WmIbW= zW@_?T8gnt{*OxPAn?aLxl8?RTv6MG{k`mg<taX`~OOPjde1yT(~_hwQUDYiDXEoXmNFXcuZBg$>Zk`$UAl1>DsrfD61eWQj&hDr7`?W@|(QI8QApd$@3iZtVVbm^+%Jy_E z61$@KDvAcGMdlxbRz}%AR4d!P|Yh>ML zyW3Ggvni`1a&oS9cFhG_g-trtd9?Fb*GDyP+BzfV&V4mu+or6h&SU%H6%KcXI=@sZ z95=Tp6*@XY`wUjm{LX4icW3v(K#L}DkVS6RwNwaeo0+XP{HoCLH|;mIq0W%*K{?-*sX`DYMRZ!1u>IJn9c;US81FL8FOvQ?ui2^! znj+N@!A28v@4)|Jcjz%$6-3~B@c7!78g%mIhC6Fr5F1g-hx{0!)wB`4JM?k%d37qn zR-;Ku7fnG|H0bG37ST4NDTpk|6O~*&7?hSw;Di9uh~_SzAhktw5MNMIknN($gGI2+ zSQzv~gRUNPvp;34XflgNlmD2~0inI`f!YxCI%jF^@y(yJCbH^xP#+vd5dr#4&()QXn1tqzFm5jV|`6mahvqf!Q<^{!Bn6lS6bvslkBl#K6*6OD4l4kPi@@uBiZn9 z;oKInhmyhS9;v#gwNiAxjEyXH@)+L$wbwN#LodmZQ21}UVC8A&%P9FAm9yRn=AUVI zMICHI{x|Ke^RnFT>XPM%*7@>;&!hv=p_+)J=F+1T18aYMmk_u#xKbB>N_X&hru>p@ z4zJVITxM101Nl)+L{b}RrR1@i>Tfc9x(%LhA`O8>(Z5CnlsR_lBfq86A9lN< z(8V_(&$v?)*%Z#vN!3EOqz||RZOvtEMXI@JrHJ)~{(`RaJF!X2HJ1hdhe20Y^sR6) zJyh)7Dafv_@PqQEapRvuqpE9mYS+8Yo10c0Ja|+(0F8K5*Q{}!4^QB2|JQm~m$}Ke zGr6oQoGxPwTew7Cn;&HwVER?KQ2wJaV)~;AVEaQ@d$`T@4cp+kl-04pb5X%EV*8`1 z&2>?OTqWcAyu4tgh)LO)PoFIf!eh0tvHEqeE7jcLw+5=anBS7!re{)nBn=}9v)t(g zwe8QjYh4%JvqL|@FqMMAbbar*RNk$~s zL#Y1pj!E0o4G)L@$7SjpC^5|7(#HJV85h>Sj}CJVuF*;d!&@0Tiz7=kPB#F%37=&L z_1Koet%-6zh`(R9G=-|!4Q4rF&Tgd#p{~i??$_H5Z%h?JuFE<3U6nd1zbm{x(HM_V z{<>WvOD}jJePhwjB-WYk}LXqrtzgT8X3AWMGW{hHj2z0ns4B^U|b{f4Us(O z%^lSPLZA0IYo^@f*W8nFuv!=NoS`S5xz_a!q&jV;bAvumeTG3xD+9{;XF?41%rC_y>Ryx%b@{C_AHFO@)l< z^3MPfNTwws?r?;b_1u^9(V8w~v>&RSveO+Mpf zhfkQC;Ws#64o&R2=f3rOj~h^bT+gu!NTz0do z0|r5q6zZGf)Q=cc+Bdq{jjj_q*C}UEk4g|TLtdVJ#qOx=_O|FY++*BlOi8h&3`$vPoSHH$ z#gQ^PHw3;PXdT2L_3*+N3#Mz~ zhp?8crsrF((o!F9c^gLb56P6Q?q1D7P-;GVR`(&jjb$CdXa}_z?O{Hg?#{@5>RCE` z1Bk6l2U!mzbR2|$NQXI`cH?Pa%6buPtnNGP^BCh1bia4 zs&k=HQOR!Ps9*wdI?v9OvON|LzUNpx){s}mT%gIdb6bYjH;eY!66Vlz?;8S>x}omQ z{su!%tZT}xZ>l?#TYo4^hBDf__5!n2>UJ^P!B6Sm+24>^TWPCn(lZ-Xq@P2PPClkJ zbm=mYi-?$+gT>;zOS+^xU*9f$opIV3%!X7FwL~|`BMhQW-NBex!&3`ll|}UUF*50_ zHME1el0M)JQR?ds&8F2Ov)CA%%n^~(m@H7(yDEtx6dp_FwmBBKAd`snzB^Q!=W?1) ziqRZBOIF5m-u7Cn3{odXi;M`}DMyBd-i$^D&vIKslcN|eVwsKPb%YW~9w#tHCZp4p zk^KY$Z3YEJVVVqGQMEA z-KQ-qlnw+g%6_xdhRUIBhlEHYVhXxuxcu$nlTZ>_O|ba|GO#6U5W$Z13?8NA5<~mRX=!kFu+4|WU{zOd6LUX%QSGpxOF4T>UdQM9XO*CC6Y#+OBm=8 z0~hc2*h8*gP!wpWmK;03B4DETKSy>6U22MRyUzyf6HTPm{AMWPd;HTGne`t@Ez*JMq3c+c+3T9z&o>~H%BsG>7HPzTFgeBl*@ULZQOw71=XPvXn(6C~ zPH4Jte9+7Hj2r3eFN~c0h~H2%d8A+a@;&CRmZzQy@B6Ayw-=%VwC#t5>AEAjBhoqP zL`KAWO!`|e^JAed{S)E%fM6x7^JoKa3E9{Kk6!eh%xVg{Kt?TZDq+SFW-Moa1~?{c zJuGZ{oNfI?*jCQAek^Q5EXR3N09_mI#cHT`!7uc3){9VP>%N}DeI>h;Z)uob>oUFN zLHTg6?rEa)lCOCoL@Fm89!LteY-WEQ86X{wxiGUJs5*uq1r0D297FGxSYcKZ^)gcF z#e)@Kb{YLfw7AT|4Xm|DbV_-tIW7^tlPrf{|7(LLe&v6-j zy6_t2yuHBUUr9~d4NxA*<^IQb;Uma2Ii&)lGni*}1`8~adn0!%V~I|kAy+!>ykVld zZzcCEXKkLq{i}bBYLul>M5nt|;2>>KUnxT-#dILj&sI zi(`4r2BF%bg@t(mS5KPMmX9U-iPX+59YUdT+_ebQP@qV0qc*y%?$F~{87L#yx3x%c zf|#oyJ#!K4C<;#l*>V!vr1(pSux<><1jejta7RXgoo!O!L z<>zm3nXd6zD0}TrL7bjzAVbN)4NpPc;nr&L ztx7lx)`Q`mv%jg(yjXu&u`I}&Ln=tjT!cGApP~=@!+!!pj3SI22N;qXb|D* zeiLq)X@|D^O@aBfI~X=U@zv8K^G&8V8>WyZ9tvW?kQpO4_G2|tQ4~EvDB*aLYHg1s z)XCO0EJxg~Up+i9bq!;yhDi1`j7OQ*pAe*HzZ4WPix?Gk^O8Z4QiXo@#+?SYz42Zi z^mzeHwyFJ+lCd`;7^KwO=rXxOhErU+T8oTMxj*7Jvuj-jjgEss!$k zS3l^K4Wz1_QkBIi=UHmgO(vXyY)GqjnN(G;3qPo-nQAhbd?xzo2W3B9L&2d++ArP! zE1`FE;hQzIQ)FtwP7QSq-SrfMcE&G}k&g#O9XU*?wKKI$;|#2UgHuk*#>bIGZ$DOg z+ewwAJj7$1!GDb2PS_2-(0h@^(R0Mmdy0jNd%>=y3!jW`F_{{esty!B ziq_C0Fklr%K@73#tBt|xsJa&*T#*?Wso06FMJ5>>sx>_4wuY{!MqJTmHHG(Rr1qKM z$cN!q!HC!&L(l*=(?N^6+=f}zoX9P z8W54XyglcVUmMvJ8OiH(e{^k=`vIlW{x498wCF zn}jj^DWeL?c@Mei9>`Bu&~pxBz&(uk<@}4SMdxJKIVhhEt_zb*q}+ROg4+*PCsMVp z3(gG&q&Kef%95ui>qy3dz!7FXvT6oSMlRMc?_^$5*^||gaT;fgo^-y~m(%Fd0a*8` z++-tf_5loMR&ee(UYz@ z1BXpW#JBqR`hiiQ91@MNH{>E0K9_n()Zd*DX4@Rv*-svyw=cXrs;vket5;(*dvHe}Cd4TCfl|yv9Yj@;qvI2gYhFLJeYa zyhfK?c@8z)@fw>@1HpvT@fv63%G0Qksnn3On_yDzG1(g}CfWpcTft2^yA_$u$ehG8 zSETaHw~^U~%uPIVLGR2(JTsp%c{975Z84$4@-ay{nkxsP(Pnsze>&e-H^ zo);d4JfbVgtB;Ydla{D4iCVQ&4Kk{>?!i%GlgT%fZV1FC)N0=YPiMG1oRey6Gpe-4 zt0>cJwKpeMX+xE_<5iT&w%Xg0s?h0uj8LOND6DxrD>V9KK2VCvXl|nqr=IxfHAY`Tl7|R`UeL}Ws`bSCef_#XtCg2vEIO`29iEEU zc+F0vjprv)$?gFr??649GQWh&(Pw(KN0X=bYGQhOhsLIN+5l~j{mDr))6o2sS@xaZ z9n{r7p5KvS|7d<4puj&fzg*PoJwHS+Ov(g(T-e$Tc6c*u#xftGsC@JHT`nw)q+eZ# zxQ2>Z3g5yX z^GtkMh*%a=jI3Hu@owd=gi;I_seoL5T(!XXiOSe?bq63Mvmi3MHj*xtDvyFEL~$iE zp6DY_2S5`WO#=r4`Pkc)rJ9qM?oF$GvjLhBB<8r%ii`|ZDx|@IOoaoPT6-{V6;p|v zX9o$A)*VHksDNnd$E_N_fs{gcil(~_H#IUiFVvZ8S$CTQ?m|C?LY#-{`Z1xq4JVPQ z{g@UPZ-{NpTpL7Q?`}gZK@UGXf?B!VZSa+l07q@Wmuws?ls}vzMgMl-g6xwBh2YGX ztOu*ccDKPu)I*JuZc#1C2hiy9$7sZB7i3~}j057C2y5YI9PxP?H~6HyBwm27qXJTaci~8}-DRTV3+N=1t{K!*DHz9&UBj2QiNwglYw<+9`~u49gy)L#Uam(jx0@Gkgu2fD%!ZS5wY(K8_ zHqx1sXRkE#wPjbg9Q4%WyHAbgQMK;8u{F$pI|hgAS71jRG3e={*lHJUfbfW`F;Lc{ z2^2;7_9o?xMzxVSuJitnb39%C56!ZlqD=j`kxw$JgJ{7D11-rsqahSje|h){`GP`u zBF?%WBb8X%y~K!u#6%ud_6S4C)kRc453Z;QTCJc+2^K4Oa%Cw_dtmFSs_!p@!4v9~ z3weJ<$YU{4Gan7BK*}2zx1g19wz{0TTCC=3@$WMY3ug}qcX97Zr9 z>7gpW?jt0K3W;J~O)Y)~#XKb6TN_nJaS9SQ0z^-N!pr2{3&A+fraF~PS3@0Z0ml)d zvvs~5PF@2G&yR0)aJ@dFvmIr(qbM+8l(cni`}?druN12yi_@5kz2rNi9g=%d*N!FP z#?*;${3t;>9YE|_7oH*WVv_NmL``m2!KYEBxc?y1EU|9liFkP-$}P|w)yZ>&zKJX& zj>53e-%7JeV%~H*Bv5b|fV*ol4x7k(qkoYbsh8TkTN|*v5x)`jKj4iM-6T?R43?z< zL+pLH1BA|EK_4Qxn;>~Xup9~AI|{h5U`18Sq^yu^-{54%5*veO|23W$IVzXiuF8ipY(Bd zAWvw+0Vz}Ox5f;yhlmXAdD>a(z#b#HB#E&w$c!#-Y+;+nRR~@b$NcwTNnbncsSa+3 zC5GHc@gr<--ObqD^?|*x0i=4SQ8 zL*PqTrNS#H5DU*pw4vlbFONF~+8~X>m3^tWv9p zn;7kRc#W(NtuKPst9sKKlA#RQ@aM#kGyd+7Rt!nP9cSw#TrUw-mOZ8-u}GaEj9-Q5 zH1@pSWBcw<8~sRaRA%IcTa2UeNq$Iifj*Y?o&!l7rOvnUh+x8+=SvPk~My!{~)#_CLEkXRgYCyrVz2m!MIrtx8S%(9q zE3rI{H6Ig>Z^cp(k!Enw!V+t=uUg0wPQ@v$p`V-prmF zTR*EP1ky*e7QB}vT7*=UoIvVvVtn5vO}%{Uk{-tedKX@jP&J!#7Oa#eASU=V5DAxHa%%2Z&t_t)z!xSQJzvuu1&gkg!4fkoA@mMo%eZ$hn_QfsCJHSm;h-e;`BWNxesvmsj>FF@XoQ1r6@|bWtO{HXQ1#NyxOd4zVB7=y zZ^eb7!O~%SV>iVWS*bcYlT*>ed8`X>V7QwWo6*c6ifYJ9RdYyDP-tr;4{fQLeYFS= zbd5-AA>~~y-bI>bP;X81GYd3LM4Y)w7k)yC6b(mc!L*L~S3*TRC%yfD8J#|gPat&E zd2lq~&OJ-+oNbJj$OQrVe@d=}<}1m?SHz>V#uIYzF!ra2YAMG<5ttY0cew~}W+v&@ zXrfl*2&F%ehPnC}*@O=;$_{T#Eji%@$x zh^zJy>079?WQHX~+W4;^(oY-z&SZP|WU+4$E0ZRB3$6@dvORq#JA*pA`egql*6)jk zD<^xk^}D%;)^B{}!u)Au{B`zYZ@~^$50{i{qfSg00TP^Pzz4&{;Q|qF_6kT_kTy}o zK|_H!b$^9VL8p3YjZSXB|BSj*PW5~~qFcKmM2-ktdNltY$-js3@1gt~L3ETNik_s0_+=i>yQ_u^aX(V7zMWgj zYRE6Xz_Z&mQTAYe==&_2{mJDKDqmx_X+@yB!v^Q5b6?o)|s{BXqTafB5oR`i+<*5jjb0lwsg{8`C8e}#V zi_;j#kPczNE?}4%(QvHbX2hJj?3iLOCDRymZq_A zTOLAh5@##*mA_Yj9bqos#mR&Bkc!<&?J8!S^JaNkK1H>6n_30_AsOj30J8XzQLtbb zdK!v|210B|IWVMMZ8k`9rJ7x7Gy+}E?Q5yDak4>N%oVL-mOYiPYQ+@iQz``)i)Z19SOa# z|G%zSeY=sRtUlf{&q+s(z>!3b)VT#0gWK~IwQJKTW$7qOL+%gzrs6ox25X7`83I~vqtfqA871DELid-p-kT!fvAd)DfOABF%{d|ufjp(s3{-Ma zrSz>XRGPsnQI~z{-H&?tO1*s4yT5NeG*Qt@!2l@`0on&OWRdvj{xhZ-Nuhq%F1E>4F!pDQ6EeHl|Xnhbr^?p3oX-zsbEhFoF8C zHZtaJe0mhFPc7F_$-8uN@;Jhe##xkFN2x@e?HaW&eht~)xFykMV!X{w@zkhzYHD&n zyuaNv=6@#IcLN)Yxq04X!b=(5NUaoeN4c^WskXzR*Ecq6;PGUsvFq{B4~d*h!p zbO&9_(~U^W6YY(!CHj9h-fIg|BA;C#p7(YE` zGfjZ+I;h6P6jm=psIXw`{B=_ zFP_0S09E^M*4)m?rs^^i4qFv1z1cr8QGhLB_n&n;2Atac7u|^lHf9YS(#3ONKAlP! zj#HX+KFgG5op0!r7M*WUWZ3S*x)XTU(c;+Mq&rpXO2Nw&c;hW8VLXMuheFwE#2zoK z;5AhhM-@E>g zP#^T5rq99X#SnxQbg46Fz&*HlKanf?K@+Ms|N3g1e^OH(|P?vcy|~o*cJijyFBF(lM+2u@bM(F?+$1Wu*&! zj`Bs0hkd1s@Lj&bF}r+`ud1ZjOE_nlrk9tYt*^pS?BIPR^|ZpVsB~$G!&mMoE^~}3 zEnBeEzp&({;>VCTofl=AOtV*(`HELeawv^~$YkEjP1JI#W3p0@x>(>XDfUrTvDaI? z(ot5ttYoTb+EUP?7}O{MHGqP*#NjRZvA@(?vM|%cVnaGcK3MhmLlq_7%q1foH{a}7 zT;g-gDp_1wfkuvnC5uYSN{Narp2z0Sb4+0=PvE~}{0cTM{s0Ev!s&mlUGt8 zjcFd$;-9cZyXDH#UOBn4jOT$`t)Lf;Mq}C_{XlEFet_0~!?>~Z;Xiu)4TA?;lRy2( zjnay=eS%-}sJZj89TwJw{E%Ps3dIMu=X_~Y_Y4~Va znodYd(Z@cNr+)em?r%iWkd_|HN$VF+rP)mV`}a4R($d7VRI@cLZ9tkOEnd!+drQlF zj*11vWs4k>9E+BgD}uYcoU$Re%Zjns%gTL@rKM$$mn^)h?s*x1v$p~8F5q*(H-Hqe zMYtA_0muc+0+a&+fK7nk0{#GK0JH$YfC~Tv{{HR|zzu*Lzz+fWfSCX{-~qraz-+*S zfQJAcKmnixPzk67`~vVxz^?$m25bRr1-t;*26z$h8^CV?vIlu5TBXl$Dk&WOo*02vU}6_diq>hqt7x*x~aQS1duLd=R~)tlYnN zi9=B=aqLt*^BC03U=g^k9iP z`xr@!y^H-EscGKD5T*(r`Yd-mR=SwowW4H!Dr(C1$EJJBD=KbMy5oYEwDx{T1dn$% ztE9reROxCdGE10?$XdJ<+sDF{j*=A^2Mj=OrL+$%L@p66sXO*i+2dv9Rb}ePV=5Gl zPL2*fWrY$F!S8WZAwNfWN?Q ZGmOBu!#s-8TSrp*ex$$u{Qp9M{{z1i9ccgn literal 0 HcmV?d00001 diff --git a/16/tweak16/TWEAKOLD.DAT b/16/tweak16/TWEAKOLD.DAT new file mode 100755 index 00000000..d65d2712 --- /dev/null +++ b/16/tweak16/TWEAKOLD.DAT @@ -0,0 +1,44 @@ +5 + +0x3c2 Miscellaneous Output +0 + +0x3d4 The CRT Controller +18 +0x00 Horiz. total +0x01 Horiz. disp. enable end +0x02 Horiz. blank start +0x03 Horiz. blank end +0x04 Horiz. retrace start +0x05 Horiz. retrace end +0x06 Vertical total +0x07 Overflow register +0x08 Preset row scan +0x09 Max scan line/char ht. +0x10 Vertical retrace start +0x11 Vertical retrace end +0x12 Vert. disp. enable end +0x13 Offset/Logical width +0x14 Underline location +0x15 Vertical blank start +0x16 Vertical blank end +0x17 Mode control + +0x3c4 The Sequencer +3 +0x01 Clock mode register +0x03 Character gen. select +0x04 Memory mode register + +0x3ce The Graphics Controller +2 +0x05 Mode register +0x06 Miscellaneous register + +0x3c0 The Attribute Controller +5 +0x10 Mode control +0x11 Screen border colour +0x12 Color plane enable +0x13 Horizontal panning +0x14 Color select diff --git a/16/tweak16/TWKUSER.C b/16/tweak16/TWKUSER.C new file mode 100755 index 00000000..2a6405f6 --- /dev/null +++ b/16/tweak16/TWKUSER.C @@ -0,0 +1,134 @@ +#include +#include +#include +#include +#include + +#include "TwkUser.h" + +/* + readyVgaRegs() does the initialization to make the VGA ready to + accept any combination of configuration register settings. + + This involves enabling writes to index 0 to 7 of the CRT controller + (port 0x3d4), by clearing the most significant bit (bit 7) of index + 0x11. +*/ + +void readyVgaRegs(void) + { + int v; + outportb(0x3d4,0x11); + v = inportb(0x3d5) & 0x7f; + outportb(0x3d4,0x11); + outportb(0x3d5,v); + } + +/* + outReg sets a single register according to the contents of the + passed Register structure. +*/ + +void outReg(Register r) + { + switch (r.port) + { + /* First handle special cases: */ + + case ATTRCON_ADDR: + inportb(STATUS_ADDR); /* reset read/write flip-flop */ + outportb(ATTRCON_ADDR, r.index | 0x20); + /* ensure VGA output is enabled */ + outportb(ATTRCON_ADDR, r.value); + break; + + case MISC_ADDR: + case VGAENABLE_ADDR: + outportb(r.port, r.value); /* directly to the port */ + break; + + case SEQ_ADDR: + case GRACON_ADDR: + case CRTC_ADDR: + default: /* This is the default method: */ + outportb(r.port, r.index); /* index to port */ + outportb(r.port+1, r.value);/* value to port+1 */ + break; + } + } + + +/* + outRegArray sets n registers according to the array pointed to by r. + First, indexes 0-7 of the CRT controller are enabled for writing. +*/ + +void outRegArray(Register *r, int n) + { + readyVgaRegs(); + while (n--) + outReg(*r++); + } + + +/* + loadRegArray opens the given file, does some validity checking, then + reads the entire file into an array of Registers, which is returned + via the array parameter. + + You will probably want to provide your own error handling code in + this function, as it never aborts the program, rather than just + printing an error message and returning NULL. + + The returned value is the number of Registers read. The &array + parameter is set to the allocated Register array. + + If you use this function, remember to free() the returned array + pointer, as it was allocated dynamically using malloc() (unless NULL + is returned, which designates an error)! +*/ + +int loadRegArray(char *fpath, RegisterPtr *array) + { + int handle, regs; + long fsize; + *array = NULL; + + if ((handle = open(fpath, O_BINARY | O_RDONLY)) == -1) + /* error opening file */ + /* include your error handling code here */ + goto fileerror; + + if ((fsize = filelength(handle)) == -1) + /* error acquiring file size */ + goto fileerror; + if (fsize % sizeof(Register)) + { + printf("Illegal TWEAK file size: %s\n", fpath); + return 0; + } + regs = fsize / sizeof(Register); + + if (!(*array = (Register *)malloc(fsize))) + { + printf("Out of memory allocating buffer for %s\n", fpath); + return 0; + } + if (read(handle, (void*)*array, fsize) == -1) + /* error reading file */ + goto fileerror; + + if (close(handle) == -1) + { + /* error closing file */ + goto fileerror; + } + + /* file read ok, return pointer to buffer */ + return regs; + +fileerror: + perror(fpath); + if (*array) free(*array); + return 0; + } diff --git a/16/tweak16/TWKUSER.H b/16/tweak16/TWKUSER.H new file mode 100755 index 00000000..dfe79a86 --- /dev/null +++ b/16/tweak16/TWKUSER.H @@ -0,0 +1,45 @@ +#ifndef _TwkUser_h +#define _TwkUser_h + +/* + xxxxADDR defines the base port number used to access VGA component xxxx, + and is defined for xxxx = + ATTRCON - Attribute Controller + MISC - Miscellaneous Register + VGAENABLE - VGA Enable Register + SEQ - Sequencer + GRACON - Graphics Controller + CRTC - Cathode Ray Tube Controller + STATUS - Status Register +*/ + +#define ATTRCON_ADDR 0x3c0 +#define MISC_ADDR 0x3c2 +#define VGAENABLE_ADDR 0x3c3 +#define SEQ_ADDR 0x3c4 +#define GRACON_ADDR 0x3ce +#define CRTC_ADDR 0x3d4 +#define STATUS_ADDR 0x3da + + +/* + Note that the following C definition of Register is not compatible + with the C++ definition used in the source code of TWEAK itself! +*/ + +typedef struct + { + unsigned port; + unsigned char index; + unsigned char value; + } Register; + +typedef Register *RegisterPtr; + +void readyVgaRegs(void); +void outRegArray(Register *r, int n); +void outReg(Register r); +int loadRegArray(char *fpath, RegisterPtr *array); + +#endif + diff --git a/16/tweak16/VGALIB.CPP b/16/tweak16/VGALIB.CPP new file mode 100755 index 00000000..eb657472 --- /dev/null +++ b/16/tweak16/VGALIB.CPP @@ -0,0 +1,386 @@ +#include +#include +#include + +#include "misc.hpp" +#include "screen.hpp" +#include "vgalib.hpp" + + +GraphicsAPI::GraphicsAPI(int xr, int yr, int vxr, int vyr, int clrs) + { + int segm, offs; + xres = xr; + yres = yr; + vxres = vxr; + vyres = vyr; + colors = clrs; + libID = "Generic Graphics"; + asm { + push bp + mov ax, 1130h + mov bh, 03h + int 10h + mov ax, bp + pop bp + mov [segm], es + mov [offs], ax + } + font = (unsigned char *)MK_FP(segm, offs); + fontHeight = fontWidth = 8; + } + +void GraphicsAPI::hLine(int x, int y, int l) + { + while (l--) + putPixel(x++, y); + } + +void GraphicsAPI::vLine(int x, int y, int l) + { + while (l--) + putPixel(x, y++); + } + +/* + * Generic line drawing routine, using Bresenham's algorithm. + * Taken from Richard Wilton: "PC & PS/2 Video Systems" p. 166-7 + */ + +void GraphicsAPI::line(int x1, int y1, int x2, int y2) + { + if (x1==x2) + { + sort(y1, y2); + vLine(x1, y1, y2-y1+1); + return; + } + if (y1==y2) + { + sort(x1, x2); + hLine(x1, y1, x2-x1+1); + } + int dx = absolute(x2-x1); + int dy = absolute(y2-y1); + if (dx >= dy) + { + if (x1>x2) + { + swap(x1, x2); + swap(y1, y2); + } + int yincr = 1; + if (y2= 0) + { + y += yincr; + d += aincr; + } + else + d += bincr; + putPixel(x, y); + } + } + else + { + if (y1>y2) + { + swap(x1, x2); + swap(y1, y2); + } + int xincr = 1; + if (x2= 0) + { + x += xincr; + d += aincr; + } + else + d += bincr; + putPixel(x, y); + } + } + } + +void GraphicsAPI::rectangle(int x1, int y1, int x2, int y2) + { + sort(x1, x2); + sort(y1, y2); + hLine(x1, y1, x2-x1); + hLine(x1, y2, x2-x1); + vLine(x1, y1, y2-y1); + vLine(x2, y1, y2-y1); + } + +void GraphicsAPI::bar(int x1, int y1, int x2, int y2) + { + int width = x2-x1+1; + for (int y = y1; y < y2; ++y) + hLine(x1, y, width); + } + +void GraphicsAPI::wipe() + { + bar(0, 0, vxres, vyres); + } + +void GraphicsAPI::putChar(int x, int y, int ch) + { + unsigned char *fptr = font + fontHeight*ch; + for (int j=0; j>3, 16) + { + libID = "4-plane 16-color mode"; + outpw(0x3ce, 0x0f01); // enable set/reset + } + +void Planar16::putPixel(int x, int y, int c) + { + outpw(0x3ce, 0x00 | (c<<8)); // set/reset to select color + outpw(0x3ce, 0x08 | 0x8000>>(x&7)); // bit mask to select bit + unsigned char *pos = graphScr+y*xbytes+(x>>3); + *pos = *pos; + } + +int Planar16::getPixel(int x, int y) + { + return videoBuf[y*xbytes+x]; + } + +void Planar16::hLine(int x, int y, int l) + { + outpw(0x3ce, 0x00 | (color<<8)); // set/reset to select color + unsigned char *pos = graphScr+y*xbytes+(x>>3); + int mask; + int shift = x & 7; + if (shift > 0) + { + mask = 0x00ff >> shift; + l -= 8 - shift; + if (l<0) + mask &= 0xff << -l; + outpw(0x3ce, 0x08 | mask << 8); // bit mask to select first bits + *pos = *pos; + ++pos; + } + if (l >= 8) + { + outpw(0x3ce, 0xff08); // bit mask to select 8 bits + memset(pos, 0, l>>3); + pos += l>>3; + l -= l & 0xf8; + } + if (l >= 0) + { + mask = 0xff00 << (8-l); + outpw(0x3ce, 0x08 | mask); // bit mask to select last bits + *pos = *pos; + } + } + +int Planar16::getPelPan(int x) + { + return x & 7; + } + +/* + * Chained256 + */ + +Chained256::Chained256(int xr, int yr, int vxr) + : VGAGraphicsAPI(xr, yr, vxr, vxr, 256) + { + libID = "Chained 256-color mode"; + } + +void Chained256::putPixel(int x, int y, int c) + { + videoBuf[y*xbytes+x] = c; + } + +int Chained256::getPixel(int x, int y) + { + return videoBuf[y*xbytes+x]; + } + +void Chained256::hLine(int x, int y, int l) + { + memset(graphScr+y*xbytes+x, color, l); + } + +unsigned Chained256::getOffset(int x, int y) + { + return (y * xbytes + x/(vxres/xbytes)) >> 2; + } + +int Chained256::getPelPan(int x) + { + return 2*(x & 3); + } + + +/* + * Unchained256 + */ + +Unchained256::Unchained256(int xr, int yr, int vxr) + : VGAGraphicsAPI(xr, yr, vxr, vxr>>2, 256) + { + libID = "Unchained 256-color mode"; + } + +void Unchained256::putPixel(int x, int y, int c) + { + outpw(0x3c4, 0x02 | 0x0100<<(x&3)); + videoBuf[y*xbytes+(x>>2)] = c; + } + +int Unchained256::getPixel(int x, int y) + { + return videoBuf[y*xbytes+x]; + } + +void Unchained256::hLine(int x, int y, int l) + { + unsigned char *pos = graphScr+y*xbytes+(x>>2); + int mask; + int shift = x & 3; + if (shift > 0) + { + mask = 0x000f << shift & 0x000f; + l -= 4-shift; + if (l<0) + mask &= 0x0f >> -l; + outpw(0x3c4, 0x02 | mask << 8); // write enable first pixels + *(pos++) = color; + } + if (l >= 4) + { + outpw(0x3c4, 0x0f02); // write enable 4 pixels + memset(pos, color, l>>2); + pos += l>>2; + l -= l & 0xfc; + } + if (l >= 0) + { + mask = 0x0f00 >> (4-l) & 0x0f00; + outpw(0x3c4, 0x02 | mask); // write enable last pixels + *pos = color; + } + } + +int Unchained256::getPelPan(int x) + { + return 2*(x & 3); + } diff --git a/16/tweak16/VGALIB.HPP b/16/tweak16/VGALIB.HPP new file mode 100755 index 00000000..9fb45a92 --- /dev/null +++ b/16/tweak16/VGALIB.HPP @@ -0,0 +1,97 @@ +#ifndef _VGALIB_HPP +#define _VGALIB_HPP + +class GraphicsAPI; +class VGAGraphicsAPI; +class Chained256; +class Unchained256; +class Planar16; + +class GraphicsAPI + { + public: + enum HJustify { LEFT, HCENTER, RIGHT }; + enum VJustify { TOP, VCENTER, BOTTOM }; + + protected: + int xres, yres, vxres, vyres, color, colors; + unsigned char *font, *libID; + int fontWidth, fontHeight; + HJustify hJustify; + VJustify vJustify; + public: + GraphicsAPI(int, int, int, int, int); + virtual ~GraphicsAPI() {} + virtual char *getLibID() { return libID; } + virtual int getWidth() { return xres; } + virtual int getHeight() { return yres; } + virtual int getVirtualWidth() { return vxres; } + virtual int getVirtualHeight() { return vyres; } + virtual long getPageSize() { return long(xres)*yres; } + virtual int getColors() { return colors; } + virtual void setColor(int c) { color = c; } + virtual void setBase(int, int) =0; + virtual void syncWithRefresh() =0; + virtual int getColor() { return color; } + virtual void putPixel(int x, int y) { putPixel(x, y, color); } + virtual void putPixel(int x, int y, int c) =0; + virtual int getPixel(int x, int y) =0; + virtual void hLine(int, int, int); + virtual void vLine(int, int, int); + virtual void line(int, int, int, int); + virtual void rectangle(int, int, int, int); + virtual void bar(int, int, int, int); + virtual void wipe(); + virtual void putChar(int, int, int); + virtual void putText(int, int, char*); + virtual void setTextJustify(HJustify, VJustify); + }; + +class VGAGraphicsAPI : public GraphicsAPI + { + protected: + int xbytes; + static unsigned char *videoBuf; + virtual unsigned getOffset(int, int); + virtual int getPelPan(int) =0; + public: + VGAGraphicsAPI(int, int, int, int, int); + void syncWithRefresh(); + void setBase(int, int); + }; + +class Chained256 : public VGAGraphicsAPI + { + protected: + int getPelPan(int); + unsigned getOffset(int, int); + public: + Chained256(int, int, int); + void putPixel(int, int, int); + int getPixel(int, int); + virtual void hLine(int, int, int); + }; + +class Unchained256 : public VGAGraphicsAPI + { + protected: + int getPelPan(int); + public: + Unchained256(int, int, int); + void putPixel(int, int, int); + int getPixel(int, int); + virtual void hLine(int, int, int); + }; + +class Planar16 : public VGAGraphicsAPI + { + protected: + int getPelPan(int); + public: + Planar16(int, int, int); + void putPixel(int, int, int); + int getPixel(int, int); + void hLine(int, int, int); + }; + +#endif \ No newline at end of file diff --git a/16/tweak16/XINTRO/LIB.EXE b/16/tweak16/XINTRO/LIB.EXE new file mode 100755 index 0000000000000000000000000000000000000000..b9dd016b702b459355a745b07128517cca67caf1 GIT binary patch literal 9446 zcmeHtkAGCvweOxYKM7$77y}}P!O}?lnen}*rYQj>$*AQ=AdnzPQi`eA3fN>OBfS`c z(_l6yj8nB9)6Cdw zz;ytQ0UB(KU1MjA15N-e=yMZbDd2I?{|qoYg|Yj_Gxmv-u?Z6yD*;pi-UPG&-UDo! z%-9aV^MKz0_5r4%?{q*6&vUL}tOD=|;E#X^-~!;`bjBV7)Pe5SYZfG4hFtRC{%*kN}iTW9&)5>wr^$L4a~SW3vGF1AYY90(c2<2+%N{ zu@yHk_7I>3upiI~Fl9291^5x<*@OGP0V04ifC~WU4930#C;@bJL;(YU z5kLkMe+R%1kiX_k<}8T4Y%X20bUFWf;G8pD3>EAsyO6Q8scT2Yh2}KbUS?^r*qZ-j zcE&bYLM>BHHUFm>*!7l{bS58TYk^fJN`it|xg~d3HOo~qylmdvy6)}=ZlNXjP-Znd zY-hP)Taz-+gj-NKBHy+vCCuHLyL+3GySq{0=T@(LU{$1~*}|MLyE(K%BJpaIQe0G4 zER}>UsmW14GKX?^KBeTG=IzaYffOH@LoE}Grh-_P84_$$a)yi+GKW@P;j&k9xtO(G z!6m3TW6$VgO|gGgLSJp#W;CV9vHwX~v81e=ALj2je$b*YLl;4Fhz~Tj)&I@hVq!ff zn-4*TpF*Zx+m(wSa^eFo?p1nDUfMWZZHZr%G)EUc8w47qi?UL77 zrDf8s#u~k&gj#G9k}LNIrNv%gV1EZ}+Sw%bWzfE1V4nqc^6@10DW&Dw4-M=Sz-HKz z*q=@`$0}2(bjei%hs~ z3N5-jAoDzh9}X8M7*mTAd57z&ow50eaPg>oAI;5&{rJDJeNiIOmh%yhxVtfS0&5*q z?&lE@IAaSEdhw{%6D}T+Jx0(YsQ71H?ZMmKtnzcW6 zEv~Jq{^6q={WB+|u%%_?hPKny+EleJjkgDTRXZ;}r+O4#d|vffc=3ShvGL*ys>i{L zhg45WuwpVV9#)Hh9BJxOtvf2t@#0b5i4pFz1S_0s@i}f$i_h~yMJ*oSg?PTe3vFug z5HED7#lyTX1$xRkJCm4%B`~Nxz&{wD~~!LnIV{iAKpj<@m7?Cy($KfgH0d-&1pj!0ft^)z2v9{E$Vqnxrkvb&p2EP{Lg zvriq3EHBF*;-8uNCv{X$Dgxi;O?$i9WmB^*LDVv3Bzb;^_n949b#tA=}76411;?BR0Wd%P2ufx zblqphW=kTalPQQjVxE)2d}n#*JT$O)6I=XP)dpAj8t>YT>s|Bjn19PH?p)VW--g?k zJ+i*aRkNwaTebdnSINd|?;{&G)VStvd~8$oBM-0hx@NDR(mx~ev8 z^gX=JwZ3Zo#_CPLt=+hRU54zzwgY>V08OkvHIT(Kx3R3I%z9=zmBa+Q_+No-WW2BI zZ1OLwzTjt!`R1xlg*CNix8)tJo`4O|{9{|wQOx%#Q&TJN={lAC^O+AMbTFu6yvIaY zyXsl6HJkR|FJ?9!4~E~_%C;}m|Hww)at*$@!>6}En)WQU07CGBosh)#3iF!p9(;9n z>uYbZ*B0;35i_%1d6H!{W(63(^j&lH9l^|7S@w|oBh@m&<(h*jj#CSjId^^AXDX`y zE_=f_f~)W38^y)Azv>&|?`HAbS0(4)u%tBnlpM7$*v@YcGLE6&-lM#;P07CW78`sm zP!PgYr#3&}*d1a`&S%)}=Wu(T?S28bUo!Vc*h9@L9J^n_>#ta|4j=n_B^O$luap>U zM|Tu37HoezjWwH0gTG(l&EeF1KQ#64v(2R?OIy&`*RsXdY?>oxa+rK zB3m1O53+oqz+}w`d;AE$fcJooXE-K=wWB=B2c5AKN(fFtZsMjR!9MO$nxgV%Yih;K z-qa~yEUO}8zRbbHyez?w@kOJ--a`-C;Iq_nM?>cu?C_ZysWuQ>uExjoXL%s`jtwFHSUC#|RtzDL%&-_037@Ws=%^L$fZO ztJJ!YZ>2gy!Cv6%7pJ(iGhmT(T033@>ndGhcpo+M1x0oKQrY#A61Jr)%mrCq*DpN>Kfw|0Q1K*XaC{v#@L;JMUK+8?#QL@x2a;Ant&#eYUmOew0AR~}L zinnFP4t)Mjy>eiK!V`^0wqCARYBK8QDn4s~Y}&wgJf`X)er&tPq?l;^ z?sCNH^}`lL3pe$}g1YwUjO4`N?vP!Lac&f`%Fi3Su(1x*OYX6)m$!YLyZ;OB+Z1o+ zcNUmxtdg%78^;=(s%z&lNVcwhm>dLSQ0W2e-~Rf7$qMsX+^wr3OH2N&*~-iAD=b=! zXb|`lESD|MTw0Q&^WLsgrpQ+68sF3rY>VB>N;5I>Llw4{p7u=UcD~rc%Wd4B!ndS8 z?QuNqaXyW$;7J3E8LK0L{-y)Gq;@c$dB9TYpJ0$W+e3!%=5(OmYl9)&0ZW8y9m`|dRL=lN%5*`xw zlDLn={Up9eVgZSTBo>iaOrnIu5)w;El#*CRVmXO266GXTka&Q^N)oF`JV;_Si3$>x zB)(5#4T&F+SWDs|5>+IANaA4<>qtC8;zuNYOyW@z>q%@Nv5~}MBz{7onnVo=F9{!s zS`vN|kCWI$;-@73iNt0SPmri1v4uoEiLE4_BoQF-GZGCXwvl*>L?a1KVmk?yL=%Y} zB!VQKCJ`d>a}v*xc$UO-Bz{5Sc@qCj;sp{flK3Twe?E;^#499r zlX#WH|03}l62B#}hs5tlyhh@65^s?B-z457@p}?)k=RROABjJZ*iYh*B>t7ezmaGr z@ivJT5(h~9JBj~8;vk84NVJk@BhgNRNc@S!Argm4gh?DB(Lv%Ui3o{5lMp1{CGj65 zI!Sbq=qAxa;y+3Jg~WR#-X{?y(MzI_L_dkYlK6ncF%ri~oFMTx5+_NVB5|6;-$|Sy z@ga#Ai8zU~Bs3D|NPI-%Jc*A<43PMQ#03(ABt9ka8Hphh7fB40xI|)v#AOnrBt9pR zAfc1^W{vsfOY}0Dv#vZ{@h*XLis8r(?qT&=@3UdvR_}bDS%STR%}9@?8Es+Pa|%P2 z^*pXueMs|UnMH-nJPhacljK{e#Rx(0WES|+3d9%gvw#I(XbVQwjF7VH8AT$CA&qHeY{ z=-yWhCNBZ2Rt&3)M)(LMf*owKCbR5oBz^Iyl*3duoc+EQ(K28kgUzYZS`IQPkQ7w= zK(avB*h^NKaX=dzbaafb)00R4E@$j1D`Ib8i<9}r4|&Eb-m0+2xebP(dYs_(p~=W6 zU^0AJit(u8fVE6&vIGme0Ac^(@xuuH7UUE=JZXGE3TT79U?MY)u|z|54SS@9?7Uo& zy1-BtuN_qLnD#7gOwpQT3X$T_I$&G84P#HWazfCVDC;t%IIcRZA&CgvC$N=C%#dXa z|bt8Z_b>vy8jldnaz?5GsniNvk#+?;O;hh!3gqgH!8Jr)m)d- zFyu|wrny_Mm~#Y6Wn)?=&%IGmb2HKIn^9kvVBY0?7+P@2P5z){ru`udCX8vlNv2RW z*yUZSp2P=vJBVW=s0+1YX>KzJ@|`y-{*)xG*P{KF<6Rq&beD}RY$uqS;;VJu8LyW1 zkUXnn3xR_<{!=#RjP4&Eo6@kH(wec!4CmWsE4AxXXO_~?;oSf%KkDwsrXS!yLFQ_> z1Tb03FYqJI*lxSb5PRW6_@a?uuUlFm_9M<5ixOFqmH+#P>PFRt7Hx01co?d9!QJZa zKz2U1Z^9r!LB%;s(L$PA9?j=FFi+kFuCwu45IYKcgl$*qFv&CngZ%*syk?y6cvSm? zmSu<@D42yb$<8xoDe-&tLlvXE+!E|__sb%IM~Qz+5BBYzt;8SGuPDQ2_!Bs@V4vZs z&GAO&*2f&nlX9O0Hd~nYdiaow(HD7_x-1nZ=duxa5%7d$+$6WMcfyr@_zg#BTo^C# z0}gMdaeQ#72t^;Tw!XD|BJ<=;nGPuSGNb#h14EF1pzf$;cQZJEru)i-jW6I?a z568U_**NgT=IfBa(EAb=;!zxSv4N{2Ja5wm z<3)A^G3ngk7hPUuRYdhjfByqJZ1_U35B}AK7Q62Zp3vI-3QEyRr1@3j=5Cc0yDKJZ z!BS%aokj>OX^PH3w8bu6$B$qu=N+l8goirL+i+|RT(Z@e-?p*5Hvjzyj_PV#URUiB zo(LRHQ|&-5#lkmRw0&1*B7=Ds zWbHI&(FVV0j{8~QyfS1lc|TLrIimQ<1Rpf@4B1V-4dy94J%6>$XEsTd8a3mac z2{{C$9#JjkYkA#h-g~||W~)pytoh}#!xo!bJBoLGacaKbR^!O`IBLz@;{Yn(lOi8e z_z^=2!x&LvU_4#w>sYlp{u7q(SNy-mH1YZZx~P>-9-W6_jY4LsyBl%+V(l<*&x_W~ zf?LRrcAdNpx>>l znFu)j-U%3C9QNFC$^K*67L}bIl*!0F=!?B}w}IVJn5Iq-9L@+AqQ)IAydW<_@-mFz zUO37N69FxQ7Y=aDjSqzF(uu4hj?!5LItGg9RpflF2=XF-!h5}13pAu-#%%4(y#^9Tu zk*?I(Ra`+Y8&R0~GtR>3l-;g%m5vok#$qbURC>!%?VR9FYH?!C{Ez>19pbVZmvs&t-7A1K*DX}7DNPHM=3yuV~BlX z4q-m=C3@aq?O1@vy8X+T3iAePeyzn(#+hDYj^A>X3$oJzJ{bG_bL`i{N!C_Kr@a{e zmE}t*w2g<8f)+qCFwGtoJdOxycMrjgp^o!`b|o;P)R9Dtxac&_1!} zEW)t4g{AF9aekyHW@_I$!qRFbCK%>Dvix~ne?$M~SNB?aPGTP|n=H}1E|G-;Ld6L0 z3TPHnCtOKh)O%wVf&uT5(L}8n%|aoL_rSFn4~3I?n_lQtEj*Ha1i|Gt3ks+9{6e{5 zk)%!so8WP2f{4apk33Z+YiI};a7Y&rP>dA{j7@Yan{z@YJkw!=Fd*};boi^UP6)!^ zJ0|?HVAS0o_SiDO8mVsBGg&^R%gfX>T&ATlUa9a(%U%nwbYPy9seFn$g;%Bp+RyOv z3|^k1&VYo5U{XjK#oVphFub`8b@1Y}zd%M0_fSLk76p0D5qxq&jgIjFBjllSc2L)W zdG}N86gEm1%>0(EBdLmaHa>mEnnyy$I_4uK^In6rs~@?L{J_$d%(=#6JZJ2;CRETO z!Cs_2xMSTM@^VoMfn2$l8)XWN@>W-oIdaoTj>&jYO zN&j~}s_=|Qm6egC)Mof7BwqLeDLW@m2>BU}tomNw1B0Q7JsKRQ`2b5B)0q5XkOuXm zmfU-b4c`~Y_!J;_!u74lVv}^c@R=Z^&KMl?nKmr*0plQJW!hPIEfAXHQF#`JL(Kh+ zJV+Ge9rioabkl{rcK^zxzZq1$vL*FPE%TCH{FblbXOFRxXA+-l>_r|xye}Z6q$UwK zIh@z-jz7e{#PCj|iT^i4O-*((hI$h{UP}sB`wH-~)_&t~(keOR&&TPd1|KX^Hy9EJI&)qbEwvpbCe;FqB1o)bAkU{`-~Vsh5@$InudcFm)YZd|*@Tjl!UBah;Pn77)u*6XXTs=+5K{B{~ce{n&T=KuX? z`Ug^leI2JT_{p#Q%nbh|^Oc{%aFYN3zprZms!U@w`0pMGU-^wQna0~JR;yJp>rVSD wo5Q51L-SJC=6}%lS9;=Q9{%^n#7wT8SO$~p@A$7H(_P!~KRYJZJ!y>n7rT?@vH$=8 literal 0 HcmV?d00001 diff --git a/16/tweak16/XINTRO/LIB.SMP b/16/tweak16/XINTRO/LIB.SMP new file mode 100755 index 0000000000000000000000000000000000000000..4923a4655e79d14a50042454e118b5a0650700c6 GIT binary patch literal 599 zcmWG{3~~1NRR}1`Ps_|nEmBBHEJ;)VF%`m$^o)49q!?@&7#LE3c;Pi50RlXX5E@8= zSQQ8^TpY##Nr?b4h&F}NKng1`Wng0vI3^zqk#x3-iHb3aFo`!biwOyLb@T?(5uSb_ zLH;p0nMr!76{%o#A`GlZhDADqI2DYHKno890htF50Hq_HM@d?QK#n*lgabH0Aq)z4 P4hD9HxA&Nslz?mif81~y literal 0 HcmV?d00001 diff --git a/16/tweak16/XINTRO/M13ORG.ASC b/16/tweak16/XINTRO/M13ORG.ASC new file mode 100755 index 00000000..906ec42c --- /dev/null +++ b/16/tweak16/XINTRO/M13ORG.ASC @@ -0,0 +1,55 @@ +Figure 1: Memory organization in mode 13h (ASCII version) + by Robert Schmidt + (C) 1993 Ztiff Zox Softwear + +a. Imagine that the top of the screen looks like this (pixel values are + represented by color digits 0-9 for simplicity - actual colors may + range from 0 to 255) - a screen width of 320 pixels is assumed: + + address: 0 10 310 319 + ---------------------------------------- + |0123456789012345 ..... 0123456789| + | | + | | + | + +b. In VGA memory, the screen is represented as follows (question marks + represent unused bytes): + + Plane 0: + + address: 0 10 310 319 + ---------------------------------------- + |0???4???8???2??? ..... ??2???6???| + | | + | | + + Plane 1: + + address: 0 10 310 319 + ---------------------------------------- + |?1???5???9???3?? ..... ???3???7??| + | | + | | + + Plane 2: + + address: 0 10 310 319 + ---------------------------------------- + |??2???6???0???4? ..... 0???4???8?| + | | + | | + + Plane 3: + + address: 0 10 310 319 + ---------------------------------------- + |???3???7???1???5 ..... ?1???5???9| + | | + | | + + I.e. a plane is selected automatically by the two least significant + bits of the address of the byte being read from or written two. + This renders 3/4 of the video memory unavailable and useless, but + all visible pixels are easily accessed, as each address in the video + segment provides access to one and ONLY ONE pixel. diff --git a/16/tweak16/XINTRO/M13ORG.GIF b/16/tweak16/XINTRO/M13ORG.GIF new file mode 100755 index 0000000000000000000000000000000000000000..1fb4fc424630cfa1a380c5bd2ecb6cecfbba7551 GIT binary patch literal 8860 zcmV;NB4gc0Nk%v~VSobQ0rLO=000000IC4000640ssI400II500II60RaI40RsU80 zRaO80|5a80RsaA0RsaA0EC2ui0DuDE0RRO5@X1N5y*TU5yZ>M)j$~<`XsWJk>%MR- z&vb3yc&_h!@BhG{a7Zi~kI1BQ$!t2G(5Q4uty-_xtai)odcWYXcuX#v&maI`qDHqv zZ}xf>|ETYh`&>`a&slY8e|~asgM4|2iFg@=a*Pj-7?OT}k&uBunI@YSl4wM{yi87rVqlK5H7n!KAuBxkXt$nx^o4Z!8vxlUim5aoym%3|=wHk_T&WM!Jsnpom zkB7p;$d=x*;?KagsCCul;=b4At+cqJ$*||+((}sIjo=>7%f!>BZQI5#9JFi2s7Q-N z?pQ-`{=(Ix$FHF>Tf8pji`Q%4#)FvuI1U8K$D%!rlOQrf>8aqWkpFU7f?2YeKy<&_ zRV>KCy{-*8-PFb~?YbuY z4Vm%cxbf=!&2ywa;jaI23z-)#b>)+46zyJRL1}NbFfCLt3;DHDxsNjMOHt67k5Jo5=5=xyW!hCb7;8+(J zz82ee=^Zy;hZB|v3Qj%pF)QXDD z2pw@6aVlJ(op~3go^A&A33fXk_RW!vekNy3H$1wgI@`%O9*)2)hH6Sdh9@3xrHZ&H ztp2d47NR4C%BO6!iR$71Vw$$P8dWMvYpsAkIa_C*Il^ddv)*1SZh_X#B}{Oq8T;+4 z>L!Gtlp}0NLa|WJYuUIq)Pzx&I$0X-o2e!0u9gC)AaA^!^{FAj_!>-a!I|D^+Px4T z81TO*z;#@=Otmv)vOpU7v90YAq?5vuUCOCpzM=f2$JxQ$aclpzEZvl9_R8X@)#hjO zvMmI;rO<#yqr9i*THQ72{~IBCc@{?{OCSVo;Z1 z(Qy`k%)uO8FbFmnay=Alf}{f34@Snyj&7U@=3wTVD6#E1yMoe7&Ne$sl1^tQBa4sx z7{@_6@vY5^6WgkgY#!i8hN%AYlGNy(wn)b9J1TBvi zc2?E?WreVftpye9*=l+lND&feA+D@Ct*u?f`n%EuGejqd;|l3w>h z_nqr~0e$V@iShdP0Oh6XdC%$GW`ftg-ui`nuWMjZy%AoX@Ghaw6yE=eH^4!yEk>h5 z;C=Gs9SJQM02XXr4|6!b=L9hyLmV3b{I3GwlK=oGutE&~RKrkMQiN?fQ55gE#|ZYt zZ!1t@ng;pEheYyygJ$F;Pa?K54qud~TtV>JxTiSgD#;?%I4*CwC-RlRZ(*0qQt4w9@McK-nwHLH1#$tqN_qn9~oZars;{*5E!LtbS62nL^qZGQ(JN+^Lk`LXF zAHG@2Go~?l<6MGQjg-+k5UqX(oU$`_y2;1{vvns>UR2dfwn1afGgf1j zzjx&edGc2FOx4Rc_D?eNwXXmL+hAPl=?#LquuJx_j!(TLL67;^%LcNOTkYcqOPkus z?gOmdJZo;xmeTeD>u~4F*33zaxR@3K~?{~)MJ!0Py`PmZ=`Nl;q zVFD-0#THI(t?TN|kZX!xgeWIl=}gzEQ7xufCaa>0EzkN+8`(RL1c^cauH>Nam%Tp+ zM9`U?a+QPI&MhBp$_zD_m|dsKR3}d~Z^dp-aGJZ4r1`VH`=X8y9k^sKQ+8)wT(PSL z554F|Px{h-jRtkU;?Bs$>BhQs?kU1*Xls?M+)PPhU=#M_ zagh2Y^xpMIpXv}KM=0X+EOhEd)9_o*NLYuJ~4ib6IO$7JTUf39+V zcxG^Xlzyk@FvG_#!@_>8gLpSpffND~duMVir+QG;gG3N<>9$DKhGqh0g3ZTTEQo=& zr(a1pfb9`=&n1Kj=u<`LGr%`8#KL{ibUrj#Q#QC%SNM9@SB1?LhQ1enHOPEsI8tcn zg=)Bl%QuD@_J(knO2T(zbXbR)(1tVhg-D@?V5oT|XoY~thH{99Mp%e@c!*e*hl-eK zd?-_XXo!z!hb1?MiCBp)6^Si1i9e``mbhYrScae&M4ZU~Ql1!xrKo>`NQTC?imZrw z%=L<}xQUENcaB(#qS%U!zjk3s$iN|}DA%Vw~fvEP|KC`ZUra}5Xw>L`xO*p5gw zNygNIE_ZD6$Zx!eh_Rwe;lyYB)sJ_0i2#`|dSy&fhaQ}RjaR6RotTUU>2>tzhM8EA z8WN2s1(C6+ktFz!jhK-jDUIydiwbFaD!Gy@*^({^dK)H^xJZson1o++lQ;=Nj(3FA zXL+p9KR_9j`m>X)re!kOjKGM3xuukJk&{k|lO2fvcT6c2frm$YB$QYgluSjgerMd?^4&_g>1T zmw(A~tp%5cX#j%>ZFGr{BRO{vR&9^j2YqRlBNr`|Sz!2vnO7-66u?6f)S26JnJ2fH zyNHrUsc-ufZ~Ii174VezwvVsbVXAp;K_iqBU_BFnoB4B_aXFibW|Uspm=~FtL-=z` zGMN(Kl+l)SMMs>?xpY%lX}0;9yIGx~shH_#fx&5)7de3==$(7nm&uuvzUB^Q#*gPl zn}7h6xhX|b#GAcoYU-&35{ZgQnS%4VkG{bFmlNQc1o@ljh;4NSo$&;nkuaU^xj(vj zoimr6H`txq$b0AMpdv_?teHemIidMk8Wakin*kn0=?e(DpbA=|*HfNe2Ap+?loHBp z=xLm;aG`v;oFho1Kxd;inrsC+3ls#J`@@?)dZO65p@F!aEE<2Eux}~0nonr~%ITW| zDlkg=T~oTAhxwMVNp>Fjom6O=+ZmZj2c~&2nPn-OnvUR5*b{r;` zmFkv+s+E-L7jasj!kCnVXO*EkrjVNdp;Ji@RVhrPDyN)~sY1Dx5`n1x=%wyhldM&$ zP-%I(nuM6@szd3MImVG9D6RHM zt^7v^{wJ?0xT~`Pg9%4V?9r*h8dAgx7D_mva<+l}mxE{;dr$~oi=?pp`laK~(Y9G5W_qc%qON_H~t>|$&w4kzGs;J!hYwfYCwmP$w z_OK_Svl}^zr}?avX0*^sr!A}hv?ghHNsEyS3$*|$wMN>l8*8;M`k+&bj2+9hOB=0# zm8@oawrD%D@+h_%#k6d@wr@MODjK&$d0UWkySGE-w|uK}fE%@g+o60($ zr;ED!TDYsrx|J)ruls~>l2&nAwRAhXa(260Lp!8My1MIu*$PfpXR=GkYt&>jHj5f& z!+=B^2E031!OL<62#>haG{jpru&ST@^t+%tz0tRI_Gf%2w^zBbOkrbd54di$2)u49 zpD?0U-8fDaT1!-lqL(!PI#3l5)cCjVi?;+wd*ud7vxiT^l}|VmT{DO*&wHNcs%m$O zy5Jj-YU_K^>%ah&PYoKl-}}B9_KvZXV1snQb~V968&^(9Z10l2L#u;3XbyX&k0cAZ zn`^=?d<819!hl9yn+mQ`SAQ-{!>a4S#~V<()_yOeg$h@^BU4Pb=6)6G#976|@8^Kc zJ4YnkRyK^mX1?EQGHJWX zoZQKr{8@Wku@I8~$+gN_9(2m6d_WaU$^}e*W%SChY(kY6v>GS{YK)1i3IM6R%c#7) zyLGC12h8IT%ft-JZI{cb%Bp{;$R{i%EO^5{JZH3dd$V_;8QhYpu-2xUw_%p-lj`I)4t zY0IH3$_GgQPse0v3`kcsofG-!(wqSgi#Mc`kj)dY(^`Gf22G*)90@}GM6q1dfJ&re z&AYb@vE&xWF+;t#chzQ`eAU~%J`J~@1`RoVM7)f@nCqb$ItgVx0mY2g=_$naTe?Mx zwF2nIlq_`<4Z>t1FBLr}Fc&b9-L@ON)m-h@yPR%;jj#VX3n485L`}mb9i4_&+JLc zZ&m95-Hz>z4Qj4`+#hfH3mN^~AC28&`e4513n4AeXkFm{jotYD;EUYDQtUENEIXnh zGoMt!`Hh#p5a8*}-FI5h{4C=BoZ#|3tDZaJ1D)0>o!kK&Y=%6>`CCskO|b{fl<45$ ze;wYFiq7Y3&NE@+CvMG-8g@V~;-8z}H(bry7sn0V$LOnj4{V6JtmC1b%)U&O!h8xs ze%6C$O@g=OR=L!+c&jpfQ(H?HK(9Nw7B zh5h7Dp+kGt3I?8h=!l-^#k%JZE+JFCh_I{FEw06hOy-c7X)ncjNiux^LOU8R%r~3= z=Mr14HdyF@E`x}{)|L)+Fw4%MZhhld%Q8FbNZ9K1c{N|Gu5!%ivHjTIq$Dt$;nlI( z`AU*M;p!lp>;p^73wW^)hcv1_=}`ADzwRD=bilx|+qCTwbB@lNPOkuK?=0r_Bb>> z$yv;-pCRu2?(j_g!nXc_{{HNi$?Nn9u;!SBqh#TdJlB50%|*LfwJx&E9_}K0X;+8D zq0aFihVig%AFK@P|GVm8OIQoPRnb21l+L<4uiUPe^HTNm>R!T?F71cgSVBMli$GuW zJuks9@8XEH^hn$Ejs90u@3b+$^+xaWQQzG-fAl=R%*!qIR-f+83@KZb^<-c3NH6gC z{_rRtA#BgHS1Dms>>m>eZxcrYVyllSz*HEp!C0kDl zpZdh@zshg(5b)%r)m}V7<`?`=>p~9Pw6l}U^&}rNRc9JzTZ`0PzTEDbCpaV)jYnis zxnwq#GG{a=rBa|(Y*veTp->>4tp)UeyT1*H_N3WEnEvrQc}kYG3Nnkqp0H(M?>{c_a^`UBr}TAp z>+HODxp=;taZloA^KfYTbMAX@L1GLfSkT}>gb5WcWZ2N*Lx>UoB~GOHupJC+yykfU z1mqvbkLU)CIHs@Lw;B}>G6^<^pDX|bWX_~n)8ps5AZRBke=-vs9dG->6N!`-k?GMZY+9Rnc}NC`Vi9YbuG!U<-zKU zTTnt^ba>uTwmmyJV8TCh*UlX_c;sBZr*Hn4=rw6hJ<2ctX+t0SVf2~WcjlBoIqRe{ z=n>_NGf)%+4dg?(3C2pWKnR<7khAvGi?A2g-owSHtNz)3Ab)^LvBed! zQ;ZcXu>{PH&mbex2y`!+%Gz8hJ}*wfp~P2c8}Y=gNW>F4g<^b@ zNg9EBk;3!>9Slq`!xFSdLhZZl(F#orB*#ge6H>bM_OZtp|JVc2Nu@vmsJ^G-?6b~4 zEo^jE3|BN0NFQSo?1C`WY*j&w$b5CzTVutw*Gq^0#B`OHG~%?fOhb&6F-FNl&jaxi z#mQMueO%;OWq<9?JWJUe_S;0<+-*?^11&SRG&P9!0UXig(b`a|l{eRHu?5y!e8IJs z$yTV7(9Z1K{B>E=#=P}1&%_g~U^MTQX5a%MF7Uayg4K6WcOij`#xew6t}o6w&bF|& z)K$1$jIpJdWW6vHnJ87y4ehIQ|1xHmXQXz#*=Gh z^h#H$Q2NZNp{6&(d@l|WRI4MoGfJ>Ug6g_*q7s)#fYnNyD_NVK_GOY*hPyVjgUnj% zo;U3}Ej`0N^1pYRob7DF3pf05#1l{4?&$FU{#tB~>4cnA$?MHnaCjZpeDlm{srfk0 z`7;}6pOAqisk}@ldu^dfbvSg`H~)N#*`28U;HA*4^UgFQ@)?=uOFKY2hXbGO`R$&3 zn!yjBS=;F+#6{v;{+BNI?QI+S3s~xYCn^D*Yfa6Qo$Eqyqz4XTIT8#TBM?Nif8`G? zXzO3^!lfVfP0(MR%bxwfr8oF};c*?>Q~J(Rzz{ACP8%Fx4J`;lk)`lsuY(T*9rrg! z?Jy}y!AJy&7(Ybp&V{HNUI3AYJ`NK9uw%|R$`h3bIEih@gx?yM&*~+oBxOuWL%ClW z@g_yvZIO#d^w~J}13xHPj*MocBNrK0lsan6i51IZA18xG38~SK;REC#4OzbL-R*gE z+anze>+iAt6jQ<`?srLaP0 zI#K?hm!h-cHuGop@mfCKv)P{%S@WP1{YgSgLD0FBEk8Y5;hvO9QIJ;Z zpYD9+Hd~jcV|i4fA!X_E66s2!W$9A|qSOY8FN2swrB$hlDX$u=r-U3Ko8%JKul~`Zq(JKc z5lEFDtZsD2!r3V=m^^=`m7;AeC{M51LSuB)a?LEAMmdCuvW`;~_w-=kcB0j4fbldV z_3ICXsZ!A$uZpt7nBMX_L;TS&UD6}!W1T~stEO|T`Xa27o+i+t7B-t{Y@c1T zmUZ30s}LER*&OZmKBi>6c>U?NP`b48-Uf##%5b566UsTk5^0QFD=QaDHAy5^ zcqRtkbdk&3jUqQq#v7UOs6wd;v&@v54VZ2J>!;XaSETK%Y#-B?Poz4x!9B*Pl3iNl zSL*D=9*tv+!P|-@@3q8^aPn3m{ACXNR~uPAXqU5S!DY4=%s+}Fm&sh_Eu%ShYu@ZL z+w0~x_tVTIOk$e<+04d41XadumUEuvxo1{g)X+>_^g0o}(?T~o(vlA6qag|9zq0L` zly-ESS24}fu9VZ#w6rEgZCT3Ehm;+B>8MHV>0D-da&|UaT}th0c)Ue%Z94Jx;2IEC zw;I>DEcLCU`)4FdRA z$!&9U65Q#APPExQ$aTNFe(sjHJ?kw=bl)4^`aWd7`EBoi`_bP4FE_yfPFaI5GU0U` z_`;Xz@PZ>8;+%{3#Gxv2i~lg=3a9tRW9soaj~nD7A9=^2Tk>I59OX}5@XF8Va*dlD z=C+>s$7NpsbByDhsjBrqL<$FPlNsHPZ#^7%U;i~pS{^?=X%rGKF7Cvo$7I4JKg0@WV`n{?<^Mf z-r??dz0V!+d>nk>@m_dhBL44ESA4D;Uw6Sjo}H41cH}8P&&wy?@|mYC=Lvs!&lffH z`%L@jlWBU3Kio-)}ef!B;Txcj0^E zFDv=6AO7+a?fi!I9r}}VMCl)nL-xdMd01BAIJd?w{qeC*YL%YMn zCDX&W<3qjjL$(9NuM)(wBSfh(M6pA}rBcMMV??KFL!^5{NZdK>o5bs@L`wuc0n9}I zO*BAGls^A+M646VmLkQeGsTcXMW<6mE&Igsdq7r9x>$rWR~$MMtVLVIL|oLmP~1hb zYrk0}x?t2ZU*yI88^)hQ#zQMc`inqjEV^EN#{RQFWz;@Mtj7DhMroWz4BW;Glt64G zKyCEK_iMv&M8I(*M=onXc5Fv?d`Ebk2z8uCdaOr#yhnV@M}6E!e(Xno{6~NcNP!$k zf-FdbJV=C0Na*u1HBq)4S}b+AlHHP_kWolOn}mz&gkE5n_IRY)Imd+L$ca(D!9g*t z+LqBV3zOM)j$~<`XsWJk>%MR- z&vb3yc&_h!@BhG{a7Zi~kI1BQ$!t2G(5Q4uty-_xtai)odcWYXcuX#v&maI`qDHqv zZ}xf>ztuH&_#C6|%lmr|fGB=Fc_)V?afua-8H;m{I+A)FfPr9sg=iv_Q=TcHZ-<~B zr7x!(sT-P}tB`V;l(1r#qnosY5^aUIthj5vx|e^s#Dc@ekjt)-x{uDg&&a~Sz|x!4 zfyb)O*QUv|+OgRd#&z7&+*luD+t1VN$c>ob(#7Pr!u;~`U6|!<46l2>w6)qt z4Ie{$_Zr5ENFiaui4G|;v>5HzMu8LmIX(=TPh>=s1O@tIcJZUjlg)^s?AX#HL{Y&I z(%dE7vgSab{Z>VR6%V1#mlZqSlnPZDPmBS3&g^*juvnQi^cN2E3bBZKs`M@fp)=({0}{On>$Zn-v=4vS1^(HA#}N zTgHCbW{%65Xxp=Bsd}y)Iqlb{rA32=_!wzo!ZXxV!%DIaxv5xjx z`*!hvsp%;P{*55!sK{B0jV?7^J;Bw`l{=bU_BXm8wcGU;yBK-C#pOYl?ih1<^IDYy zluUf}J5Da{E4q%qzyJT>0Vv@AfCLt3;DHDxsNjMOHt67k5Jo8BgcMe2;e{AxsNsej zcIe@UAcm+yQ?~8*7b@-C^@)n@3HO(Zfmy<$h%_Ro9T2@0X4Vxs-jSn=_RU!1kQ9n1 zj(%q$*_e6{F+!p`+ttM$T;#0>pJCl$DVLQ2Lb;xEOA;xjfH$U=hH6t;=7^7-wdi6t zxS_dQZt+>x9!KAS_v4s+a#1F8&CHjknZdZ0Vt7$<`5BwxP^TlElL40KX7cS;7=L|c zO2(h6fobVloGBUUbC)f8=xX$xmg;b3evlTMt}2$GJI5LM(|Pmk*&(fh+Q2EIEN)rq zTuq`!nW(fP_vMw4j^phAFUMl4n{`s^DJ_8KsESpLpK5w1W!{D>Zg@bFlAf@ijXN5+ z>b5&3mFYoO7ipC0`XQXP3TehEo}P)Szj%2$LW%B9vd~Ct;(BVcnu-G?w))!3+K&3H z`Ya*(7Ca(z55FmEO9Xejp~DpCS7?<>Qpse>f-1F~u(gSEJa`U*r`8&m?FFNb zM!H|fW;2m747SznvFprM2RqHf=FKFa{nCv2 zv}@OT>3KdsYj?*5o;*kZ$R{7b0|GSfyZ{djApP_MJV3zp*c0$T0o-?Azyk(^FTMc} z9AN(W2Po8r^2sy*eDl#$FTM5IUynuo_Iuww_~VCPKKkYpgl|@ty0cwtLB{g~`;h0p z_r*_s^sC?Y^!L5~`44~r4BP`2xV-nlPk!^mpZ2aG!U^h+fBpL(00mgU7Sbqz>sw$0 zpZ7rOMKF6N^d1Vwr$Y3pZw(xrq4R1uy&Gche)!Ab{wzp745p8OE{tM>UHzSV0T__V9c^+@KXbNW>5(k%UR);ts|4#SBXEjU1w)7}+Pp4}#E$`J><(FNnb~ z2Jwnz)Z!VfuthyGv5ilJqaraR$3K!Wi+I$Y8V~72KaSCXkSrk@B{)ehRuYPf4CQ|s zc}W^(GL44xWFIx?NKD>QlY~U&2`RZsQQA^yxAXxhbIHqE^l}Hg{G~9r5X@o1!I;SG zPcf5e31&L849k4xBcw^qFGRDNjliZhvvAFAve290TuL}YG0t)}p_|)8r#aWj0(D~3 zo$QRK3E)Xhddl;jX~1Vb^~ujk^s|}&3@8ok`AmWeG@u4$Wp$xqzM29)i zh_bW)qQAtbMa!vCUUt+8RVPYLy<|T@X=egRCS?Z&&zbQ(kHxBls8oZ zwaAuIdDT=3IbCE>kq|P-5UpZAwdqfXdIW+^trAI9YE7AHgrWvUrrc3lRBJ$0DRyYuLsT7O{$r?DQDx*vg(yq>|0-04QtO$~ttdEd*`kG%H!ocDAvQC2e3$ zd)mULR<(<5t!HKMTG$F!wvPQQUlC~A)#4Vly#*|5e~Z4_23LB+C9e4}d)(V9*NM9S zHR}|c>)hu8(74AGn0e)bs9dx!YUy;+DO(b+2r}i(dJ* zHo7YnEshdffzpomy66?}e=i$gDOLW?BNbS*1-dVjK~6nh#8eaVp?s1 zet!U87f-meHU_R@NjyIh%g?(=zpS>3|_M66r=dus4S|&gre}pr?FlJj>a{h#a(? zMcm(4hxvoS7d(XdXpuFZkyvJOPi8HVHohimLdo0+RLB zX%p#NR;5a_2A?V;RyDg-E4N)I5>8zTbGzGcj$eyy{b)(&y0|%S^10Ffed{svdE=~8 zxW~QhWXke+#>YlBzLkCQFnuf2uL1bJuio$G_|9hs2k3bVY~Rz`nY3l^?AbM&cFWQ? zyltOtvL8HMvNM>{3XXej^M3cY*SzmICh3rM$#({?J+pdOa)1+GXD-(l@N@SQ2k5A1i#Lw@RAkR0XTn%B~s{`9C%z3Nxr6wni)chH*M#fVchoit5&2LvWc z*(%P+3qdmzgZbQ&_B7x}Zuh*Gs_TCbI&Fom>+!PGldj6t!5e~eT2&gUW0mO~N3-=+ zWm@dFZfM^}uKBF$>C2^$^3WZBioe^KJKLQ7?jseXnG1^TO3wWM&S7af33D_z1ACsM zd+=8~*VJarHctuoZx~~LI6`p2B7v+BcpGJXJb)gv$ACf>WDwYL3utMgg*G5)I_0-~ z7l?e&FgjGXF&y`O;1>#@g*6%&eC%d^7KMQZxPqqxFfvG6>O_BQ1#Ky(EjNgQIjDjw zsC^$eelXaCu_Av8NCzr`byYYE7MO$wn0zILgAt{J{=|h{h=gCLgkqQk{HKL|b%v^w zg=M&fY)DjY$WUOI19f;-Y50a~7>8&$hX-|se#nPJ7KjLChJrW*c}Rzbc!=*uhKdM> zjQD$m_)mc7g^_rDmiUK@c!`+kh?)qAoTy8a*iV({iJ^%91Bv*Fdw7b2n27>aiUY-p zI5LV2wTZGwi-fRS3IdB!m5Q%ui??WsZf0Hx6pWo1i^RB##+ZS)h))w0Qa}iWyqHwJ zScs^Ye?YiT%V>wqC{cD8Q?)l!MW_nf7>2?~iQkwf)Rq#*RF0_Fjq>!2C}&i-LQ@Fm zj_{}mx;RiD<27rhkND_{!$@~_Fptz{f>OdS0V$Alu#Yyfkmooe4tXHcIFYDek;Ma% z$QY5e2#OjhWchee>BxE{S&}Ask|Zk}&B(0Kh~vS(6q705O@9FgcSp z*^@MhlR6oc&%={GS(M@6L8xK3nOQ;{%s*={$2um*InycPW#4`I9TT zk!od!ed(8fd6R`Hmxqa%iHVns**|>Qm`nMXbs3m5P?7IKn36e}l)0Ci$(fyLmwlO+ zdKsCGNt$$tmJCUXnhBE?K$Sj80Y)jBWYj>fX_z)C0V$-LOhlVQWSbKZlX+PIY$Th2 z$#I{Fnr^9@Ea{A`sgn{Al*-AQP3fDz=|0g3KXo*n)JZ-Q@RKnaoX~@vb>x^m*`5Bg zM|(MzwJDz3=|I`pJVZ&H#aW!_S((0(mgcnomO&Yx!kL@ud6oT1p4z#cv57*ud7qvc zo&-9cZ3&=W6riRFNaQ&~6fl&B#6REZo#}a;$|snD_nfZjpZ{5t^y!oX`koi6nCGdX zE()FudY$EIo;10k_Suyucv44b4mla0KFU1)IhWMQn?x$1mPuO}i3-p;qc4e?MLL@) zI-b!vPo(j62`MH`MX$M+5 zl}`GiD7vHt`kpKbp}PsABdVudDxWpFM{SCqJIV&_#-lL`s20$r_1U3o+NR72qA4hq z47#Fa3800_n3r0iT*{s3DXE=WpiEl-r94ER7T}>ux~L8cpBVb3k!q(md88bdr1_DY zow=ZrshnnMon*#k;ynv>dzJkPlJ9z%DH*X6JFyfyu?;(rgZYjhS*vf_oZhIh z8|$tg`mGO(q~q644G4u=Vlq#tvIV&|PFORC+J#_#pemt}Pe?lvfMBA*Fk$X|dvmMxgJ$NEIl_G(%EO-#L$r9dW(krIFA3Kqa$mw1Syc)2M$ZS zw%9R$Ejxo(ScBL>jvYID!o3)g5M|{XKPdK=O384 zx-^?(i@|)^$i6OzAMgABx#0^{wkK*5Un3I+$-)RZ92+cr9qf;FqB$X~x;G5C`+L6sHYG27F70=a(-wQ; zSS zgA|FzOl-bayKj&ZYT>wqU#E3o8-qsJ6$LDTR?C3Zz>nFh#=Z;0rSrFT;&M-AE?0{; zB@-=9Ln`tY$z@Fc$NEQYdQ6X2%*mdXE^dr{lj6x-1&$_YwY`zQA&R^uY{YD9eCy}5 zntXpeW;3$mH0nsiA-J`PD#^IazYVO#wb#R!rgejyz^zQk+cL(%EX`z*d$r8Rh`P+K zOo@GK%)mUp-b~6{WmRcIJN5Cr=RC>K0!%rzzHnbZP@IC z*oocLj9t@?{n!QI)RB$TlwH)HfY---QJ0O`ncdT$-PoZm+M}I3ll|D1ecDl7+KRo| z;0#ua{n@FV*t31vwO!Y@9oe}J*Q@d$h|PIY2D|P~F=WVAfAf0d%d?60koMz}_{D z-V9X#0f((d^DWCJpnpoLhIeru$|A=tk8`@KsyC}UpIZ!A%F%g zdoz8RKRp5Iz0~oI-AHZU_AS}){oyC1M2cPCBd$Cv4%$2Y;RbHj{(aLT-s1O7;CeJc zF@EA)G~5gx8p6!B)&j~zSj8G0$QTUDc5vQvbkyp--#lI2EG|Yip42an;@^Yikgeh} z)Z`pg+a_+}Y>mTl3($PPVo>;wP@$?WWWEo=yA{?ym~>E0vdjDG0)ed}y()0htEUykT(9_3`N5|8le z%fsvTjo4w{>55+2p>EQ5yv3c?gZi<^V0$rC95PEt*kS$W9bVS5zUb}E>!^L@xL(w{ zF5u$s;s;*tW6p8JUggJL?#V9W-TmXAydT)ivLs#DmtN(z&eIiO*WvE(zHLmHc&FRU0@bu2v%qWJmj@H{P@Xa0a^v&8N5A5zf@~%DW z&7Q-|Y#jAWd)N?-D$6LD(A*cl@|BJAC!gyouk*~F@+J@TLC^6!$hDn~%t4<2^dcDE z<^2gfPxK!z);*u_Ll5-XP1{o6@}t}I)pjy{zJZj?Gz4sqWG~PvT?JF$?K;2qurBpc zkM$9+-CJMpqTX@=OgT>@^IW~>d0oXUr}iT~_=I2hCCT+?jPE84z+Y0qm?jjPHqHtS z)B8@c?`-$Z9?u68$1xB1x}43K-0Fx=zHy%UIO~Ad?7)~z=Xwzxwmey;z}eSG(F=<)F{ ze>$b_{NnAmill+G@BNOPwdB3CUHiDfJW|`=^+XlXzVv_e{DXO`wjRj;xMU;b+CTci zFTV+`V}jf?5CFiF^Ie?v=G}iV6i2e`EU&sG^JCi+g~NA_?NrA1TYGB`a3dV@j4j+Z*KaC6o2bMN5&Oh_y!`)Q{QwTcC(xfXg9H__TG-GbLvGmr9!{)B(c;B~?Id30 z$R%S(kg&vU3|X>?NtEbkzGnoSMl7uB0(I7xa zDCOC-1k*1qm!V*R6q40OSi?ZI&&IvmQz_$ zT)*!15jGmMs$^|pF`D#>ty+Qz4@S%?$zsKg6Zg`~*K%b{Vt@TP)S0vAJh<-WVjS6Y z8&7W67M={&^6N;Lkw|@7)%NMFf_k(*4H@*=PmXm@?zG95Y}ieaKcy{vC}P!}cLRT0 zmo#qPM9W6MWgYJFYstmO^V>7!cJP$PuP;@;S$g(Y7E$;7`$-N*U8`i$%r(& zua*6VaVsIbe)(^~%$j>a?bD^42aGW^ITKKJ##p5 zHawTKF$FsV-DXfj=RveT^B~m9j7L3OG*NXX?F+{oud=kEO(~rz%sa~vI?OegFu%e59*P>+K!#SwkPExH&}UXDA4mSUHug*oPE0mhf+n$c~t(PuuM>Smm|1v==NiQafRQ@~bgleaH^6sT&ox^vZD zvdgAB-dD4odfKe3h4rk}`o{W!X9FidagUGxZk6P^&yrT`#1S8x@wCBNo9XE`MzI~a zH5^>JSJs(ony2M$9z@TuUX$VaMxdcx_avY$Nly1Q=fiCyTNW<@za6Ny$JS~o@MvCAGgBy zv27P#ZE+~pzwKo^XIRgM83};@dsyKNhY7 zHt&JK!=U|SRxmKN?|l?}%WCLnKkSA7PiaXcp5}UFDj5>#bNx%u0N*6N8X9nj*UO>y z=qAPEp>5X-DMsWv_&~tSj~$O(}w812g?sz=gX=1O7y85qJ2-2XXO?>&jtu*_g&%(eXlYte(0mrK%kTs&EP1V|f0UzAALDXS-3L zOc}YxNcN+Wo5sv5!WFzJTW@2@$6N0(FG*9TvOlf7(uLaenO`q}>P z3svfFafdzADm$L85qn)(4?XcTgb&$ky?AFsUL~!5s;z<1WKEe^@;(+hiF1g$VyA0Ct?|<> z=1V~J6Dx=-h6VJ$Y;!82a=SSAIl=h51lhDJk-JIAz)HzKgsPy?c{4Pjz!M=sNdi6h zK|!7Rzb}y=4`e})13{&VIMpJ*xv@bU9J$#NLZyN_pxZblq`|`?!eUdw4$(5@0z1H~ zy8}ePE`vKL)Hb5)LfZqwfb%>tJhd`JycH|4hm*L^8Z7cS!!Hy#B$K+Si<_)~!#G5= zdVYOiI6yH(GrU0##6A;zw3nM9M@&Bd zOLRI(oJ2(AsqMSKqwBgXWI3-BwNEs?P!vT^qr28vnOH0+c>5@QE5uaBMo#XQ_UCzP#Z)WcTX!_>pX$`TAn9E*B8M*e$7`zyv)dK{8s zsAI9Ji%P|lN;Ph*ybV+@Z?neh_&G)7yV@{E@0zJ}gvKbW#Kd?TaTL2()V&|1#|F8_ z@bgAb5kixRmw$sd)VRj2!bO542PwR;Ei}l8{IDXtNS4q@{aZ(AJiCXiM|IQ2(Goq5 zl*o*n6TzcE!t+Cj!N`+DNsrV=?IWs&Qj0bG9EB9YX8gUFyu*|f6w%nncLXl~qPz{T z;*3W`#-9YrnRG?=vq^?D3)|?xBMCu!B1t-HN(>B2FG;S_087i7HY+5!XLClb?8>Kf zn(bOYE9|%Q)5&W5!>NSGv|NLU^hMCyClqwNyX3;Z#7nP~6nVlr0}D*GJUn&;!t+AR z7E{b`l*QxgE*oMyP@AZVa7?Cz%*d=sc`P5CLPfiKOwFv1!JNXk$}*^OM?O={J$u8_ z+{m?LOV4D?vb3t|t3Z>CO$9tn)NHzOo5t4c!-R7i-jq$wJWjM!PQV;P=G?~Tw994m zkA!r?f^&t!G|lL2&RsN=59GC;EJwpc$L&-61MO}D+v8j=seHPBrRnLPTb_a;@m2|Lk}NC(kfL_ww%D&(li*F zkpEP|v-C+TP0}ER$_q3_5yicmx61SOvaWUDR3~y;~jAT$Q|CRmq#1$MKB2Uu`?` zMAcr+!C@WE3l*qrpuuBJyk`|k5`9moVLP|8(!(R{Z_*KQVmVb&+O0aTUHzGQ+p*$Lfw1?f!h%K{;T|s933$jAjbmgaDG?QiPrlH!{QeD?9b4zoZOUb+ecB448 zTiL2~ERp3{k|nsD{GvyF(*ChN{)DcWtytp9#0*8bYh^?K6`d@G{EQP-S66+;r9?Vx zrNgrlRQ&u{#pqe4E!l)^S!-?3xO73e8BT)r*&Y+yPtDPVwbhvA)K2BbBE3#!eXxxs z+xTc(f2~7eG}fzy9xgq_TU;3)0m+dxR6ZqDxn+-)qs%jf#OuRXv&6P^E!_1uTo(G8 z-15hTVbjW`)=?!~wxv^dDWu%ATb7gBc~x4@?cDavH&_f@aCt5;)%Q``-);e8El1*8!jOE!DU3hhPUO~x%_E7{pxb}d)$9e(+O#^!1zjkOzqm!+^o`R0tXsV?O(gqKnUjsh4@@-m5tyF>x-4x}b ze}vltcHqEkGe9)CG{v(3eq6H!;M3Jz0%ceio=_N$;Xj>W8qQz=-CwTMVF=^lpY-7b z1LBhuVgVy!jWpu@LgI*2;`w6YdvxMNyy0R4RVuDxE52eZZb2#DVlM7tFaBaM4r4JM zV=^vdGd^Q9PGdD*V>WJMH-2L{j$=9QOYQ z$KWy9un9m8WSBJFk);EWv8(?y%;fzU`RxyPeq&Nbj^aU<*-Wn5ku6a}R@(NJS%Jc2 zMu>t@{^L!au(MTO-gE#zEUKU2PC*@NU-4i8$clPhTD7n5WQ?PIES$pqitPg-ezv@W^evxa1Lj29%pi9(FgzlJC9*}3jhEB literal 0 HcmV?d00001 diff --git a/16/tweak16/XINTRO/RUN.BAT b/16/tweak16/XINTRO/RUN.BAT new file mode 100755 index 00000000..9c31c1f7 --- /dev/null +++ b/16/tweak16/XINTRO/RUN.BAT @@ -0,0 +1,3 @@ +wsample lib.exe +setres 80 50 +wprof lib.smp diff --git a/16/tweak16/XINTRO/XINTRO.TXT b/16/tweak16/XINTRO/XINTRO.TXT new file mode 100755 index 00000000..0ac05850 --- /dev/null +++ b/16/tweak16/XINTRO/XINTRO.TXT @@ -0,0 +1,569 @@ +Title: INTRODUCTION TO MODE X (XINTRO.TXT) + +Version: 1.8 + +Author: Robert Schmidt + +Copyright: (C) 1993 of Ztiff Zox Softwear - refer to Status below. + +Last revision: 25-Nov-93 + +Figures: 1. M13ORG - memory organization in mode 13h + 2. MXORG - memory organization in unchained modes + + The figures are available both as 640x480x16 bitmaps + (in GIF format), and as 7-bit ASCII text (ASC) files. + +C sources: 1. LIB.C v1.2 - simple graphics library for planar, + 256-color modes - optionally self-testing. + + Excerpts from the source(s) appear in this article. + Whenever there are conflicts, the external source file(s) + are correct (or, at least, newest), _not_ the excerpts + provided here. + +Status: This article, its associated figures and source listings + named above, are all donated to the public domain. + Do with it whatever you like, but give credit where + credit is due. I would prefer it if this archive was + distributed in its entirety, including the files + mentioned above. + + The standard disclaimer applies. + +Index: 0. ABSTRACT + 1. INTRODUCTION TO THE VGA AND ITS 256-COLOR MODE + 2. GETTING MORE PAGES AND PUTTING YOUR FIRST PIXEL + 3. THE ROAD FROM HERE + 4. BOOKS ON THE SUBJECT + 5. BYE - FOR NOW + + +0. ABSTRACT + +This text gives a fairly basic, yet technical, explanation to what, why +and how Mode X is. It first tries to explain the layout of the VGA +memory and the shortcomings of the standard 320x200 256-color mode, +then gives instructions on how one can progress from mode 13h to a +multipage, planar 320x200 256-color mode, and from there to the +quasi-standard 320x240 mode, known as Mode X. + +A little experience in programming the standard VGA mode 13h +(320x200 in 256 colors) is assumed. Likewise a good understanding of +hexadecimal notation and the concepts of segments and I/O ports is +assumed. Keep a VGA reference handy, which at least should have +definitions of the VGA registers at bit level. + +Throughout the article, a simple graphics library for unchained (planar) +256-color modes is developed. The library supports the 320x200 and +320x240 modes, active and visible pages, and writing and reading +individual pixels. + + +1. INTRODUCTION TO THE VGA AND ITS 256-COLOR MODE + +Since its first appearance on the motherboards of the IBM PS/2 50, 60 +and 80 models in 1987, the Video Graphics Array has been the de facto +standard piece of graphics hardware for IBM and compatible personal +computers. The abbreviation, VGA, was to most people synonymous with +acceptable resolution (640x480 pixels), and a stunning rainbow of colors +(256 from a palette of 262,144), at least compared to the rather gory +CGA and EGA cards. + +Sadly, to use 256 colors, the VGA BIOS limited the users to 320x200 +pixels, i.e. the well-known mode 13h. This mode has one good and one +bad asset. The good one is that each one of the 64,000 pixels is easily +addressable in the 64 Kb video memory segment at 0A000h. Simply calculate +the offset using this formula: + +offset = (y * 320) + x; + +Set the byte at this address (0A000h:offset) to the color you want, and +the pixel is there. Reading a pixel is just as simple: just read the +corresponding byte. This was heaven, compared to the havoc of planes and +masking registers needed in 16-color modes. Suddenly, the distance from a +graphics algorithm on paper to an implemented graphics routine in assembly +was cut down to a fraction. The results were impressively fast, too! + +The bad asset is that mode 13h is also limited to only one page, i.e. +the VGA can hold only one screenful at any one time (plus 1536 pixels, or +about four lines). Most 16-color modes let the VGA hold more than one page, +and this enables you to show one of the pages to the user, while drawing on +another page in the meantime. Page flipping is an important concept in making +flicker free animations. Nice looking and smooth scrolling is also almost +impossible in mode 13h using plain VGA hardware. + +Now, the alert reader might say: "Hold on a minute! If mode 13h enables +only one page, this means that there is memory for only one page. But I +know for a fact that all VGAs have at least 256 Kb RAM, and one 320x200 +256-color page should consume only 320*200=64000 bytes, which is less +than 64 Kb. A standard VGA should room a little more than four 320x200 +pages!" Quite correct, and to see how the BIOS puts this limitation on +mode 13h, I'll elaborate a little on the memory organization of the VGA. + +The memory is separated into four bit planes. The reason for this stems +from the EGA, where graphics modes were 16-color. Using bit planes, the +designers chose to let each pixel on screen be addressable by a single +bit in a single byte in the video segment. Assuming the palette has +not been modified from the default, each plane represent one of the EGA +primary colors: red, green, blue and intensity. When modifying the bit +representing a pixel, the Write Plane Enable register is set to the +wanted color. Reading is more complex and slower, since you can +only read from a single plane at a time, by setting the Read Plane +Select register. Now, since each address in the video segment can +access 8 pixels, and there are 64 Kb addresses, 8 * 65,536 = 524,288 +16-color pixels can be accessed. In a 320x200 16-color mode, this makes +for about 8 (524,288/(320*200)) pages, in 640x480 you get nearly 2 +(524,288/(640*480)) pages. + +In a 256-color mode, the picture changes subtly. The designers decided +to fix the number of bit planes to 4, so extending the logic above to 8 +planes and 256 colors does not work. Instead, one of their goals was to +make the 256-color mode as easily accessible as possible. Comparing the +8 pixels/address in 16-color modes to the 1-to-1 correspondence of +pixels and addresses of mode 13h, one can say that they have +succeeded, but at a certain cost. For reasons I am not aware of, the +designers came up with the following effective, but memory-wasting +scheme: + +The address space of mode 13h is divided evenly across the four bit +planes. When an 8-bit color value is written to a 16-bit address in the +VGA segment, a bit plane is automatically selected by the 2 least +significant bits of the address. Then all 8 bits of the data is written +to the byte at the 16-bit address in the selected bitplane (have a look at +figure 1). Reading works exactly the same way. Since the bit planes are so +closely tied to the address, only every fourth byte in the video memory is +accessible, and 192 Kb of a 256 Kb VGA go to waste. Eliminating the +need to bother about planes sure is convenient and beneficial, but to +most people the loss of 3/4 of the total VGA memory sounds just hilarious. + +To accomodate this new method of accessing video memory, the VGA +designers introduced a new configuration bit called Chain-4, which +resides as bit number 3 in index 4 of the Sequencer. In 16-color modes, +the default state for this bit is off (zero), and the VGA operates as +described earlier. In the VGA's standard 256-color mode, mode 13h, this +bit is turned on (set to one), and this turns the tieing of bit +planes and memory address on. + +In this state, the bit planes are said to be chained together, thus mode +13h is often called a _chained mode_. + +Note that Chain-4 in itself is not enough to set a 256-color mode - +there are other registers which deals with the other subtle changes in +nature from 16 to 256 colors. But, as we now will base our work with +mode X on mode 13h, which already is 256-color, we won't bother about +these for now. + + + +2. GETTING MORE PAGES AND PUTTING YOUR FIRST PIXEL + +The observant reader might at this time suggest that clearing the +Chain-4 bit after setting mode 13h will give us access to all 256 Kb of +video memory, as the two least significant bits of the byte address +won't be `wasted' on selecting a bit plane. This is correct. You might +also start feeling a little uneasy, because something tells you that +you'll instantly loose the simple addressing scheme of mode 13h. Sadly, +that is also correct. + +At the moment Chain-4 is cleared, each byte offset addresses *four* +sequential pixels, corresponding to the four planes addressed in 16-color +modes. Every fourth pixel belong in the same plane. Before writing to a byte +offset in the video segment, you should make sure that the 4-bit mask in the +Write Plane Enable register is set correctly, according to which of the four +addressable pixels you want to modify. In essence, it works like a 16-color +mode with a twist. See figure 2. + +So, is this mode X? Not quite. We need to elaborate to the VGA how to +fetch data for refreshing the monitor image. Explaining the logic +behind this is beyond the scope of this getting-you-started text, and it +wouldn't be very interesting anyway. Also, mode 13h has only 200 lines, +while I promised 240 lines. I'll fix that later below. Here is the minimum +snippet of code to initiate the 4 page variant of mode 13h (320x200), written +in plain C, using some DOS specific features (see header for a note about the +sources included): + +----8<-------cut begin------ + +/* width and height should specify the mode dimensions. widthBytes + specify the width of a line in addressable bytes. */ + +int width, height, widthBytes; + +/* actStart specifies the start of the page being accessed by + drawing operations. visStart specifies the contents of the Screen + Start register, i.e. the start of the visible page */ + +unsigned actStart, visStart; + +/* + * set320x200x256_X() + * sets mode 13h, then turns it into an unchained (planar), 4-page + * 320x200x256 mode. + */ + +set320x200x256_X() + { + + union REGS r; + + /* Set VGA BIOS mode 13h: */ + + r.x.ax = 0x0013; + int86(0x10, &r, &r); + + /* Turn off the Chain-4 bit (bit 3 at index 4, port 0x3c4): */ + + outport(SEQU_ADDR, 0x0604); + + /* Turn off word mode, by setting the Mode Control register + of the CRT Controller (index 0x17, port 0x3d4): */ + + outport(CRTC_ADDR, 0xE317); + + /* Turn off doubleword mode, by setting the Underline Location + register (index 0x14, port 0x3d4): */ + + outport(CRTC_ADDR, 0x0014); + + /* Clear entire video memory, by selecting all four planes, then + writing 0 to the entire segment. */ + + outport(SEQU_ADDR, 0x0F02); + memset(vga+1, 0, 0xffff); /* stupid size_t exactly 1 too small */ + vga[0] = 0; + + /* Update the global variables to reflect the dimensions of this + mode. This is needed by most future drawing operations. */ + + width = 320; + height = 200; + + /* Each byte addresses four pixels, so the width of a scan line + in *bytes* is one fourth of the number of pixels on a line. */ + + widthBytes = width / 4; + + /* By default we want screen refreshing and drawing operations + to be based at offset 0 in the video segment. */ + + actStart = visStart = 0; + + } + +----8<-------cut end------ + +As you can see, I've already provided some of the mechanics needed to +support multiple pages, by providing the actStart and visStart variables. +Selecting pages can be done in one of two contexts: + + 1) selecting the visible page, i.e. which page is visible on + screen, and + + 2) selecting the active page, i.e. which page is accessed by + drawing operations + +Selecting the active page is just a matter of offsetting our graphics +operations by the address of the start of the page, as demonstrated in +the put pixel routine below. Selecting the visual page must be passed +in to the VGA, by setting the Screen Start register. Sadly enough, the +resolution of this register is limited to one addressable byte, which +means four pixels in unchained 256-color modes. Some further trickery is +needed for 1-pixel smooth, horizontal scrolling, but I'll make that a subject +for later. The setXXXStart() functions provided here accept byte +offsets as parameters, so they'll work in any mode. If widthBytes and +height are set correctly, so will the setXXXPage() functions. + +----8<-------cut begin------ + +/* + * setActiveStart() tells our graphics operations which address in video + * memory should be considered the top left corner. + */ + +setActiveStart(unsigned offset) + { + actStart = offset; + } + +/* + * setVisibleStart() tells the VGA from which byte to fetch the first + * pixel when starting refresh at the top of the screen. This version + * won't look very well in time critical situations (games for + * instance) as the register outputs are not synchronized with the + * screen refresh. This refresh might start when the high byte is + * set, but before the low byte is set, which produces a bad flicker. + * I won't bother with this now. + */ + +setVisibleStart(unsigned offset) + { + visStart = offset; + outport(CRTC_ADDR, 0x0C); /* set high byte */ + outport(CRTC_ADDR+1, visStart >> 8); + outport(CRTC_ADDR, 0x0D); /* set low byte */ + outport(CRTC_ADDR+1, visStart & 0xff); + } + +/* + * setXXXPage() sets the specified page by multiplying the page number + * with the size of one page at the current resolution, then handing the + * resulting offset value over to the corresponding setXXXStart() + * function. The first page number is 0. + */ + +setActivePage(int page) + { + setActiveStart(page * widthBytes * height); + } + +setVisiblePage(int page) + { + setVisibleStart(page * widthBytes * height); + } + +----8<-------cut end------ + +Due to the use of bit planes, the graphics routines tend to get more +complex than in mode 13h, and your first versions will generally tend to +be a little slower than mode 13h algorithms. Here's a put pixel routine +for any unchained 256-color mode (it assumes that the 'width' variable +from the above code is set correctly). Optimizing is left as an exercise +to you, the reader. This will be the only drawing operation I'll cover +in this article, but all general primitives like lines and circles can be +based on this routine. (You'll probably not want to do that though, due +to the inefficiency.) + +----8<-------cut begin------ + +putPixel_X(int x, int y, char color) + { + + /* Each address accesses four neighboring pixels, so set + Write Plane Enable according to which pixel we want + to modify. The plane is determined by the two least + significant bits of the x-coordinate: */ + + outportb(0x3c4, 0x02); + outportb(0x3c5, 0x01 << (x & 3)); + + /* The offset of the pixel into the video segment is + offset = (width * y + x) / 4, and write the given + color to the plane we selected above. Heed the active + page start selection. */ + + vga[(unsigned)(widthBytes * y) + (x / 4) + actStart] = color; + + } + +char getPixel_X(int x, int y) + { + + /* Select the plane from which we must read the pixel color: */ + + outport(GRAC_ADDR, 0x04); + outport(GRAC_ADDR+1, x & 3); + + return vga[(unsigned)(widthBytes * y) + (x / 4) + actStart]; + + } + +----8<-------cut end------ + + +However, by now you should be aware of that the Write Plane Enable +register isn't limited to selecting just one bit plane, like the +Read Plane Select register is. You can enable any combination of all +four to be written. This ability to access 4 pixels with one +instruction helps quadrupling the speed in certain respects, especially when +drawing horizontal lines and filling polygons of a constant color. Also, most +block algorithms can be optimized in various ways so that they need only +a constant number of OUTs (typically four) to the Write Plane Enable +register. OUT is a relatively slow instruction. + +The gained ability to access the full 256 Kb of memory on a standard +VGA enables you to do paging and all the goodies following from that: +smooth scrolling over large maps, page flipping for flicker free +animation... and I'll leave something for your own imagination. + +In short, the stuff gained from unchaining mode 13h more than +upweighs the additional complexity of using a planar mode. + +Now, the resolution of the mode is of little interest in this +context. Nearly any 256-color resolution from (about) 80x8 to 400x300 +is available for most VGAs. I'll dwell particularly by 320x240, as this +is the mode that Michael Abrash introduced as 'Mode X' in his DDJ +articles. It is also the resolution that most people refer to when +using that phrase. + +The good thing about the 320x240 mode is that the aspect ratio is +1:1, which means that each pixel is 'perfectly' square, i.e. not +rectangular like in 320x200. An ellipse drawn with the same number of +pixels along both main axes will look like a perfect circle in 320x240, +but like a subtly tall ellipse in 320x200. + +Here's a function which sets the 320x240 mode. You'll notice that +it depends on the first piece of code above: + +----8<-------cut begin------ + +set320x240x256_X() + { + + /* Set the unchained version of mode 13h: */ + + set320x200x256_X(); + + /* Modify the vertical sync polarity bits in the Misc. Output + Register to achieve square aspect ratio: */ + + outportb(0x3C2, 0xE3); + + /* Modify the vertical timing registers to reflect the increased + vertical resolution, and to center the image as good as + possible: */ + + outport(0x3D4, 0x2C11); /* turn off write protect */ + outport(0x3D4, 0x0D06); /* vertical total */ + outport(0x3D4, 0x3E07); /* overflow register */ + outport(0x3D4, 0xEA10); /* vertical retrace start */ + outport(0x3D4, 0xAC11); /* vertical retrace end AND wr.prot */ + outport(0x3D4, 0xDF12); /* vertical display enable end */ + outport(0x3D4, 0xE715); /* start vertical blanking */ + outport(0x3D4, 0x0616); /* end vertical blanking */ + + /* Update mode info, so future operations are aware of the + resolution: */ + + height = 240; + + } + +----8<-------cut end------ + + +As you've figured out, this mode will be completely compatible with the +utility functions presented earlier, thanks to the global variable +'height'. Boy, am I foreseeing or what! + +Other resolutions are achieved through giving other values to the sync +timing registers of the VGA, but this is quite a large and complex +subject, so I'll postpone this to later, if ever. + +Anyway, I hope I've helped getting you started using mode X. As far as +I know, the two modes I've used above should work on *any* VGA and Super +VGA available, so this is pretty stable stuff. Let me know of any +trouble, and - + good luck! + + + +3. THE ROAD FROM HERE + +I'm providing information on various libraries and archives which relate +to what this article deals with. If you want me to add anything to this +list (for future articles), let me know, although I can't promise anything. +I am assuming you have ftp access. + + +wuarchive.wustl.edu:/pub/MSDOS_UPLOADS/programming/xlib06.zip + +This is the current de facto C/assembler library for programming +unchained modes (do not confuse with a X Windows library). All sources +are included, and the library is totally free. It has functions for +pixels, lines, circles, bezier curves, mouse handling, sprites (bitmaps), +compiled bitmaps, and supports a number of resolutions. The version number +('06') is current as of November 1993. + + +graphprg.zip + +Michael Abrash' articles in Doctor Dobbs Journal is always mentioned +with awe. In this 350 Kb archive, most of his interesting stuff has +been gathered. Read about Mode X development and techniques from month +to month. Included is also all the individual source code snippets from +each article, and also the full XSHARP library providing linedrawing, +polygons, bitmaps, solid 3D projection and speedy rendering, and even an +implementation of 2D texture mapping (can be used for quasi-3D texture +mapping), plus an article on assembly optimization on the i86 processor +family. Definitely recommended. + + +oak.oakland.edu:/pub/msdos/vga/vgadoc2.zip + +This is a bare bones VGA register reference. It also contains register +references for the CGA, EGA and Hercules cards, in addition to dozens of +SuperVGAs. Check out the BOOKS section for some decent VGA references +though - you don't want to start tweaking without a real one. + + +wuarchive.wustl.edu:/pub/MSDOS_UPLOADS/programming/tweak15b.zip + +TWEAK might be of interest to the more adventurous reader. TWEAK lets you +play around with the registers of the VGA in an interactive manner. +Various testing screens for viewing your newmade modes are applied at +the press of a key. Version 1.5 adds a test screen which autodetects your +graphics mode and displays various information about resolutions etc. +Keep a VGA reference handy. Don't try it if this is the first time you've +heard of 'registers' or 'mode X' or 'tweaking'. I was planning a version +based on the Turbo Vision interface, but time has been short. Maybe later! + + + + +4. BOOKS ON THE SUBJECT + +Extremely little has been published in written form about using +'Mode X'-style modes. Below are some books which cover VGA programming +at varying degrees of technical level, but the only one to mention +unchained modes and Mode X, is Michael Abrash'. I'd get one of the VGA +references first, though. + + o George Sutty & Steve Blair : "Advanced Pogrammer's Guide to the + EGA/VGA" from Brady. A bit old perhaps, but covers all *standard* + EGA/VGA registers, and discusses most BIOS functions and other + operations. Contains disk with C/Pascal/assembler source code. + There's a sequel out for SuperVGAs, which I haven't seen. + + o Michael Abrash : "Power Graphics Programming" from QUE/Programmer's + Journal. Collections of (old) articles from Programmer's Journal on + EGA/VGA, read modes and write modes, animation, tweaking (320x400 + and 360x480). His newer ravings in DDJ covers fast 256-color + bitmaps, compiled bitmaps, polygons, 3D graphics, texture mapping + among other stuff. + + o Richard F. Ferraro : "Programmer's Guide to the EGA and VGA video + cards including Super VGA". I don't have this one, but heard it's + nice. Detailed coverage of all EGA/VGA registers. The Super VGA + reference makes it attractive. + + o Richard Wilton : "Programmer's Guide to PC & PS/2 Video Systems" + Less technical, more application/algorithm oriented. Nice enough, + even though it is a bit outdated, in that he discusses CGA and + Hercules cards just as much as EGA/VGA. + + + + +5. BYE - FOR NOW + +I am considering writing a text describing in more detail the process of +using TWEAK to achieve the VGA resolution you want or need. However, I +thought I'd let this document go first, and see if I get any reactions. +If I don't, I'll stop. Feel free to forward any suggestions, +criticisms, bombs and beers. + +I can be reached via: + + o e-mail: robert@stud.unit.no + + o land mail: + + Robert Schmidt + Stud.post 170 + NTH + N-7034 Trondheim + NORWAY + +Nothing would encourage or please me more than a postcard from where you +live! diff --git a/16/tweak16/XINTRO/XINTRO.zip b/16/tweak16/XINTRO/XINTRO.zip new file mode 100755 index 0000000000000000000000000000000000000000..a3146672af8a11a5e49281df032549a03202ee37 GIT binary patch literal 40240 zcmY(qV~i$D6E-@w&7B<^JGO1xwr$(CZO`0e8#}hKV_Wxm-jkD)@2je=s&uN8PUrg3 z>AG4`1{?wd90UXg#5mqs)He`2-xm)Agn|MD1R4YcL{>_eK}=IjH5Jx2#t3J;;8qdA z>}KnqWK|1!)o1>^pB(}^rUc<2gVpvHHv^XBXFLAGJ$t z*sSa&ux*aL-~aYAApX^>;Psk=SxBPIiiWM!6)r6NQ8kK6T!c*Nm_;x0Gz3gZ3$hsM zFHf+Jp}1Ia_W%gc={M#TsLQ?scua9*yBhI@L7pYtI;4Ei@5pMQQgAM|s9(Vv`}q4d zsA|HtYJU-r5F9abK{2h-*}%XDtP)|-4mw(qlCYPnWLQCGAZrGc_NygYA$9EpUBP?6 zeMO3c3^CS`9|k=BmZ7?$z}p(~+y!3l6IL$ad_qCzpyWa5|7I5}7|=`vLsL|s&d1Ct zQa1zx55%nn_Zj4Jgy#hx6^s$@0R0|dVuGiG-Vprm%t>xn*zZN*V0Y*B$@-Dcp%17R z!@V!K9OM4NJ)OV7tM=(31&|u?c#mT?{VU-Mq|&M_4@;|Hr43S?|6m#PBYda$o_d9o!Ty@ncyj1-!<;?SGWDQ;*R&HP zdg7(@NYAc`*pIR&x>0uEWr6 zw`TNAv)q*(=^cbjWQ0oowjI}$Fq}(ke^r1_rug=-9OtqYXoqw=1gIuo9kVUFz{Mwe zSuu1-GG}S{gRaMV`nw~>BBSNxcM=J7w}E_%H8^<4hBJVhk>h#fTgnb#ugc^(c$fbk z>$N#>{CkdD4rk2Q@h_A(gov}3k$<~xxp*ouiJYX}Gi9(DE=ya`s?gF+*$_(TNQM16EBcpO@McSICIZTBXWyT4gmIVW41952aLxCz23K)P+Nbl|kS+t@e zZAH_&f{BL=dT*jAU~0`8oF~9g1D97eEbJ`wU2d2tX{lMIwi}YG5qhk9n`OA<1m_wl z;R+`YKH>D9!V~#lTac3Gtt-lp&?{kPVf^U<#xKO+UbfpssOW%w?O`kPzj`SuM_cy{ zCg#BjkpylQPJK5D$@rHAtb|ALr+JX*GH~A3%AL#7@%VgfEu8p!GZk`<9Vqk8rRwx! z8|AZ^lyUM+nijJP(sugv(Z)xVp$ZM{$;xU{HG|E$9%<3C{uKzPSzki9bj$!r+*+dt z3o}P@iU2hz39ebTEZu5^V9nDzT1@7d+f3a#d&97z;-y-(V-H!?V`RE;jbjq5kb4WP z5~bq?y7FX_jOI)#*QL8+%yHvt65P2o#9%RAP}YJfKHj{0i zU4i}dp#FJa&!v5eC;8NIFCjvB8WSqP)= z#-`k&gXfkuNv>@NNJUL94wQz))VWy9H%Zx)20Y|4nBTezmi?sU6d{@pM< z+iucU-D}6Td!vXA|Hqnts1+!DzDP zI@2mO+mjWeI-Flqv+H8s6mLZ^ylBz>bKHeDybl#@=`5x4-x2+1-5N(1_Dkje<(_Vz z)>~bhee(4meLqrIEe_@!S+C}Cd^>T=1#8w08ORL#DRpC;U3AM}1^hHazx@VLybzbL zV-wdT`5s*+i|S-V=yAyPB=+zUfnIWn0ny$xkVgG+424#6KXys2bzML1a&`7u813>I zDVw;{wc1rv?pZxu->GeC^YbHcu$PrFd+O2y1}m4#7SaxMBO`6WOnqQ=u5~(Z(k?oe z_$frO3*s43(mG{y(Nw=Gq8aSz#z*?O;KmaKvhWps#He4ZV$h}$6TX_mCn~v%cO?TH z1vk}#;rwLv)E!89`>t_mOZO@6D@o_n)D~GTnm?PxuhTRplqz=OwO-#G7~sp0YVZV> z<74yRabXcHYfv96SlYnNO7E>W&2WNxP#v~*xUJQ~R z7jhJ4#YK$WIUVL;4qwNGBcWAIp^1IncQf|pkpxs?e|)5C)G_>v4!3NB)fL@K`}+2TnN0i{xm(pC5g~)b75e2^`May4QeiiyR1jWO;B`{W+@Dr zs~ioGo1=|!@Q85l)s@+um1#KvRRYTY+SE1ffcES@90y?JE2wdf!rr9B%^q!9FB&8vveVpx*~o^Bf1(zr%SV%-Wdm>b!cU zNmG8Q&*GKEU^Y-$Gra{;_vr8mrAcRjT});9eB1{~64);*S?nFTYOg?`?G8e%&io-S zsZ6XcuCmsymcU{Ay`7m{G?p66B(7X!N){xk3GDn2cOXH(P_Gi*#g^)=Hu#3t!G|^o zMYzaGHxSFP3ZX6vp()3LDR97A2NDgbm{@V35a7eXheJ>YA`Quym~kLu;l#m9LjDY7 z8qzVb<3Pv4kAWYBzz&2Ok}&Vg;IyM31l18HneL*(!{QXUWLXFL>v@1G--rg$FPNBht>(CA5=HA zX+&JdvW0Gk<_RPmlsB|!gkQ(Jg7O}`F+^^pT!+6xd;$Fo{vP<*2l)$)1OXisGDy6y z=!nBfKmbbPNM;#QGO$nx9uGPmd^B*s58+6{37d-`4_XntG;qF;;7Gv5^7l8pZBY1k?WFO9vyc13ru^x0S_;TQRAIg!m6LuTH9<(EPYv6hx$&s=X zejD)y^fmZ%;QRLg_`c8`iYE>)*e}S0pz%TU--9Xp)OW0&P`vQ@;PWBa12OyLcg&uU zJ#hNq4Ivx@Is5c??4Hm)@Vnr*A;<#}`=ob&-XMJ8J_arJUG5;?(0n2Lp!NbC20iwD z?!ezrzaadf`U4FH9riu$pm9J_JlM?r#^|!-?<>f!9(34wg-Eve)LzRtYXg)&eNmAv z%U#SI4X6_iA^suhh#&y$b%u}MGep|O7q)%ki;&>G+)HCIshoN3Qw^;6$Vs!b+n%Zac=U);TUb z-C6|WOC39OQus8-L^Ra^mClQux%B^W}oIi3c+N%B!$9b^Dr zUkBC;Hcq%>ONc<|R(+IIOW!C)cLNv8!mY306Eg+ZT0XWaYB&O~3(zL1+?RqQUTVyG zs=|JSa*zftk730mDiHrdFCsgwe72$o|J13(Yh;VZExh@Y;mO4oQbfWwv)9K~ZID`b zP~)(!J0r@Mx7fC5dXBTuGfNTuZla_L(x5RQ%hEI}1U<#dtvmwq?C$zsbB zPRODhS4OGUaT5(flE=Ie6U$VTL0A_((SZ)eIjYqJ50u_`gP*I&0TfChtG#{4P&`bp z*;;-2ks=mkGyyHj!uhA*ZO+E?fpN3z*-z!EKvqSs@hlLPZ!o^o>aYjEg6lTLn$VB|B>0BTZ@n4PGPdS%d56nRp1FrKJ&D zP<5h?+0%o;QkIQaG12+8QS39$vX8TjSFWmvGplEhUniQ?y56~}PQ?x^_4Wm6=q!R$ zaGwh%1B7JlPQ*8Z_Om&JdF1C>u-ln+_m&(n^uuJ{$*d?@Qq19}(M(r|Q>%?a*xl5!>W*}9Kf5L|F^f5t$!lQ>%m=-FALeIXGebO{-B{S*&ZG2Qxf%x4bGKHXLoAiX?4}XtU?%L!%=$8s{;}LIo?s9RXVW?l0sPiPQmipxy;64^t>o5tFHlM z&J{S9&;8{K=|Hb~bVHEEw&OG#85|`Jy(5HD&tt-)5OFcxLoXQyJ)(g=WI*$wW^jc| zwUM3YZ~Tx7I)K3}8ZWr0wzf5knBXrh9pCb3VQc3J>)XuoCwTl{b74e8 z{fS#x50@kPyZJkIz4+2>XB6tWP-W4wyYf0|rT%vvyMLjm7=Q$I|2Xw+)c72teAl-w zugR>%m?`}_eRGM%K-PzU?M(B4JP4x5JOAB)t6l$l45P6Ae6T%=1o6jN_bw)yW_P`8 zCAq(U6qJx3gD5aS?e8JX?Krk}2OrH~c2_%}JmZK^^_m{vq!CY*Z3iw`27fXa(gK$H z=7h&!s$X~TGtT5Fbt4~1@A*03>xF5Qm{v7+1BGL2{YbY?Ht0Z^H@CTJy|K|U z(@%~&z9CA2E!wOn6N zQ}s0rM1=LBMxfXyn>!^0r18;Zm5RoWXiO3i(L*AD!W3815svDN`4xm=OR-C{*#2-| zG%nPOjomxws$C>(ipU4lv5?$rQwsiUqJ7XEbVtJ5NLMm3-4J_S!%73XGX-eG3&vUR zKgqf*pBeJGh=#MnW|SQm4?pIUcojaFi@Y4+)w1&a`eaS3*fnrg2^wHCS7)KbEXI3+ z6T9eYb66wa&O7_ZMDIR^y#1mx@>}|N-ZRy8uw(#!gh_G$lelX~7>7(hK5yvR595qg z<~a@FY7%-C)tT8p^<`7gGbZ?1$!mXUbkSnnp(f-)X0OQ~_HyEbx$8huhS zIW)T408Q}^uFq5=S_de6;%7+~u^I`F7s9fP|5ii@T#iJnpt+LpRS1ma0`|y27@j;D z=)FxcMwT~5g4GSmxk6**O#OXQP}14P;}mU}y``0@TtutLsEq)AlZmt4=u(BW-LrRY z&W4-&UQXkfoKWG; zQk>KzcH4St-o>09%YmOhaFSBIdCAJ7cc+NT>TwqH+06916c4&7`~|Y=8lGz9zf-eq zkOmZ8E46xqAJNSD_K2NI<_9u&It~Dn@l!-d;v<=ehUgUx$6U~96ar-#VmlTDbnrms zpy^1M@F3+t(DB4?A!$Q?Kn>!a;|SbctGxoY*cm5Lo)U#)DC2{g%CT|L#8%y-`*YGNyY13w zZ&+OExf>oJMw***+d8I}J_hQNyBt&7sKFykJqc3<63Fd{_MT=j+a1X6t+lZOJ!Ohf zh(mHEJ(T6s!W_C$j3xPslb0y*RN0msaT?BVx%_owAC(M8*Wzt5DP9^Y3=kPhrs|V~ zKi15eWK}Lg6nz=0j@^NQG{QpNl)FNaZ%yC%>;rKFpp@ipFg@ez|PNuEq4|?~*)vQ=V!WOj!^guXLMCe)rVp zuBBOy2Z^NoF-B8DplSGbFgu6~`MAszL+$M;vFXhbJz?YSdXXgA4V47H04md+<{}3TtMQ^n9OThMWQDw& zS)TGsAOvm;;!}5Yis;3-19Yooz#lM-L~|r@0WLFlotfv{Kct; z4DY^pjoQRe{#m2b8}k8WofJx4Z*)^|bks&YX2s8Ind1)a;}Ori3c!gl!Z7>&fqmb*H{W=9pVk*zqe- ztjl)s!9PM?DS{y;{4NhE__+8>$OAT6R$k#*be8Z1g>fUs1`^9vUZEm=rmkTp4&iKS zqB7^H>5p{`O7F;bDRP}{l(4j;MA!>{XvAg9V21x375jg8gv*_Ke(WK!`AjJ~fcjcDoZs> zt(Zk)<);Dsb{3ALoSh=qcsv1KW68u?!=x64eK!*s-sRO>1R(yf&NrXdgD?|qH#u4> zvnh$5M@B`TtdzqU!LA-I#6|s+!YuV#(PLMCJr6%HyEMa8Ydm3r&VSTf*m0B<)bQ|0 zK+A-**0z1S7Yk{uO$51)o*+Gr&ZGe)UUG(g#k$p^YxO!6wXp1>X^Jd!gTV(n_FDMX zrn7R=;CR^%Y(6`i1V}U^@0tNJlP{KvVGO3b~;D|P>^9BFS4DVGSXOdT|uNV@4#|_sT#bqW<$7f6pgrqeEF}%Ll=d(N5Y333gkViLkl#>uys9eKqAaMURsO0{zC@4!X2&st7s>wOv2_f)d zM*;8Rg`}w(iD3bSRMxbm{#8{pY#l~xbn507XP#KXX+#FM_P+67k0a69f2a|)({(G|WhL&A>JE*`Qv0wBW z)UxepOe?uW`Y2Hf-kNB^wg2X`|Dvm(2z9U7Vb+s{OKBk;0Yq`1jWF(8JgY7W9vk-d zqigon*f;H44!)W;v9^;1!K(J-SfWZ!h)vPRR(0_IKFTdA^k5#6%@`UTa-MREL(gPQ zA7jUc4AbJUkDZ2X*@u6^fQK43s_5zgZCNCmqYa!ajKGTwgcL8Oqw22phr~=Vixy`n z(q~`1JrG3O@y?B1w%3r)r-n91?)~}AMVOyw5Sxvw+LZ?4$?e0*I^1$xHbawMj^`6$ zP*AV9tmV;z@0{N2iMMd4b*X{(B|t8fml+1@(M;r>TA#}OlT_LQJLX|SQ1l9A%_T}#0@ z)=M=RxkFH?TstdQo6I8n^iKeFEh44f#gL(r%P1JJjFsNS)EPWF7u#xmTOu2u(}~ff zWT@kfXL&{ad5cPXvsDJ-!d4lU5MiWVydZ^*cQ&#nWPFnDNvqE18&|`0-82Hb&$zqKF`z`IGQnqJP!*>0dARlKQHzGZd2?PZ@M-Mp*ao@f27?=5hk&{2{OFJYq8 zdD51<;BTd?be(p?dae8PwRiu1qo*uG&iro>!(#Cc5r-FVOkm}0@~5uC!n~H7Re-;< zV~DR;WRxdvsBV|{gv zQ=MNYW=^+yLrX+yQCiGMO-7eZY#Uy*-CShqLe=v6dP2m|@I?A<)8YI;d!^gT$zk8x zNnLAa@nqw_qs7OmmAL(1^V1_s<#tyCF2c6%sM>`r!i|b zdt)J)Ku#ox$?;;oxRl?_BIi~6HHkoHtzfO@EJ4@)O*OiS!DG>MexC9xD-}IqQrd(+ zrc}v<)3KCA%;-3nWhH__1>AKsP1HRhNtynw6%!`YP3DNkX|FIB13s^t#@l#Kd9^O8 zUUjkBYx{kj5+!6iS`%d5_839dM_V@Zn@!=fFKHKPj@koS*PXU-?KUz=eh%8Xx$8F? z#XdXvW?!CXt76*Vlp8*5S#5Ix_r3LqTszBSOxIl$--ucFhn@Eq-?J{I{0H?wC-^LE z2Dek}x}!WU8Vi9mucU@<#P3Gw$62!);7C>N$Lk#rPMku2-}mR+BHLcI49&Vh(J$=fs+?Zq}uZ$ z2#?%~*xNZQieg2IRB>EH6+@BQE_;!;+aYe>cCCh3CQa%vMK=yJ17Pc=NOXmm#;N8{ z=s9=*BF)sgZE-fNs|VG!&8?hHux(BjMp5Ir%e78&j0-2q679LFDAL(`Co=P<%{tSQ z4T7!83w;&=s9w1G=2W?{#>5tu4BBT}MXuh|%hA!ZFoaHcPBglOd0yD%`SwsRuqaS zD@_?n)|;v_>MQyx9p4z-cCrDs(e0#Kzf2uguAEvtHq%1@%KnC!Q_#*X>2s52rIhF7 zFQoZt!gg#Kg`=1uTI7uuEW?#y)N(igXcp1_O&PCDO)WcYS~63+u@LT&sV_)hay;*N z{;PZ4^?kj5-3x?fc-s$!c4}OAkRV7}vh%)hXryA{L+Es+WI)eU7jUBi4&PYw+HtKY@G) z0y@K?FaQoI%IF7*jAQuy45b+L{ftbo|NROb`Ybx1&jZKmFLr<5eLING*mFNg)Zg7UwBk_U7x!U-{PTK9TL6Nd%FkQd;BoCj^mWJ~@Ue00|Gt&~^0d|q3`=kUpV{|= zTMq{ZoAI%u2tZFQgk-E7#M(SFx4AO}i|QCSX8Y@foU0Gflp*}9o+*%j zKLe`1C~4o9Fl!km^kYVQ61MbjBE&6Gwy$7~JSdqWTNAz(V+< z$T6Cx^*2gK=NNCRQjBA65ay9(BT2mz@~soryRl-1(Sj3Jz|0_l9uo{Zjx!&IO>imL z2D13rRJ?sI?5W{t4pq}NS9kED%p5z9OtQQMC235;7tXj4_k(bvt~inIXu5(JqKci& z`d{OSHaV}j6!j*AWqDXh{VCMsFxL{5hY_+RJ6q0%ueeFg4qWq(Xq%~RoaMP!36+oL zBxA0Sbf z%VgEmsdy@kmGOykYSj{9cxns~C)~BsNvh-H%ip{e=?ZDn>UoN4A?a%HSYTM2hFt0t zxzGPyKMfWats>iLnrqyTPWeVz0B)OYP)_7$2GBaHxlrkiaD26-m@%52hbtDLF}0?Y zG8TZM1<&rUx@iJnF2{W zGm=4Sg|5)uMrQ@*Da|Cw3MYdDfbt=2z`-bEpW%q3!oVFewMN$LR%~M`w+*|MX3RL$ z>J?D>ox5{0a|HgnG1vn0h&C+ARD#j5DW-s?gAMRsMH^F@LAv8@3F za?4Qn@*FX^t5N2qDPEzMOeo=feHyAcMd$hmS|(?6@&>$ihu6k_K7H{8?9%by)ar~> zY-c7G2McuCB42^#h@1MKFr6#gy=>3j4f&KFj_(_+{!Fl>`riZnd5m#m@%pXV@v)Jx z1P0{e`KkD`+pKvGZ>*W4*tZ^I|M-me(B3!Dk>1C|7>vLur$({l?dvWtW)p3q4MM3X zb~Td`1e3dnpwI_#n?jWGAu#sMedaPd_3z2)z zBosat1LC0E`VZ$OM$gB(+-|6ctSxQQYPV&jObpRqj-3)e$e(tfB?~T4$Rwx^AL(2# z#Fy@L=A{KQQ}5#{Ix`XaKIbsM79)9ENs>@{Gx@~F~?0$+XCvH{XNYceN+7_{xJ=YGYk*;*M)d; zs0Cqwq4`)i(^YsYu7rr9IGwjku7sO|nFr5~YtuyrwO1HOaRy$ay3Lb^!k(#!ov{pX zFpmuREx7WtYO1hzs%pG>uW5wMVutr&2e3`}nsX{!o`qR=hEH>ZM3hwq1WSgGwMW-Rde1yZH+DwFN_xa=#uTqdXG%tP zQAt)*DpyfK40nd>tw#XfVvyWoxYc40Dq;uM?dv1GHv(0wPhyQcW0R>QVJ1TPq2rn- zVxz`=(ujk`Q-i9Y;ze=dm#8ErlwA;Epf9N6r`O{p*`&sngBd(*A154oA|soMWe!Fx zzE%=EJflFe7`@G8l_P%ThQw)9#^q(kLY=!korPyp)RVIbK(`_U(z2%VmZdxTbKz3dehdE?aoj{uL0!P5o#|sVz5S-iRHD z3y5_!%oH+{?j*_gi_E-ziDyz3{QtH zPd9r_(Rxo`A5OPkOM~W0QFu)he~n8rO!uV*k$BagD$fX*bg6^P2)6=6X$n1_xmZ)<0#BlgjO~<@TeQi%@ z*f6U0vJ)arMKk0>56pRY$#LS!i84>s-^j$y$`pBXkzvk4+fQ9ccNLS!odvk6Xj-+u zXLW1k6;)-PTLukUWngm!k)GxGY-CJkrSzR5nU5v>6VC|*Nd-`gDUamzT3KIIL7+uN zOJxN=0uuTLfEnof*%0qJXOVVpP9tv+ zid;qST6h?6`8lA!#LnSix(ea6i`P{0^`UazqEgYOY|pH6>m7@H0lB1-C4v?u?Af-E z-0&C>*`LEX{NBaufTEzzJUYC9yhaD=_G|?!(5dqrFd8Q54?UHx{D}ATCMow{?|G`0 z*;}|-QqbjIOj%~s+1V*sB~=9$U0E8@Y3AC$bl_a!EECEm%b2ut!QenlFA6-fGyL!} z1ELMXHp=a-3%#VXFW=HAxze}H#LgNk6fWF9lidj@GSV*6L#xwLFR-1o3x+aNLoL#Z zxXTl>fki4($ZFKGB{UVeiB-aYG_;_~pR=+X&6HZTYDFuruI$jvi)xYc6t1x(k`paP zt=ci~+KK4eX6=O5sZ4S$i9xs`^o?R~PQ`x{DV?Xen}Fh@_3*!x@W{4@vaT`uaQ zrmTs&nO-}Cz+_@uTYTCJ5(q0-Vi(BxyqAT8O)684{N>|X= z09z@nJfvch;NjaqXxhX#>+o&b7(WVCVqyuW+hp+T0@G^EecCN~njfgz@kU#1yW1Uj z+G+4QE?d;yIBf?WE+0}I!v;iltZqY0=VY6(?!XATXJ{%~D57on?IXLYM1(VRZ#5$tG z-dJ7m_0(O+)4R~&_F~~n*`Wbwk~K21LGH9~h3T=UEnq5E-{F+U)Rs|=F3w;Daw}q@ zEWdT!#B@MN`kX*Xw?rrmrzvov>#;=A&HLn^R$F_-bnW9OT3`AsTn>PwDInr??tS** zzQi}B8iu$Iy0Z<6;A_ZB+TJGjiqwSgSR(n9C6K`ba%_g^eIaR@hXTd*a^UKfGy)i8 zhpR6K$MF@rR{a@E!r(M|NL6GzPW>@2MzltUZ~q0(@<@ODsE z-p9!7pHnq|f6+6t#(x8hMjTE|A!z=2ftOjq{wcDq%3L(d$cOphQ;+ht5wO;ra} zPEgX3(|Hc_^IEj#1nrF1#^S;D_En7v5@*pHm$dyBq2!9*31Ef4MVoY&1Eot%X1hBOnvSt1{)qH;c&wP``mSvC z@*{Q>Kp}GZiT1?yXI>WJal@MNfsV$mo>Py!=yZuiw}G9FrP8^fBMzC8Fk3$H^Z#~RCZ2?Gjt(w3kBCJckrvvv=vY= zAQg72$Glv`aDxGxTW#N)`m~(`5heA1*E;2LxM(UfyI1@3HkGYJZ(tb7`&s~t= zupnoTLw9x)dmM3R{H(?Y*)|eTdsLJ+(uwX^u4}YO2(9Xu+p^gE}blJaPd3m3S4Fy-m?igg0-6e zT=A8u|K^vU>%c(MR_isYOZ;4pd;^Hh(UDw=nyi=F)qd~XKbWNnXbm!P-W4M0YXe`5 zeT+a@zxt1zl!BiN;u>F^n1H9A1{nIaD_Zu`7fx2bNv)aM0^*ymn>*R>q4uAkpP#Gr z$;&6$#?#EO64QfZ-ZlTBS+Q>IHiqVzUpFK^RvHl_MRWH=;rESpM70Q)!0rnp8BO?p zwFUmW)VVI6hVA-{N9E_o3;m%qhUeIpZR?-@ zXYt!drM(@_fG6JmnQ8hL^@5vO1ZthsXH$bmNyfXkpF1idV%zx^4aVmsf+hYORFYwh zsTdy?0|Yn5T$6&QSNT3f;IQ9}|Bu~^{NBri{iy#bdlT6#9phtsz^fthET#cXE~N_z z`y2ZXK(yhV(O1pfB@||Sj9wu*>+?BL;5jSdrIoR_rQqISzK3X)w43L>m?&C=?mUd~ z9zA8anEv&8Yj7yw<(2=B`^;NAw(X8RO~?Fm4pEas#B~H%c_eU0qb1n-^HZDWODg{M zZ>X4V$DVxr`6klrCE1Tv=T`z_k8K}tO|h<*Tt@+};A7;vf6CzzvI{CuUi%Z~G>jl9LQ8PQp|fV9K7xY{5!drd+6Is~+Q3r1(3x z4)Q6md+buZ*SurL0hKo^ed)~2S6_D{?9&I6X`qCMZ&+kxgiDNPENM7zh-I*%rloQ^ z1E)V#j!3#xcwA{wnRh`+Rcxh0hE_(sRa2!-Yg1=imvyI8cMD;@S8`VV*Oa00n#Np% zDK7JF*`DQvwZX-?N>%?%exsSutpLNl^Qq%y#gm)+H6OTkw{b^xqRtcBO!uqzE#4*u$!WmQ?XL-X`2OcIeGc0>V z0UZd0>0GJS(y3flp)j?{q>JQq9zL#&CF17-2XjefG}Wbh(JM^V_&)pJ*=osWmha7e&qZH|!L z^H{g9!r>?LjLk}(Z;BCUB|`LJ^pv&fahfW?by>=MhI$gqqKE;3cr4NhJ0{&I2$SQP z*z&R*(}=ygJ3Lxh^RqEB?7t31S(%}-noI<6#5FC0^{};BRwOp{kNBj>Jor7@=%ki{pYE}iS-|xiugnI)%a-W& zww)3TI6X@TD_i6XD8a(X!lq(%8poP#6XdFn?_gWTqwkbTzg~tvRbEJY*SgLX)hB-7Gv~QBp^CV zB`YDtSVk^+iJT`Jxhl7*YXiYa4T#?S9)ym0#F-ukt?`CfenbE$?=eXvk=NsmK==aFUy|x{K=lF6Q zL08zmIlBY?Xxql0hvuqIUe0PddJ?YrKF(NGy>rgJv*246BnFXJ^~h5C*cC~+ak{Q^ z0DWUN@+!X%0ZX9q&&fweye+}}c^S=kmINtmY zoCr5nKIT*gP#6&9@d*qO>0yME%I-`WLXg1;UpXYMnW&`)B_X141Vpdq!Yc9fL6Rc) zkB#eEj94FXvY9bPrs`hPj$X8Xh64fsXZhTMJbuubUyi|*c&CVat&ZXYSK?rBZ$bY{zC^^WIL+r2SkN@ocB^K%wi>+UbTFZwvr1wW}&j#xe8?Q zGE_8UNTz6+T2(Z4172-KC;@TKG1_Xw&q8sj;3WvEWZJJ& zg@z4b6W3+uS-L!NuF$CFcoodoC&PXB;uY(_dsfotOXRRB^WAp1$ujxa``*yZaV`tD7ZNr1lKS8<)%Pmj;0AY zMq?*c?jU>vBgm!9-K8R1Ee1W>&f)E+7o+BVTa*SJnL@mFRp(;r!aLaYo12<8BH`N} z#|xxdcDLAD6&)L$*R7+?>6X50g_U;q-5cS*{fnb1>_IXz6MY=b_bZowWX$*O^qE6F zzt7thyILQ1p(3cJ9E<$Xr?>{utYUR(X|bi*q{!4gDWG;;lcu-gNI2xi@U!kKg{xp& zW>T{eGwpzv73;SM&DybN1foeZCUsBgOSs%^cCT2rE>AgLmuARhjkAFpGh;#!YGZck zF8L<_3w6Eazp{Ey+^D@v!W`U-$w>c7h+$9qo3FD|-Cc7v{>(1cr!FnFwo-`MX-zFe zq!Rj`S4v%<>zaEzyR&QSNncxg_J}#zao@k}~(ze(@l zyQG(L-NWDg;5Y4ix4RAaT-XC;+DWY+T0WuxI zRlJUwT-5w&%Z(o9P2xVvllS7Y*q^1- z`tuD1y&Km5yq7lk$2)xTE}RT_c249?yI;9(>9AgQ4{khq=Lzq834HhO^*xPAer}aD zeCzQIJO%~w^O7UnkEsRbrzv+IvMT8R!3KEFW3xSd%6^`uSa~n7{CZ9?`0nA@^9~)# ze-_W+JF`xBU)$5K?Mg5|_YyeXbKrO#)L^>zIPf`Qq5GdH#^nU;j1K;f=0$!Z@{N4??fr;Xu zKRdU6U(*7gH2{#*e$ZS1SZF_ZC_s;g0Latw;WLn$G5{h_YEc9667Qm}SVBJ@%rbWk7n(D=5~_Vmz=w9%*bFkG?2$Hp-pxBgM> zVNPvjq3dByZD&&LV$u~E2pQ&08SX6+VQvxW9v&uN8tyz2>3tAs2Onub8)+dGtzs5! z5*aB|9;r7Gt*{m;^%0TW=DNxmxvUYDf#3t35e3Sz3d*PQ16@RG(MQusMypsx6NSYp zRK(~%M;?3x)n&UhLs>KkxY29HbVfvVm%9|V#hPvUwaB^*mst#sN5ApM3Pi?4XvIHb z1kLHX^nJ&ES_I9O`6X+|KD))Oa>Wt0$KX>1ZOH`fp2l8nh8;x*oX8{?Yy{nHB|Lm3 zJab{(awWWLC471$d}k#5wk7reK^jHzC1ir&qRbpwTpcNq5G|0CHuzYGt~6WO`;~ zoMS*hc>ZrjmA&O37vldIRT}^O_lNzDcOs|x{}HN2)%I+*m{9!ne*=d*B7}sO&?vu~ zj_Fg~j*G4(+ufezn&#Ro>2Rf@wiX2ZlL_bb^QCc*5hA{K{5%#doVrlYS5YWjww3E= z;ajD$(E78`{~zY=p}P_;Y|wCQR&3k0?TU?xU9oLDIdLjZDmG7Su_54s2a z1A4GWd%7pj+Sj@tJuzB)&0My^C^HvlZ+yE-WS8l2Q_^9KC*N1QHsX;wGMLz>Czog< zyo*?*4z9+~H_@W?^SnZ2ZC=kjign$=!))qg0^+VND;U$KkL+O1dm`)gB`a|IFgwrwZ#2oMuI$T~RAR~vqnSA60dD*?8EI^4>_!@qX zy@Fc!3X0}PdMaABVIP_PWPth?~@GpRvVBLYDC{FSUA~YbD zmiJd$xPktb@*@R*gKf_Aa_R8STmeizr?!uI8Rt%x0ZG_7we%T(1V-`R7QG)X*T`x@ z*8Av+7#(%b4U~#xvMQR%Uyjm~5)LlES^i5NyEL?e+5J6OX=DZk&^~+xM|;%8r4g zY<*v!Tu*qferF_m#}*`aMeU`tQ-Jd9DjdW-(Y8)kP#ZU&IJjzQ6kk?8XP*N4SYqbQ zub0x=^<#B4PGCz|=NY_3M6gs>$Sdy7(SE$!x#T!wS%JjVncx>LL+D#_>sz8-1-(#0 z%9rs0SJ1@?(wzo94l|qf%VH3A6$)!qn=Km#0?>6V;jQv5VXaXAL!odSU-zPDYG3!` zc&@$n#Yi2VDnph3oo#4$oOyopglc}dZan6DWP0Wp>)tO|awM}MwJu#XTuf=f3QP|k zPgDN+T8MjVwp;Nz^A;Ad^BjfF7nB7Xqao>ogy6jC217+6{d$BH6zzLj#kds(-}E%@ zgMbP2H2L=iOACs)ALsb?dze>e0Y0r6CrW)i`|b$69z+@ozaL|S{ni3>HW}K9 zjXXepB%SoU466h@R_#1Lz5xHdp$35?Z9-zVcfa(j1Uw8DJlB#Az@H}uetnRDLF@Ek zFVF^G=$k+myojDlvHDU!5+jV3i$7NWMkdTHe6ZyO5}4iuyiV@@W0Vy}DoYGvjx!B4 zfs@4ZLGvN4HiD-PgqohyGApF8ZsC4 zR=kVP64lQNa~ER)+Q+M@ml9%ch*t?KCTF7@6-i->^#bMNqn=5MB+LgVF_Pg^@yfAi z{fLQ0Its-1mczGXkB@jXC*eAkRoqrh4U;^Ar|XbcU01VidjzL-9iP;Dbb;;qEM;v& zoBB1-pE-7^!j@_SZ^_?;H0gItQ6e|ZBH5H3-&e-nzbmKYGx3mb(`P08G(Ic$*p&5+M2md+rWk_2`3J_rQXF++Hk^F1 z5D7>l8Ob*v)!6i1)H_rmHCd@@IitO!QBY*STF z!%kF_&cnTm*pOalG<&)-<*9my^Gti5UZX+z&e1q{ z2$~EmS9W#4bgnK~>Czb1Zgu1bc0)}3O{UuNy_vk7_Hsf1ixDi6O_XtCxh;c zM{7e8m4k_r@A^QQR!giyjg`f%-YSAtYr+?!F}n4}(mr+z5Sr00Ft%qMM%!nQs`ic5 zcXNY&CA#yQ>jE?9V)F!Iu6Cn$nGISa)2(_jaP+oOkF=#k5Can?rCVd#CGNdGiW zvxwU#_&_idpl(cL!$0&8&z!)obu??TUnS>R8`DkuouYzdLcilZ%vsIlpK?E2 z!O69uD8lAEsm&ej$hTNC=ErWo_eja_miZt{=Q!2PL7~~qZma8tqlG7?lIP({ansDo z>sC~ot_e_p7GoOC*DB)5+<4`&Q}qV#1$)TGe7$m8?R4;IBZ}laUc@0}q}`=VPF9sQ zHF86MXG_~7lgY%poBV!DdXMe~=4u8{y}#Y6=E~YeZ9wDSQRIDl8NbzMt(OclFk?Mf zwV}rdHv%Ff8;mo3ty1|Wm;!nVEv_z2hBiZ*AIgRZu3Z~W3C6JwU)FLbo$Y+T?>pwd z{V&)aybr3?+ed+y<`ehcBcsyXJ?Z}Uto{s(b>Oc(b=x<`uQOJ#u&3UL_B)H~SLZh&z!q5jxXJSzZZe1{0`wY7k7=I)Y=J9KS7AAo+f^! zS^62FOw*I5h2CYGqxFtV?OXNv*<@+r{TxwXOz%dfz((%ZH3e2l7Glhm{LJU~%r6^$ zcvnsyNZ>^5AMTF9HjH!64$M(I9bbbF@_#L~EO( zaBfm-{{H{~PL$sqE5Ak?8{v!pE)K$bw5lGs>McC#QWXdrxDf-g(L0$mpo|}*8VMDv@%N8$ zv{oAJ;_7fG3AYt+oxDFu4!G>f5?@ba24y`xSQ9~3A!-9G;B-lD^@-e#NhiGIDBh%t zyvY?N$-|JzW4OsJa54CF=5JoAXJbB;x+&D&DYUviz|rLQ$2jfB6xK5_us%sn-BfHS zFt)5zR=!m3wN%dNRDQg)*}+s{-L!oQHSw%82+=fY-86ok_|vHG7XsRjt0c8iTJH$D!gU7<7IOEOuiA%OySE)>j318 zXXV)d{IdW)cv2GpNOCdR@Tpj$>B4g0(sbG8AkjLTOl~@Gx{@44$s7su91OHn zZ(VSE%ABBa=Yr^L$I5KRv$&ed)E{VR6XQ8bXF0uR!t?MV?wolbIbn?3R5rZaxzIfK z!%U&IynjtHzI+)ibouLNqHAk{l5)Ajy1A#iSv|=a$IagvVt54uSvlw4>0fgB>m7Lw z(c+!n1^IaSQ2hB0@PCXj|CGVY9`Z?GvZh52iR_%^oq6X@&}4?ZXM#x9<$vd*i=j&Paufz{(rSAH*|?JR+Q&u2s^?1C?*_*-s3U%=HV;}BCIFadKlQp|=>fjw9Hv{q=h zUN!|^L`R#B)LCQ!|0jGR6QEaUFp+mkSDB~xM^W#)R8X=2d$&-&vjPR70QbE#*|wa= zyMz!>@|K*N*YPK%GS|{3&wRY<7hhosLM|nK$unOGfo(2OuBzIsN<5;f|sjs|tp-5^z?11yxf>SDR*2<2F&V?gLoW%bW5^9_Rge_?~(EH|+wUG)K42 zG&=VsruHhEWLF;ct~2u?JMGmc1KcVhX!P zD7vH#SQLe>)>XDZCV^0GozPXW1R{YpADt$$s(8}U0z&tu^o#mn{bsz_jvRp|1+esL z_{KtpmOO=)(2It0g4Sfj1}uWEMu9GMUZtAYPJnM$epOcnb!+!VLhnXb9YMF5LU$>5 z_lSVXxNmo5S2xE=cLqb-9AeTUgGYxx5EKin-RNG|58mnmu6zJjsC)S6fx=@UJG6vW zcIsCrB$*wZoH=H({eEj>J8@?ba- z;+Qu-fZOLR;N1y>R=#qLtf#Q}#uEKl7&H>e^evN};{^SiG~AG%O}1?PI8*Ahf;8R- z{aTsamkU0uh#H6bJ$E1E$jMyB6c{k$18{tV1dM(}mx=C0d}P&~JV@;yzCGXER4jhX zSDs0W*uMKZOkmcG?4@Q66uzjNKuRRGs0%d(#!i0Ck>%KtUza`dcV_e4g53wnJl!Mq zjJ@oQmQMDen9(DO_C4BNzmtC0?zM**m%Ez~gi5bsK{EzxO$IIXC9YMC^dJtEKD2r4 zyQo+&Ysd0XVK6C6(BI>XTPS{yzRNiHC?;x6jpt`DJI48^?vEQlCs13r0F!&kV!Em9 zhwSbAE>4=W{Q?CoIT{Z*&t-?m+FPRO$J?iRk*ojvPaOo5xrgTV)hLc_u#faJPMatD zwoHvibxzePM*G`M^$GTDD^BQJXxc~!Jl%Dl2#(J|DDt)RIN6c48dMrj^{!YerM59_ zcO%}~^Pi?LLfO;C@1w(13mBE#%peJ}e~`W?wgngr=@0h5tPDIzqWD&m{Q`mi0Vx7O?ol(MRg>P;^o)k{0QIq@>Umy>C0V8=bs>;6 z)3S)tvITI_Dt=iExU8Y1@0hpjqy*9=nq$NeK)RZ%%TZHd$6t0(Yxf{82B0 z*|*IVzm25v4IWt|{lK*2!L%ZFxP8ST^Ln*;F9gnSE`G7KSf4k$Ts;>rE-C=+Z_MKl zA`60H^5yW)5)lGF1A^}2w`3i5o|)EezxHTKBx4MBC~5^6P}T*$_Fx>B|M@SHZ|}b- z?fP(vu?6fKaBdI~x(jo~6qcsOmlx`EDtJA#H=jLg#9`5=~r{hiRG zq?&zp&>^A52DRh9ef*#^;+$XKA^5)?-kF0v86Tt*?WEZj#lhMoPm~fYDLw%p#V_%HH+OLG2DJ z%F*$^9WLQz7?K0HodXVK88D+uuG+Jj>9g^G+sB!;DcXqUgyjvU+i9Zv$LV!S)XQt( z`&yxk>HNVdd%`D0-&M4D`bpZXxlNqj`}Ft+nt}`Zx`(O!dur52vDrI;v6j5}DY5+T zM{?Zlqc3!c)XYO>?=6RG#k8}PT??uqcWnZS^iEj;67R6X1YAkEY z-Wp@bTfn(cYr6z(K<)ROzu$|?>D?VoXp9}ZAY!O+)uD;fG4sx+wPtAB?Bjd&rifR& z#BpGGAb;u2=l)e&Oi6I_%~wKh%OSAI@T0w7P;F!9NfK+m=P~f{Gt|4Pm3ZvC-JIfZ zUF5x=r5C=&EM$`t4XiKq!7%sfcq@<O8fv96Qy!E6H~e9$xDN@L_j-`5VsiGuJx zj%iC3uep*{1knvkNzGi%&b{Nv!*g9ReAVrK$ZWMERyqba+OVOS-nH#{O9X(0p9NL+ z(UFRCF$fJw4wny0kIIaV@d%IiOmMQ3@beXA50EjnPO1vYFQ|hwG=D5EX@RtV&Nb5X zF^bSgaLzAnXX)&i?ERA5RXn2A;kf!utXwTKzdsyy zMQL<6Mr9_GR6pc^q}v!Rm-Z;^Lz%Te6%SzRt=SaENKnjGbh&o3RF78S$bz^_38TWB zCl!^UJz8sqT4Z4Y6q*EMrYuS842rfKf~u;L;lhbcJ*u#4N_1gV3rk}i$eI-{rb^c{ z)OFPidas|*x$&F-nmhbr%YKZh(F=h?m7by>Hyw`0cv+ZSaj{S|4gBH*Wi_1$wqGBc z60W%ss5q`*=OZoOU&v-A%lhjrJ)hNt_%sV6<2|maB)F?wH;)7CSCx`QN}2p<2&Eu zQJh_M>0c4f3}oE_Z@>GevVAQR+2cnd=s)D;a2E1PmsGA;a(Exs=Fb6*4vh zQfn)avXYZfX-E2J2O}+;CHlC1s+c)X;XuC{_;uoL8?dPu*kqw?G#azPzJD~xcDObD z75%|Lm%vYy3_5JB$arK&LL;H1;G%2Uyk{NtyKqcn(9~#3qzAmY%-j+pMa}$pFi;;B za^-dA76df2K?^``S^ktb5o;ECAO%gt$p{&6s=8BOA&wH(H8vM2(dE%i35@E+@{0a5 zhzF5fy`%gU(Q|*&)GRo4Ed#hkg=G_MlBbkoRCGS;Ws z)wM28_t3K~a9CcmZCYAhx0_vk*0)7IU)Fb;Y{Ay~nHb7CjP5_g)QPKpWNW}S#Rb?# zxMadHhJS?CHVF9o;?|*#ba&wJD3n}YwUCN_EDwTS&M*d}%>OTCGdK)+5LZf-sY=6^ zcRp1UQyR?7_}1)Xlpqk1VG1Y@=R39r9|0U^&pR~ETM6f%Tjq8^^Pgr#Z+lti`uBiL z+-UQj6m_14cTIH_5;Qju|11UBYRi;fquRDD^M~3yl<}OpPLs8(_i5Rtwy^|YR@k<5 zx-JI5Yd7WjtXEfsKUFWikGuz4LDGmiCnkP7rXP0Brf6Lbp_Am?HTUc0oSkt? zHxPAj5gK&rPEX^zCcbQ=Z`i6DZ{9n}oCur`GSm@1k4Po9D7JmJe%`E1E@!zWa}&7m z4yxqWDo!JOH_@HlJojqX*;6iXLq)+J1WhW2crbV4)qgmWuH*EhS z{0yu9zR7*(F&EC$q%ZoX;r8-NW!_h@;m|!wbVW%$;h~N92my(8Ep^MSQhjh0$Ijb1 z4=V!qO>qCJj3E`Y`G=U0iLhA!GyP5KFUtQiK;ta_PIMSA}1~ou~Dr;jBK!l*ael7StW2 z@s?5wdXuKoGTlFAF>ob!c2-{-_oCy}qndxvgu8J!v$-TExZzROg>yqFCZqd5rUlEc zv8f8*r{i&0H2tiUKi71o&JSCBFfFOj)nm*kMJgMzJ*(2UWH*P5UK~G8Vr;=uHyI2o z<@|D=GNMXN?0ket`fJ8TY$4}8FERRW%3Im3Og-=7F`eBT2F)uxL4`Ps0313qPKzB5 z;J$DubP54Pdi$L#wO{IY|5o7dm_Yh%;6ui#o>mVQGY+_=B^BEH`4eP-S)Bb&69;7z z6IK>WwEcNpXG6(^w zuu1+6-@`PIT&GicSeT5b)-2{Kq?4>%=NQ}4C=FY;6!{vLD=sU=WOPVmL8POXwUI4W zjbCs+tR!Kz9?iQ^9ZO46UCOc?Dt=KM{0WY&(WfRIYvo|`t1?R5k=Pc){61R_H4}S* zH_;8uVc#`QESh=2smAMS@dt0tT5*p`mDb{@!A%od+8Ty;)fTCmW|tHx_*mrwJRQSc z$A3%>jjo6;Llwe1v+MF#>tp4&gK15>9uEF!7AiE23y;REp~%YqoQS&C0rXF3*rG2#>mJBg})GFka5|Jbufdlg_DvhDef zQ}BhwDi5Z(0?}mC3C}zptTJiBz=S(M=&v^$-p}@n~11^ z>8A%5ke1mlLiaKW-Sc%A*7+{(V&a$kTIPu1{GGUSb$%y(>0ct~zfSO*W?ug?d+6Qj zth!YHDB^XD$UYaRHjtxAJxBMWsy@aYZR&JUI<@*%rfRy6jr%bVUC|ar34bYDfHP2==}5JA9i(K)F11aqGc%*Rq;KxP zCQ4sN&cai3uryKwt8~HOI<(4=x64khr^-^K zW-cNn;mIyg*U{87q2%KqvoV9PLnOo0tS)9b0w%HH@znZ2+Z7Yim(pP>0T(YqiRnLqbSqNx3jgC!Bid!XWEp|?@SKQl@TJ=GWVHdsY$#8hWGZkpmn!HhtHkC z!j3sZJNJTZ!Im)0$EALyGU=vg)eIQ+49Kl(s%wERDy2@{xtUu@l*cP$SZjSC($UPe zz=eX952EI|qjRLtBE3L$PA-!W^Fy3c()B2IVq&uX+Z>*St@x>HNkW8EJgC6j2Av)h` z*4tA%Uf-aL>ZR>Ru!#2_An%nkk<-jQ(~M-fNIZCpH!Uh~4c+r#$F z9Zb~=BE&zq?;T;{-jVLAEfKZXrk8&PTi-9m->-{sr0Hw*~K*pd1g*pAhekXB9`^tGRwIr`7n!v zhfGFM_*=n^UoKZt^04x%tFQQ?lhK^74x>ed6ZjKTN~O4KStm<}k=E;j)}LWW6H1h2 zYMAv<>a1AOSh3XvQ`%%o>Vv=k7id^;Q-mh1#vC-LwK)hH9GdunBug0UBOv|HSNelt zM9YUT#k9h#;cu+`aH>3)V|6#O2FvfJk&9P8sl%>yR+*dZO1H2P+UlVpF9K)GE^QEy zq+}GPWAyexS_NG^H5w2Y$^&X2sTq(8p@gODu4m#Li~6i5@0QJ&ll{_{u@UTwtd?Cv?%w*<%;sjGY`1ci zuDzTncgw!g6JfY)dt4m1{T!?e8*4TQjeeAx+n~X8>+U)n=p9n1OT+XY;DaKTJqD)2L>BF0IvENp75TF#r1Bv)Lj%U5x_IZ5k`EoGKm0&wfX+}`FSwp#xP~v!V z1)Id_yPFOcchRc@`5mR!fN({Va_K`_( zZ*_qaH#_NDW1#6#jzMXGG<*V)Qwn_;nA0gq+&!EdIuD&TU*{)=A|w;~uplrj{N1s@ z<}S<#R1wFlOF2ZrJZjYqYr1?~6c$oDX%_4HD*|t*A>{yq3t#+~s*c^F@ohP!a0CK< zxb}S|YlvfL;!|nDa4vyKY3?wpsBkT5J@sf~E$Kk_=o*6bh=BS;iw5c4hMMC!Iiq)R zUB(Uq_mWFS)BV4QrV+6!?EmzeDRo<6$^Yu_(?l-F z=#$(rNq?ON3M!qAU}}!snu%g+iZ&Fp{6cILUvWDsH{ndRxF{=JUsW?)VRTh+%~2Td z2KOlDZP8!*>&BRTq?1C`p8HuObhq-n)u?{@tkf$|bj186P`S6yd%p;KU(Fi$E z*}}g*o@(ROT0gKx!jyBlDx8>EXjtC>j~IMBnNvfUO0&ZvF}-+-BYfy$P`hcU)s1QM ziPr%8J$v(hH2l}%MCr0Bl|gH%x+h)9X0v`q>bke4-ptkJ^AwK`l7UNOMXkjmb*KS$ z>ejR`$g;$cOYy&ndetW!v{$8V7OuXD+_2}5>;PSYPNcx?JBe^5wW~D3WT+mZx0MT} zKMrk38{gY5we=Xk@Lg@V{p{ZyGNiu^wL{Rd zun(O4ES1&r=l#grDZMi8S`xjS)}L};11a>zd>XzJjacM}K|(KHV;VyWx8FPH$=7Iv zAZ=kD6$OTEKzQu-*>Q++c5n_ifdv>eLGLau8A4d-;N<_rP1qC3`-MMa0={Kj3;G3j zuvhT72L-vGifIZ?VH(f5|0TX3rLq5Jy6@|@FWJ3k3aLq7Ys%1L%IGLYw{6ONZOZb` zloiE{jo6Hx*^EQjj8oZ+%gBt|(Tpd+j5ooI?^@v+f)0_Iu#$Wc+}&8{SPwsZpD$lT z`bgyOD{yp|ZLJ<&6vaG~b1S(NGU>k@H|Nyh7v9?ys%LB!z1ma;>m!_0bHppNzwU=7 z5*Au0M^Z4B0Tlq|16zQtelChTrB7R>+Jns zU=+8~n_xN%$<>_#46Io1e@D-BZzJ}B6eLK$dpg$E);HHbCzh1RQTUYn6Qj3uU8NV@nl zRk?F;yjg!Q-+y!|SwH;J$NHu7*4DAN$)e@XmKUBHfAv7r^!VNsxNnQmjR#GzJ`!hm29S_{8{!5h*}=|JhON5{IR5QvEOHomgR|J`F+D!= zZ_ckX(98V`+M?>&|CWtC3j^@!n6?H`k|LH;&($9Lxio%=p(E5q+r4J3JW1 zvkt3xxcWy1U+c`+S&Q>;N2T!B%$W|K{;)D>wRkazN(USK7mS~W_x4_njxUk0b6s@D zh=hVQSEgF#@pQ4y4i{Lntg#DPt;F^Y*^wfTJ5^m-EdDhSVkyRR*7_L?i|sCr1O^x} zwg}L~i0$o@20*y@EKq>sz?3_JBagrcGd7Z?>Yle4Y&bc?)@?&lomH(%TkY|`^=KLn zW2Fgl#A(s60i4QGHjR0#^}qp0b*Rq;PGJUnCvTEF`o#CN@OIfDEsq2#kIUZ;>FfQe)Gz6m z$VMQYW;310a@RvpQrGr_r7o!z+V{~EjPvM3Thb@uP~3(|*)S7hjo}QHM%G5>PNBng zXCWKF@@#{h2a$<1fHV4f)-tWWxyS+~{sO|qa0YH(QailJ;}=(7Xtlj7ZdlE^{Tjy! zg0a*^gg-hb_)NXKBPln71Dhw;pfR@LwvkpxSE%tz#POrOo2$Q1Kxoa>UL>yD!(RB? zd8oSU`DUM`J>Rozo(`0S^M)w^7 zJHR*i-HT+x&*O>fazMlm`%ar0ML~NIx-KW0$yQ@wm0OCNl>z70nY$`xDg&~FLP1@O z+AI1KEU>nfJIjEhm$TqUX^&VC-e!;v2$>S(#K?UbK*xIcN2&*kls>Q+wT)YVF_e)> zY1e)1GdBx=rF4vl_;QQr@=B-=(ga3JGmlFuyu^m%FCut4?J0wKX${g}o0z{pDP?!% zshBWrCVw(sf{^(c->VKP>;_WSZGfbUfew4UTOSj|SMI(6m7k5|0e_n!7V>`bfjcBH zyEtiw(=+iiUF9;j{}y(wy@A_M1r`-WNOMA!U_n4JArS7pLX~zf;zyFI0B4nADeI(2 zOFzb!kEgcQHZ6t;$DrX-c+0KLiTRmAB#WHYu>qzNN0Zu?!Lt23v|azY6Z7@)r(CQ~C!T{8Iry5v-`1O=oFEfj;n=Q1}|J>`Rx`9O@d{sQ4~eM>@U z>%CX({;`|Oq>u$99ykzKiFb%>@Tr?%F1tq)L@a0Ws|KwIw(L)?qvcwJ25PV!akkae=g)<}k?O zwg0!n2vWqa1boH!-Kkrzag?FcTR-CHcjMJRMiRGcr)}JC^%l%-Yz+r&bQzSFLD!-Y zy5uMz2MBH-OR=WEel6J_t;yTasqB``Xr!XSEc$Y_ZCX2_8U$7VZ3@ccZaC$bbVR!bV+@Qvb+b8!NJm)pdxl>`YWlYjSfxuIRS{Kog6e5b*=-&OWqVwhK z#L)=KQO|B}a^$ZzPXsZL^H7mdznH~x1~;#%@NAAKlTNLUE~mJ5!)}=HrLg~`eccp? zkHu)W`Smv13x9b09X)Suv9G|@RBOIZ(TArg2p5b>P(dGh9Bp3wO2aCt6wkGW%fbG8 zewL}K{;cmzGSKSE?gq_cm9cxDy(Px^m+~y3Xd}Mh6oqN|?5Ue+mYqg%heJSN60rco zi7c6J&r4E*qr=0d<`m}y#U8n|tX30E8G8#=3f2<`jUVHsIE%1#r722rIOKvYDaUO* zSw?qOBAzdP3V4mHB?->~CWF78V!DeYV#Kf$`4Kxdv=iH`XQ-?Qv z8zD=A>>#TH4JcDsY<~napZ|6##zh@f$&hamE!Fv4LAh~}7!HfuP#%R?4H`UamQCv3 zRKAuDXTX^`02a0x5HNC2_BC8wtr)T)nM6*^Hchb+9cl5A>3j(@hMrk?R6kl}CKftIqfQcBglr2Wz9tQwZYIv^$I3mh{1 zHzQLSRs(m=n{+Ky>0(cXsMrUlR$rpx4$NBcE|feIS!75oy^x8Y*^+H+956W;`s}}U z)R2f}H(&8#c=&vTsahY;xZ15fViHk>ZFBH88A#k30>>SG-x$Yr!Kjp&Mkfn(mu%FC zlUW}k=ygj|30+GnIWIB2w70xozj(76;e(P zqQH10^>hh$i{?ODC@j>a-`SQN#D|>G>{g6>yvlYuSyhL$>aopUM@Wc_lEAjDI4xEB zlQUHzd~)gNM4gzmi>Ne($~J#JeqoG&2JFI3SUeu9X*ym}A<*(rd-!K*yH~DkX z)Zra2zo`Q?i74 z@|L_}MsiUDm(FzxhQx47+DSoF$7ry9vi!r+^1~I1La3$)4V}zm;`9V+{+h~Mc&Qi+ zhg3B=TBpQo*eMmF_D6pjstETrR@Iu)pnHXle>&Mv3P-Y#46{O$RNwZxl|SJE-B(1D z+%SQ^3641OUw4ydxOu~mCYTynru>w>Z3W_WJQeVvsx=9Gov$9a4_a9H_{MP{T{EHJb5ezIZQH zwZupj@!b%iI5Qjgi4A2?bSrvPN{^~mw`j$ti3D{~Tj!=+sZmHn3;4^(R@w%5k_&(8 z3x%yG6gD1@KE3#ec)a}Cg#wyUQmF;A4AKT=Uecq;rdLGDT&-M^Yec(PiyJOtCp_3F~e=?1F)_x9bNua`LRa!1eSZ zmK8e7Elbm$*7RASbXDOD0)4Qn@Rd5{w@1%KzE9HQJcvac4gBq@KH8=^xya4J)XSWt z=c3F@_3h5tgdxVG?1(BY8r1}gZf4fY7(DsW_Y!wUW&(QO9RPn7NKVdF+A#NR2Mm*} z-7`5v;N_257Pi*$E7W$T7r+p{J#a(>-I2gFNgw}@OQaDN*4kMmeX91FJpUoEu>n=E+{rxobuN0( zbH=UvNR;M;n7orMjC?|%yBPX`Arkj6a7L1R4wXFQzXg;`rPC?~W0vym)C1l$tWqgD ziPzl3`1J907423Vv_TKWOSIu9 zVQ)v3h^|6`a;$vd(Fu!)M8?rC=@SXzJ7(-;dNN5J$ z^%?vGfvhkHkKauIZ(;GO3)ro*P_FUcZulWdiJ5fsEXt6@QJaZTWZCA_@z72`+!Z8D zsSN*$>}U#8aXjSSJu+EPrZS>aOk#+i+J7|=U)+ca5NycH+T~y3mMjV&l6~Xdl})Ay zG!KyUu5IrfAPYKPqYG)fe=1R1zdP>VO>TpuCGtnbadnU*oX(#;g9-_HA5!C6$&-6} zUQNtx=UpKSaXXTX#;IzQ`F{~S-8x#|uy(9@c3@H^%S+CL;pm`Ru)LV81^Hbkz?EAyjt%#Lmp$FlT%-aP_eYGDOmmw?5iGH6!e z8p8PAXDgU9LN^!|2rM217-l{J{unrE6}=9c2;9Ksi*%7foaa0mAT!E~v9EaDW}7Ua zcllZ&S5pDcf1hLANK*+5SUx@9yArXd`>?=w794PJ`Y&E%>5NZZx3DT2o+*DH}6%vfD-O8b?H+HepJ1e&U2IprXHK z^<8tEUo#vrHlFAj1gWXPiRM|zsc-#a`&r1x?YMmK%yNL(yGX&@B)gK7%)w=_q z@c(;H{Tz}LoiCK&ig+2F!}{=+ALg$I<7KCRyMITQD-jk;G#~ip>H}&m&h%q0m*)Ll zM;T0$OPfi{&wE789w)WF+Du1OWvg#XScpkWMzj6Dna z(9K>v-`D*?xy`|JsYj6adCjCnanec^S+as&q^iAN4?GYnzHC&&c+L&CHicg}2z^@; zbCgShNk_5=ujGg!K84OmStB^9<#eH&%&t768ED3}?#Axcp;{7tqXlDor-drtmxt>a z8?+&(9DxnPkd3rt8*K0z?HYIjK^?S23^leaT4{CVDg|d}hT{-82J{J~ zd3g#dFK3HZWeN%&9?|(TbL=D4XtVRreJuj5tNmCR$I!|Y^;5MwY;_) zb400~U_?CY$~-5hd8leXaBXlr$@mc7*kp6u2P6{>S|5ja3n$W!zs%dQRAr@rp>aA0 zR}KNQBi#SyU?-qn78x83MO>E8!*RUw%)HKfJ%adXurhDqh)ohPeN&{`89QLP2(UR( zCD)J1V2*w~UxzJJE-g{6LY>2<2$2(mBuyXyrz_SQxH$U9QO57Y_MBT@4aPs`+22$# z-F53RaQ#Pd3)xH7zD|Aa&$*-$LqyNUxdu4@^Vi?yi0FS^=;2{tnbS%9e$|3x?qLl_ zO=vCO4<}ax8L^NwU6uWUJB1t~EStfHhLwkv8=}C!e^c!JL!KEAxfhz1`a|SmA^*$~ zym=_!oz#~NSvmD9M`|OyQm7NlPE{^lSS7(SKN0ffFbDaz)Nb4@#M{2L(f8bzDw8ty zk!*bx-m4Jstj(@KSdsuBFW+B|fs9vTc$tn%gIm0c_m>gjiB#Y=@F|NSi_vbM8(#_% zY<8sg>~vPY<@(gtuZKHobwV>UitBw9-NorVGh1xC5&`SR$@%wwarkhz=fMIrR2(hN z`I6l`^xEaK7=bdaNDQq76RY*lIsZ`tst7dZV6y{M7pCqklXBkDNe72L-`g z&6j@cnB8Z6vahKM+d|zR$tS0n41@oKZD_p;HDD7q-32Rvi-%s10&Ob?zCjxHJNK6G z%pie0$qgNC82qr_!&@07VO*=Kw=JhT?U zZ&P@e0xokfGdk(L+*c>|1y6}|iq6D`Qf_=(mEREburSX$)P>xQrQdv(8bI__IVE6l zsAy@5I7;NbR^3QPu{qHxsFi(m2TfljzU)|jFbd_N3$$a*N29BM^-P5dw5O>cTVllE z>mNXxCFgHwJn>@C`L13#k2&$xVS+gGe|`s#$ySM=j6>zeQ(D=D{zCGSTUBP*_Z<&c zA+GM~#xMinAo^{T5?RW~ulN1t7$pg~)ezxT>iPU%b)9uk9NV_Wk>C!&2X_drg9nG; zI!GW41a}MW?gSVlxJz(%cZUFh;GV(V0z6LL``$Tq>%QI9U0vPvTdS+~KfP-2^?h7G zPX^2fo0V-jgPU0`LJR?z}r=&rkoYHDvS?hI+uh>9#uD z3Gr%)$HE8oyLat`K`o-mbK|RSLYaCVVB-|ydV?&H&nZe%^HdH+TJHAxX*tGQ ze7RB>@J2M?k4!|YP+!MHV8$pOqd(15uJFM84?N=)lM$&^Y?_9sU7J}i+uGogwFn7= zI|sR2vw_hcS!XV1ryrHdf(BrR>VJQaN3KoAs?dI5(upp#%F;a`gHMdttt4f7DbQW5 zNN^)gGX6Yyr6i8oLcafl0#%AFBzH@C!pIAE@v#HO(`&s8TDn;37xv^(Z(J(q+Dyeg759QQm_j^$~^J@F35neEfheZ7B zyjqNsrS(;UUP@hs`3$H0QT8wo_ZCv~#a=13&*cfVan~egCeJg-s*J4AOS{K|h%B^w zG1P>iM6NmTUH?fvzL~j>t+D~Ah?gkbg|)nu++sC=;sNZICZ|!SQmoMqlH?M8@_F~^ z5=c!BFcCkG3$>QOCjXT2#;{QTolWSp4m?ZHR##M2A!F?tWjF8O>|5bon`P~BhX!QV z8XkZ~eUeX3EQLCa_V>K{{<9Q(Y-7s;7kD*9B^KArpBb3t?P{@ma%i^OQj@WMmAzwl zD2CH9gfSG{L%}l#pL0z@IOlepD`1LQu0PgQkfptO>L<^oI~1;X*_SX=&A7b(uKcYn zV53xCM%Vz@8@|EB#_kvYnJ#=*r%n8mfV@px@!>_^6Di%L>*#&Ob!K~77|xb4BQHjk z(6YGA?CNe26pTCIP4Z18J6o?78iwWB>nJRO8{e!-DX2i=XwpyPnR~e+WPcbsNsU%*4lv z8h36c6)rTy`-nb-9-*55&a%8Ts zBq|S<_sh}1i20vR!~_Izwo*@ktYJoW)={T~xKZXLN&uGY@k(g@3t&1EI>&eYc3Wt= zcekln#Z7-WQU=@yF;2!HJGe0~R(b9F{jD@k+qglyn9JnjW~C9iK;dlzGAm#)U}aYN z2_iYVY_=5fFQE!^kc>3LaX+Y{)c2qjxPeu3V3kJtdf_}kW-vM{Xqm~+i z1(iF)>R8#dr0ck_T0h>5mCp`_2NAtr)Os(|pjb((nn%X0V%=f>K2E4JiQwJMgQjB_ zeA*>I_$!|e?m9iUSyh+{4%6(K;f=GF0!OM`gkUKxom=k>?;TZaLI}#c+(Abhy_#rz z*D-gaG@;GW} zGp>mm7kMEuq0wQ|F$xOpfySbPl&-Y=nV<}?vMeJ}3$EUMC-s zB8+M|dQEy!)LAik2elz2=*+0yvo<95g}nKPqzt#7=Y+-=nGSTOcp5)LVO5Tq>PIz+ znV`Fje)R93yNR#s+w>+KmsWA3DZA-Hair3;{Pmk@=z(zHZN!EJ2g=SXU_4byLFiW& zTDJU!e$$!>CJ4*NuK{Qu#`EK&+$I1$Yyv-Bj1A^uXd$~iQ?2_$hjwm%E@Or}pC6tc z7}DClZLc*D4V{`ADrYIJ6I%CjRDR4>Y8*rQ8nx~423Qq#i{as1TO7vEKqsq<5S)8) zUm20!$3J2{ldSn|P>;k~PiHws7UrABkMx%2)wOc{0%?gNrZ8%Ci`PHi9BW^@>`0OA zE6QRY_B8~P_8}w3a#;JtPpmb%A2_5=U(HM2k(B;|W4<^OI!;(fBW!Zfxr@ZMb=Cg)t-$-w^Z*rbs~KytgMe$ zK?<6FA1dVI&((}gs+jq@rk0gO*@e#6|AsWP*IXoq_Ld7v4!Sw~OLO;BSKttLT8JCD z4aU@RNZg$wR?dHWm9zW?Qz%Z%@=G%mV%%TPyLM=7Cc#7ElDM2T%ouQItK2MO(O-AK z&%d7C)ynt5X(*Qu_a}<3T|Om!=UQ!vG$iBW7O~@+TNm0r79cDbf~vCJbhdm4;%Inn z(yAX%{E%GW#*1r3KO<|(df;1A?v6B>=A)6JaR()8g1R`E%t&ha3i;2F@4W~(W{XK? zZ!%Rg5&W*5P7FwCXQ5}G@u)ealZi*DE1zxBxbI4;X{OQT)13#PJ%+y2Sv{K`072y6 z9cj{!ntBGf&k0EFwDD4^#EE!CK4$pD?5abzv2~0%PIA6-o(_*K6340Qd8+hocN~=S zV9X)otM5j&8OTw8VD>=J?4#?qW^5X95zb|+ih9SpQJPNr;; z%eiJr)lE+ zl8B@BP|f30gD3>8v;e_Y$xpr2Ku4uKF0K4vF><~geQ&Ur$yzS;upHJz!#0C=5D=S` zc=Q*0;I<5@unYa!nV_vHD}e4MpNBp04G|YaVG1_+Yy`@c*Tjc=s_>reMvsPI-&x3j zVSJyrY~43tp@CF6wbjVa&vAU+sdkC5PgXDkS223TDbCbw2uG(T=K0cFUF45LC(rZ7rG4-ci~bI)@BzyetSuM1!`_!Ds_)+u)cPH#ch2cRnf# zj>$n}9L(4?C5#3cL6Qr5g1tKtt4uLA<~uX#*Y{jmbEOt@ML$h(y7wU~Y0hB{U;Ll zRCC>HM_ndV_$V`!I9AtXdO%bduM;#C{y+#v?=$KmY%R685NRul0Ruzv>PU$2 zs^(^631%}X)U|ac<;8xsF}uTpGYijbuFMR6YY`xyS?^*YFRzZw5ub2ss-JlIJN^Vr z8u~I>$D;ei7p3n*ZbQXf<<0fd$JOnp+jYFht?Tmrj@)L7D@;1y$A%eogY<;j!e)gc z?o3GgGPxUKwvQXFFY~qgJ6|p|$IpYi2J)mRRaf7KlTtytimqEyMY7tj`av=A@?f)& z@pF^1;QB&kt^uhlmGXJd>*MR)fu*+1>+&f3f$I==XGb?SJ5R@`<}7HsiSa~-aJYqG~ANHUeb>B z8HjLxMlq<8|L}R&amrsM=@l3*0)Z$o~?JVH0DOL4{4MUK8%CIJ8cYW?quOG4D3X5GL7Nox8^V6R zM^}7{#8)g$4+y|C8J9}#g(l&?XGH}OA)Uk&u3ipu3!2kyULCN87vm16hj;wqlpq>y z5b{!^TT|4lqcLDtxJ@9B!cym@C$d~$!(?A;7a=oTUvoQ?`!43?<9UA}EWG4?b=~$5 zp}Ig_Z)jgesHq}`y|v61v>_)+!ReJxixX!?ysO8)bjZn)-1p~>pzExdP)MbgS!+wz z%E12Nvopf7{dZdW#n8n(ZVB~pt&$ieNE$HWGC>E8MExL?D03|1)^Tfw4fW2gIALkC zy54xX`{3aZ^kKeMP5)^?&2z=G zojvOVVKb-q1-V69%7W=z3R^a`Obi*F{q>Hh=&!5Ml^X)d45NXKMcy7Bg5R0ul}A%@ zeff5NDn{~OC{qz*uaq~3iqQNSf)g$qG(mOZrK*Cp^ySgQ&=S?THr3-gQr_+0Klx^F zXVe~2j%!WiMHE$we#Tq+9sD6hgH2mYm$b!z097HcT~H(!nyyH-+P1k^oT9Ss7biCG z{3I30E+zB_dY8ZaG+^1aej4e!Zz(wh6pUkH*wCzr$3#vkr20%;0hIL*o}N@|y$LS% z?0n}#XKjaxK9Q;#EXivWf~~WJgERjiC6fA`H28oI(*iZB)^lK904CC@Mnbkr-A8)d znQ7Ov7kOl-G&w^WMpAPi2NinBmW7fRh^m2J-=EjWNxDYPox|dya^1L#?3%s1w7_3B z8w1DlHs);I{I09xd}*b(_HvB~&;t@coX@Lmq4^=}Pa@zXyFZUV6eowiH?uMJ-D>G1 zM!89)NGoIQA*ivwEF(Q)>@r2Cx3)V;U#Dy*+Wi^2#TG#YdD|z-7x(E(N?6 z`*WtyMCD;f2s4%RTW#~lH^X{kw}??J2H~-Y4cJ()se~vbBBg~2O$F2z(dwBL7+FX0 z%)I!$d&aNp7PMn&*UPkkfp?&{byQ>LVi1H_OOQn>lRs*nk$%I1JEAdH@?B%{Mr3vD zmLd>Sj$P@<=23jSn+a}b-2*E962D^+!Uikn#?cM$$v2oisR4U$po{;u?BR>6ejZu^ zN(>e};B)Y|_spWX2wT~YU8)<>6KnX459EFfX~ZMZ-+18Yk*uHx@=YX%5)alxdiUNq zofG{pE$U49XynbfPv}l+$Kq)vHA6D63GpTcMPY3VgmCu+A;KvmNshIZ9X4iSINjru zHq;f8V?z#OPPls~+|wtCsq{LEQ{U3Ks?1V_&snPbAux+-KS=zkD#U)*2*h%U8lfgp z>3+5lOF9(?(Ck<-qnb=$TEp1iVcpUT>)-+)Z~rJ$fqc*aaP}+~V3a#*IP>F8u|=w@ zq+*V>Ak0=xVoSXxPz$L<1dyP}adfUlEK4BdCss%TsWtXSDaMnRC2B&cV}$EBmNtwM zB_J5~49ZnoS&C0CysEwLRmphx&~FzUCdG&&5f&|^P3P+fUs|!fIrvEWsCiP3Z-BQC z(v@-b&UlkjNlgxqw;OCv+I%@4-IBjc7Xv01Ql9!mq3|p<`$JW`r}H=>!x8X{V{gO# z%9e~uH;kkc8Nci+lCWLs3hwoII$(s{Ou>eMoD`O@AbQzhY&Y4|=RS#vpu?wLKW+Yt z5e>qOFjvl^;qm5v&-V~s%Vb8m(9{8r=$U=Hv0pPvey1lytuw1w8yD4=^&#FgoegIK z4qif=rlya(DO+=slEPC~Sp|n;ruUqZ4(753Ybz`5(qCpyrm=3!jtbT7{D`Pv@kwY* z8BN;B9m4OVrnt&9{-g=ppc<#$c~Qger+?4OLB*JU%YoO-#bDE|3qmPE=r_j)tqt8| z;^McV_65HWiP!F@RxSc)Q2DfTELU{by{Kl@vAUd~Xk)I6!|ovzTF0+qRaEhxxd|Ve zky5ZPh-ly=`4Y-RfZB;(*BXtaSa4)2xEU}@8I zuc^mTPC7F;_IHC$dGThWm?Sw-f(y@603S|~?6`j-l)|ZxyG#x&1}&^0w>F_9CAqk4 z!e}3m9kTfbpvj4XAXXI=R?dVYzXK2pTJBKTG5hPx^E$){0IuNteu)rDG^A>Rl}P(V z4xHt1aS0j{AyiSlNcfrq)sS5wLAz{;Z+WMZDg(;rQ~+B}om{efTtSKOK6N7&qm*7c z+Bv7`HyoyLv37jo7D?3VuFKXlbw}bnjF>ZLtg);XM+ zpa{uk$t?Gx^?apbHu)hjCZcV~7)J|up&U1Q4(VDv>=7?{j?*sI>Vj)oNqOntO-!iK z=-%Q~i!j(ud2>#3#08(H3pm*Bwlbn7$_J0mB6(P3tXZU7^&>2*oj#4J8axRFmTKQ3 zhpsa-*UaMYpxOmBa)I3skdnJn-tbbS0a)DY68B;RWpj(z;zA-^lxX*JkaY8$9L_Yk z5&c?Kd6`6C9WsX;ns89!ucPa39R!GiFSG}Nafv9qZNXAGzlxyQ*D7#Y70FDW8=Y@w zJYFK!C!{||laM5@%RBfA9@y8)QtG7zXROG(qH2-nsdFs;ZZcP`KnkDj!KLqJifSmt&{Juh5hqR({&RkH5 zd%m4LTEX)-q2WV_JAsT5uHXADqfbk4Yq!b#`y7h z4PvV}W2o$yP2QG$JqZqwcCnrGnThtHG^~Oa=Ii*3(O%xi@|rT6QMhxrj;rnKsPaRN z($`AqJkHmHKh@Q+wfE5TaOIyZSp8`UrLH1H4y5^>1_B-;GX_Ze%Btog`JR1CZ2%O` zG(K&jkubJCfAqi7a7lHNK&o!F^c)D?mO48%wBaSO{@iE*m z3kN7)OBGHIM7!6A)?9R|o}a4SX_w!?;+l;Ql2u*4K(6kL6dw9CbvtcF=JWobVzS%< z(th;@-9q6rH2E{1{5P)Kdb?o$F0ekuT1jmc(QVSc7FLX}=U)YuI~&;8g+*aPi%~^c zdwOC*ZFod+_QM{t%B0#fFAUnj{?DQv!l3?^*D$bfV(@QYz2lK#z^{S4{Ry+YNnl{; z>0w}ArMLe*DE(go{<>9^mtd0yN&gcnK>?6PAU!>sy^3}By|!iiWjOz@@fVc)8cK{GaLmn-=unn2^N(V*iotzjc=U zjnP`c!2I23^3SjQZ$1} F^FJ0kcbEVG literal 0 HcmV?d00001 diff --git a/16/tweak16/XINTRO/lib.c b/16/tweak16/XINTRO/lib.c new file mode 100755 index 00000000..ac261a07 --- /dev/null +++ b/16/tweak16/XINTRO/lib.c @@ -0,0 +1,352 @@ +/* + * LIB.C v1.2a + * + * by Robert Schmidt + * (C)1993 Ztiff Zox Softwear + * + * Simple graphics library to accompany the article + * + * INTRODUCTION TO MODE X. + * + * This library provides the basic functions for initializing and using + * unchained (planar) 256-color VGA modes. Currently supported are: + * + * - 320x200 + * - 320x240 + * + * Functions are provided for: + * + * - initializing one of the available modes + * - setting the start address of the VGA refresh data + * - setting active and visible display pages + * - writing and reading a single pixel to/from video memory + * + * The library is provided as a demonstration only, and is not claimed + * to be particularly efficient or suited for any purpose. It has only + * been tested with Borland C++ 3.1 by the author. Comments on success + * or disaster with other compilers are welcome. + * + * This file is public domain. Do with it whatever you'd like, but + * please don't distribute it without the article. + * + * Thanks go out to various helpful netters who spotted the 0xE7 bug + * in the set320x240x256() function! + * + * modified by sparky4 so it can be compiled in open watcom ^^ + */ + + +/* + * We 'require' a large data model simply to get rid of explicit 'far' + * pointers and compiler specific '_fmemset()' functions and the likes. + */ + +#if !defined(__COMPACT__) +# if !defined(__LARGE__) +# if !defined(__HUGE__) +# error Large data model required! Try compiling with 'bcc -ml lib.c'. +# endif +# endif +#endif + +#include +#include +#include + +/* + * Comment out the following #define if you don't want the testing main() + * to be included. + */ + +#define TESTING + +/* + * Define the port addresses of some VGA registers. + */ + +#define CRTC_ADDR 0x3d4 /* Base port of the CRT Controller (color) */ + +#define SEQU_ADDR 0x3c4 /* Base port of the Sequencer */ +#define GRAC_ADDR 0x3ce /* Base port of the Graphics Controller */ + + +/* + * Make a far pointer to the VGA graphics buffer segment. Your compiler + * might not have the MK_FP macro, but you'll figure something out. + */ + +typedef unsigned char UCHAR; +UCHAR *vga = (UCHAR *) MK_FP(0xA000, 0); + +/* + * width and height should specify the mode dimensions. widthBytes + * specify the width of a line in addressable bytes. + */ + +unsigned width, height, widthBytes; + +/* + * actStart specifies the start of the page being accessed by + * drawing operations. visStart specifies the contents of the Screen + * Start register, i.e. the start of the visible page. + */ + +unsigned actStart, visStart; + +/* + * set320x200x256_X() + * sets mode 13h, then turns it into an unchained (planar), 4-page + * 320x200x256 mode. + */ + +void set320x200x256_X(void) + { + + union REGS r; + + /* Set VGA BIOS mode 13h: */ + + r.x.ax = 0x0013; + int86(0x10, &r, &r); + + /* Turn off the Chain-4 bit (bit 3 at index 4, port 0x3c4): */ + + outpw(SEQU_ADDR, 0x0604); + + /* Turn off word mode, by setting the Mode Control register + of the CRT Controller (index 0x17, port 0x3d4): */ + + outpw(CRTC_ADDR, 0xE317); + + /* Turn off doubleword mode, by setting the Underline Location + register (index 0x14, port 0x3d4): */ + + outpw(CRTC_ADDR, 0x0014); + + /* Clear entire video memory, by selecting all four planes, then + writing 0 to entire segment. */ + + outpw(SEQU_ADDR, 0x0F02); + memset(vga+1, 0, 0xffff); /* stupid size_t exactly 1 too small */ + vga[0] = 0; + + /* Update the global variables to reflect dimensions of this + mode. This is needed by most future drawing operations. */ + + width = 320; + height = 200; + + /* Each byte addresses four pixels, so the width of a scan line + in *bytes* is one fourth of the number of pixels on a line. */ + + widthBytes = width / 4; + + /* By default we want screen refreshing and drawing operations + to be based at offset 0 in the video segment. */ + + actStart = visStart = 0; + + } + +/* + * setActiveStart() tells our graphics operations which address in video + * memory should be considered the top left corner. + */ + +void setActiveStart(unsigned offset) + { + actStart = offset; + } + +/* + * setVisibleStart() tells the VGA from which byte to fetch the first + * pixel when starting refresh at the top of the screen. This version + * won't look very well in time critical situations (games for + * instance) as the register outputs are not synchronized with the + * screen refresh. This refresh might start when the high byte is + * set, but before the low byte is set, which produces a bad flicker. + */ + +void setVisibleStart(unsigned offset) + { + visStart = offset; + outpw(CRTC_ADDR, 0x0C); /* set high byte */ + outpw(CRTC_ADDR+1, visStart >> 8); + outpw(CRTC_ADDR, 0x0D); /* set low byte */ + outpw(CRTC_ADDR+1, visStart & 0xff); + } + +/* + * setXXXPage() sets the specified page by multiplying the page number + * with the size of one page at the current resolution, then handing the + * resulting offset value over to the corresponding setXXXStart() + * function. The first page is number 0. + */ + +void setActivePage(int page) + { + setActiveStart(page * widthBytes * height); + } + +void setVisiblePage(int page) + { + setVisibleStart(page * widthBytes * height); + } + +void putPixel_X(int x, int y, UCHAR color) + { + + /* Each address accesses four neighboring pixels, so set + Write Plane Enable according to which pixel we want + to modify. The plane is determined by the two least + significant bits of the x-coordinate: */ + + outp(0x3c4, 0x02); + outp(0x3c5, 0x01 << (x & 3)); + + /* The offset of the pixel into the video segment is + offset = (width * y + x) / 4, and write the given + color to the plane we selected above. Heed the active + page start selection. */ + + vga[(unsigned)(widthBytes * y) + (x / 4) + actStart] = color; + + } + +UCHAR getPixel_X(int x, int y) + { + + /* Select the plane from which we must read the pixel color: */ + + outpw(GRAC_ADDR, 0x04); + outpw(GRAC_ADDR+1, x & 3); + + return vga[(unsigned)(widthBytes * y) + (x / 4) + actStart]; + + } + +void set320x240x256_X(void) + { + + /* Set the unchained version of mode 13h: */ + + set320x200x256_X(); + + /* Modify the vertical sync polarity bits in the Misc. Output + Register to achieve square aspect ratio: */ + + outp(0x3C2, 0xE3); + + /* Modify the vertical timing registers to reflect the increased + vertical resolution, and to center the image as good as + possible: */ + + outpw(0x3D4, 0x2C11); /* turn off write protect */ + outpw(0x3D4, 0x0D06); /* vertical total */ + outpw(0x3D4, 0x3E07); /* overflow register */ + outpw(0x3D4, 0xEA10); /* vertical retrace start */ + outpw(0x3D4, 0xAC11); /* vertical retrace end AND wr.prot */ + outpw(0x3D4, 0xDF12); /* vertical display enable end */ + outpw(0x3D4, 0xE715); /* start vertical blanking */ + outpw(0x3D4, 0x0616); /* end vertical blanking */ + + /* Update mode info, so future operations are aware of the + resolution */ + + height = 240; + + } + + + +/* + * The library testing routines follows below. + */ + + +#ifdef TESTING + +#include +#include + +void set80x25(void) + { + union REGS r; + r.x.ax = 0x0003; + int86(0x10, &r, &r); + } + +void doTest(void) + { + int p, x, y, pages; + + /* This is the way to calculate the number of pages available. */ + + pages = 65536L/(widthBytes*height); + + for (p = 0; p < pages; ++p) + { + setActivePage(p); + + /* On each page draw a single colored border, and dump the palette + onto a small square about the middle of the page. */ + + for (x = 0; x <= width; ++x) + { + putPixel_X(x, 0, p+1); + putPixel_X(x, height-1, p+1); + } + + for (y = 0; y <= height; ++y) + { + putPixel_X(0, y, p+1); + putPixel_X(width-1, y, p+1); + } + + for (x = 0; x < 16; ++x) + for (y = 0; y < 16; ++y) + putPixel_X(x+(p+3)*16, y+(p+3)*16, x + y*16); + + } + + /* Each pages will now contain a different image. Let the user cycle + through all the pages by pressing a key. */ + + for (p = 0; p < pages; ++p) + { + setVisiblePage(p); + getch(); + } + + } + + +/* + * Library test (program) entry point. + */ + +int main(void) + { +// puts("First, have a look at the 320x200 mode. I will draw some rubbish"); +// puts("on all of the four pages, then let you cycle through them by"); +// puts("hitting a key on each page."); +// puts("Press a key when ready..."); +// getch(); + +// set320x200x256_X(); +// doTest(); + +// set80x25(); +// puts("Then, check out Mode X, 320x240 with 3 (and a half) pages."); +// puts("Press a key when ready..."); +// getch(); + + set320x240x256_X(); + doTest(); + + set80x25(); + puts("Where to next? It's your move!"); + return 0; + } + +#endif diff --git a/16/tweak16/XINTRO/x.bat b/16/tweak16/XINTRO/x.bat new file mode 100755 index 00000000..cd011b0c --- /dev/null +++ b/16/tweak16/XINTRO/x.bat @@ -0,0 +1,2 @@ +rem wcc -ml lib.c +wcl -0 -ml /l=dos lib -- 2.39.5