16/dosbox_0.74_mod.diff

   1 diff -Nru src_old/hardware/adlib.cpp src/hardware/adlib.cpp
   2 --- src_old/hardware/adlib.cpp  2010-05-10 17:43:54 +0000
   3 +++ src/hardware/adlib.cpp      2012-06-29 20:17:08 +0000
   4 @@ -150,6 +150,7 @@
   5         bool    doneOpl3;
   6         bool    doneDualOpl2;
   7
   8 +       Mode mode;
   9         RegisterCache* cache;
  10
  11         void MakeEntry( Bit8u reg, Bit8u& raw ) {
  12 @@ -162,9 +163,10 @@
  13                 memset( ToReg, 0xff, sizeof ( ToReg ) );
  14                 memset( ToRaw, 0xff, sizeof ( ToRaw ) );
  15                 //Select the entries that are valid and the index is the mapping to the index entry
  16 -               MakeEntry( 0x01, index );                                       //0x01: Waveform select
  17 -               MakeEntry( 0x04, index );                                       //104: Four-Operator Enable
  18 +               // Note by Valley Bell: Moved 05 to the very beginning for correct OPL3 initialization.
  19                 MakeEntry( 0x05, index );                                       //105: OPL3 Mode Enable
  20 +               MakeEntry( 0x04, index );                                       //104: Four-Operator Enable
  21 +               MakeEntry( 0x01, index );                                       //01: Waveform select
  22                 MakeEntry( 0x08, index );                                       //08: CSW / NOTE-SEL
  23                 MakeEntry( 0xbd, index );                                       //BD: Tremolo Depth / Vibrato Depth / Percussion Mode / BD/SD/TT/CY/HH On
  24                 //Add the 32 byte range that hold the 18 operators
  25 @@ -209,13 +211,29 @@
  26                         Although you could pretty much just stick to always doing opl3 on the player side
  27                 */
  28                 //Enabling opl3 4op modes will make us go into opl3 mode
  29 -               if ( header.hardware != HW_OPL3 && regFull == 0x104 && val && (*cache)[0x105] ) {
  30 +               /*if ( header.hardware != HW_OPL3 && regFull == 0x104 && val && (*cache)[0x105] ) {
  31                         header.hardware = HW_OPL3;
  32 -               }
  33 -               //Writing a keyon to a 2nd address enables dual opl2 otherwise
  34 -               //Maybe also check for rhythm
  35 -               if ( header.hardware == HW_OPL2 && regFull >= 0x1b0 && regFull <=0x1b8 && val ) {
  36 -                       header.hardware = HW_DUALOPL2;
  37 +               } */
  38 +               if (mode == MODE_OPL3)
  39 +               {
  40 +                       // Valley Bell: OPL3 Mode should be enabled by 0x105 bit 0
  41 +                       // else there will be no stereo sound
  42 +                       if ( header.hardware != HW_OPL3 && regFull == 0x105 && (val & 0x01) ) {
  43 +                               header.hardware = HW_OPL3;
  44 +                       }
  45 +               }
  46 +               else if (mode == MODE_DUALOPL2)
  47 +               {
  48 +                       //Writing a keyon to a 2nd address enables dual opl2 otherwise
  49 +                       //Maybe also check for rhythm
  50 +                       if ( header.hardware == HW_OPL2 && regFull >= 0x1b0 && regFull <= 0x1b8 && val ) {
  51 +                               header.hardware = HW_DUALOPL2;
  52 +                       }
  53 +               }
  54 +               else if (mode == MODE_OPL2)
  55 +               {
  56 +                       if (regFull & 0x100)
  57 +                               return;
  58                 }
  59                 Bit8u raw = ToRaw[ regMask ];
  60                 if ( raw == 0xff )
  61 @@ -227,10 +245,10 @@
  62         void WriteCache( void  ) {
  63                 Bitu i, val;
  64                 /* Check the registers to add */
  65 -               for (i=0;i<256;i++) {
  66 +               /*for (i=0;i<256;i++) {
  67                         //Skip the note on entries
  68 -                       if (i>=0xb0 && i<=0xb8)
  69 -                               continue;
  70 +               //      if (i>=0xb0 && i<=0xb8)
  71 +               //              continue;       // Valley Bell: not neccessary anymore
  72                         val = (*cache)[ i ];
  73                         if (val) {
  74                                 AddWrite( i, val );
  75 @@ -239,6 +257,37 @@
  76                         if (val) {
  77                                 AddWrite( 0x100 + i, val );
  78                         }
  79 +               }*/
  80 +
  81 +               if (mode == MODE_OPL3)
  82 +               {
  83 +                       val = (*cache)[0x105];
  84 +                       AddWrite(0x105, val);
  85 +               }
  86 +               else if (mode == MODE_DUALOPL2)
  87 +               {
  88 +                       for (i = 0x01B0; i < 0x1B9; i ++)
  89 +                       {
  90 +                               val = (*cache)[i];
  91 +                               if (val)
  92 +                               {
  93 +                                       header.hardware = HW_DUALOPL2;
  94 +                                       break;
  95 +                               }
  96 +                       }
  97 +               }
  98 +               // Valley Bell: new loop for better DRO initialization
  99 +               for (i = 1; i < RawUsed; i ++)
 100 +               {
 101 +                       val = (*cache)[ToReg[i]];
 102 +                       AddWrite(ToReg[i], val);
 103 +
 104 +                       //if (mode != MODE_OPL2)
 105 +                       if (header.hardware != HW_OPL2)
 106 +                       {
 107 +                               val = (*cache)[0x100 | ToReg[i]];
 108 +                               AddWrite(0x100 | ToReg[i], val);
 109 +                       }
 110                 }
 111         }
 112         void InitHeader( void ) {
 113 @@ -274,13 +323,14 @@
 114                         */
 115                         Bit8u raw = ToRaw[ regMask ];
 116                         if ( raw == 0xff ) {
 117 +                               //LOG_MSG("Skipped DRO Write: Reg %02X Data %02X", regFull, val);
 118                                 return true;
 119                         }
 120                         /* Check if this command will not just replace the same value
 121                            in a reg that doesn't do anything with it
 122                         */
 123 -                       if ( (*cache)[ regFull ] == val )
 124 -                               return true;
 125 +                       /*if ( (*cache)[ regFull ] == val )
 126 +                               return true;*/  // Valley Bell: bad for later trimming
 127                         /* Check how much time has passed */
 128                         Bitu passed = PIC_Ticks - lastTicks;
 129                         lastTicks = PIC_Ticks;
 130 @@ -289,10 +339,10 @@
 131                         //if ( passed > 0 ) LOG_MSG( "Delay %d", passed ) ;
 132
 133                         // If we passed more than 30 seconds since the last command, we'll restart the the capture
 134 -                       if ( passed > 30000 ) {
 135 +                       /*if ( passed > 30000 ) {
 136                                 CloseFile();
 137                                 goto skipWrite;
 138 -                       }
 139 +                       }*/
 140                         while (passed > 0) {
 141                                 if (passed < 257) {                     //1-256 millisecond delay
 142                                         AddBuf( delay256, passed - 1 );
 143 @@ -309,14 +359,14 @@
 144  skipWrite:
 145                 //Not yet capturing to a file here
 146                 //Check for commands that would start capturing, if it's not one of them return
 147 -               if ( !(
 148 +               /*if ( !(
 149                         //note on in any channel
 150                         ( regMask>=0xb0 && regMask<=0xb8 && (val&0x020) ) ||
 151                         //Percussion mode enabled and a note on in any percussion instrument
 152                         ( regMask == 0xbd && ( (val&0x3f) > 0x20 ) )
 153                 )) {
 154                         return true;
 155 -               }
 156 +               }*/     // Valley Bell: I don't want this for serious logging
 157                 handle = OpenCaptureFile("Raw Opl",".dro");
 158                 if (!handle)
 159                         return false;
 160 @@ -330,11 +380,12 @@
 161                 /* Write the command that triggered this */
 162                 AddWrite( regFull, val );
 163                 //Init the timing information for the next commands
 164 -               lastTicks = PIC_Ticks;
 165 +               lastTicks = PIC_Ticks;
 166                 startTicks = PIC_Ticks;
 167                 return true;
 168         }
 169 -       Capture( RegisterCache* _cache ) {
 170 +       Capture( Mode _mode, RegisterCache* _cache ) {
 171 +               mode = _mode;
 172                 cache = _cache;
 173                 handle = 0;
 174                 bufUsed = 0;
 175 @@ -419,6 +470,10 @@
 176  }
 177
 178  void Module::DualWrite( Bit8u index, Bit8u reg, Bit8u val ) {
 179 +       Bit32u fullReg = reg + (index ? 0x100 : 0);
 180 +       // Valley Bell: moved here for more accurate logging
 181 +       CacheWrite( fullReg, val );
 182 +
 183         //Make sure you don't use opl3 features
 184         //Don't allow write to disable opl3
 185         if ( reg == 5 ) {
 186 @@ -436,9 +491,7 @@
 187                 val &= 0x0f;
 188                 val |= index ? 0xA0 : 0x50;
 189         }
 190 -       Bit32u fullReg = reg + (index ? 0x100 : 0);
 191         handler->WriteReg( fullReg, val );
 192 -       CacheWrite( fullReg, val );
 193  }
 194
 195
 196 @@ -455,8 +508,8 @@
 197                 case MODE_OPL3:
 198                         if ( !chip[0].Write( reg.normal, val ) ) {
 199                                 handler->WriteReg( reg.normal, val );
 200 -                               CacheWrite( reg.normal, val );
 201                         }
 202 +                       CacheWrite( reg.normal, val );  // Valley Bell: moved here for more accurate logging
 203                         break;
 204                 case MODE_DUALOPL2:
 205                         //Not a 0x??8 port, then write to a specific port
 206 @@ -534,7 +587,7 @@
 207                 //Setup opl3 mode in the hander
 208                 handler->WriteReg( 0x105, 1 );
 209                 //Also set it up in the cache so the capturing will start opl3
 210 -               CacheWrite( 0x105, 1 );
 211 +               //CacheWrite( 0x105, 1 );       // VGMs can handle Dual OPL2 correctly and don't need OPL3 mode
 212                 break;
 213         }
 214  }
 215 @@ -617,8 +670,9 @@
 216                 module->capture = 0;
 217                 LOG_MSG("Stopped Raw OPL capturing.");
 218         } else {
 219 -               LOG_MSG("Preparing to capture Raw OPL, will start with first note played.");
 220 -               module->capture = new Adlib::Capture( &module->cache );
 221 +               //LOG_MSG("Preparing to capture Raw OPL, will start with first note played.");
 222 +               module->capture = new Adlib::Capture( module->mode, &module->cache );
 223 +               module->capture->DoWrite(0x00, 0x00);   // start capturing
 224         }
 225  }
 226
 227 diff -Nru src_old/hardware/adlib.h src/hardware/adlib.h
 228 --- src_old/hardware/adlib.h    2010-05-10 17:43:54 +0000
 229 +++ src/hardware/adlib.h        2012-05-25 18:37:46 +0000
 230 @@ -120,7 +120,7 @@
 231         MixerObject mixerObject;
 232
 233         //Mode we're running in
 234 -       Mode mode;
 235 +       //Mode mode;
 236         //Last selected address in the chip for the different modes
 237         union {
 238                 Bit32u normal;
 239 @@ -134,6 +134,7 @@
 240         Bit32u lastUsed;                                //Ticks when adlib was last used to turn of mixing after a few second
 241
 242         Handler* handler;                               //Handler that will generate the sound
 243 +       Mode mode;
 244         RegisterCache cache;
 245         Capture* capture;
 246         Chip    chip[2];