1 Chips and Technologies Super VGA Chip Sets:
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5 82c451 256k DRAM max 800x600 16col
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6 82c452 1M DRAM max 640x480 256col, 1024x768 16col
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7 82c453 1M VRAM max 800x600 256 col
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8 82c455 256k DRAM Flat Panel version
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10 82c457 do. Full color.
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11 F65520 1M D/VRAM do. Full color. max 1280x1024 16 col & 800x600 256 col
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12 F65530 1M D/VRAM do. Full color. max 1280x1024 16 col & 800x600 256 col
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13 Supports Local Bus.
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16 94h (R/W): Setup Control Register for Microchannel boards
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18 3 Enables Adapter VGA if set
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19 4 Enters Setup Mode if set
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21 Note: This is the same register as 46E8h.
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23 100h (R): Microchannel ID low
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24 bit 0-7 Bit 0-7 of Microchannel Card ID
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26 101h (R): Microchannel ID high
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27 bit 0-7 Bit 8-15 of Microchannel Card ID
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29 102h (R/W): Global Enable
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30 bit 0 VGA is enabled if set.
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32 103h (R/W): Multiple Enable
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33 bit 0-3 Multiple VGA Enable
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34 4 Must be 0 for propper operation of 82c455/6/7.
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35 6 Extension registers at 3B6h/7h if set,
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37 7 Extension Registers Access Enable.
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38 VGA Extension registers at 3d7h can only be
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39 accessed if this bit is set.
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40 Note: This register only available in Setup Mode.
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42 104h (R): Global ID (Setup) (Only in Setup Mode)
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43 bit 0-7 Chip I/D. 0A5h if Chips and Tech Chip set.
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45 3C3h (R/W): Setup Control PS/2
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46 bit 0 Enables motherboard VGA if set
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47 4 Enters Setup mode if set
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49 3d4h index 22h (R/W): CPU Data Latch or Color Compare from last read
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51 3d4h index 24h (R/W): Attribute Controller flip/flop
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53 3d6h index 0 (R): Chip Version
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54 bit 0-3 Revision number
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56 0: 451 1:452 2:455 3:453 5:456 6:457
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59 3d6h index 1 (R): DIP Switch Register
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60 bit 0-6 State of the DIP switches.
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61 0-7 (655x0) Read from Memory Address bus A on Reset.
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62 Bit 0-1: CPU Bus type
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63 0=PI bus, 1=MC bus, 2=Local bus (65530 only), 3=ISA bus.
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64 2: Pixel Clock Source (OSC/)
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65 0: CLK0-CLK3 are pixel clock inputs.
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66 CLK0 or CLK1 is MCLK input.
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67 1: CLK0 is MCLK input.
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68 CLK1 is pixel clock input.
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69 CLK2 is CLKSEL0 output.
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70 CLK3 is CLKSEL1 output.
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71 3: Memory Clock Source (56M/)
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72 0: MCLK = 56.644 MHz (80ns RAM)
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75 CLK1 is 56.644 MHz (MCLK source)
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79 MCLK (CLK0) is 56.644 MHz
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80 Clock Select 0 is 40.000 MHz
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81 Clock Select 1 is 50.350 MHz
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82 Clock Select 2 is user defined
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83 Clock Select 3 is 44.900 MHz
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84 1: MCLK = 50.350 MHz (100ns RAM)
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87 CLK1 is 28.322 MHz (MCLK source)
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91 MCLK (CLK0) is 50.350 MHz
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92 Clock Select 0 is 40.000 MHz
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93 Clock Select 1 is 28.322 MHz
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94 Clock Select 2 is user defined
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95 Clock Select 3 is 44.900 MHz
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96 4: Transceiver Control
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97 If set there are no external transceivers (pin 69 is
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98 VGARD output), if clear there are external transceivers
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99 (pin 69 is ENAVEE/ output).
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101 3d6h index 2 (R/W): CPU Interface
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102 bit 0 16bit memory enabled if set
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103 1 (82c451-453) 16 bit I/O if set
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104 (82c453 Only) Fast Font Enable ???
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105 The byte written to memory is used as a mask
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106 for painting foreground color to the pixels
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107 with the corresponding bit set and background
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109 (655x0 Only) Digital Monitor Clock Mode
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110 0: CLK0 = 25 MHz, CLK1 = 28 MHz
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111 1: CLK0 = 14 MHz (56MHz /4 or 28MHz /2)
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112 CLK1 = 16 MHz (50MHz /3)
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113 2 (82c451/2/3/5) Fast MCA buscycle decoding if set
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114 3-4 (82c453 and 455-457) Attribute port pairing
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115 0: Normal Attribute addressing
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116 1: 3C1h is both read and write, 8 and 16 bit.
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117 2: 3C1h is both read and write, 8 bit only.
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118 5 (Not 82c451/2) 10 bit I/O decoding if set, 16 bit else
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119 6 (82c453 Only) Pel Panning Control
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120 (655x0 Only) If set external palette registers can be addressed
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121 at 83C6h-83C9h. (Brooktree/Sierra type DACs).
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122 7 (Read Only) Attribute flip-flop status. If set the Attribute
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123 register (3C0h) is currently in Data mode.
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125 3d6h index 3 (R/W): ROM Interface (not 655x0)
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126 bit 0 Disable on-card ROM if set.
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127 Enable ROM at C0000h-C7FFFh if clear.
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129 3d6h index 4 (R/W): Memory Mapping
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130 bit 0-1 (82c452/3) Display Memory Size:
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131 0: 256Kb, 1: 512Kb, 2: 1Mb.
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132 (655x0) Memory Configuration
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133 0: 2 x 256Kx4 D/VRAM 256K tot 8 bit datapath
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134 1: 4 x 256Kx4 D/VRAM 512K tot 16 bit datapath
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135 3: 2 x 512Kx8 DRAM 1M tot 16 bit datapath
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136 2 (82c451/5/6/7) Enable bank access if set
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137 (82c452/3, 655x0) If set CRTC Address can cross bank boundaries.
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138 3 (82c457) If set DRAM timing is for 64Kx16 (4 WE, 1 CAS)
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139 if clear for 64Kx4 (4 CAS, 1 WE).
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140 (655x0) Enables bank addressing if set.
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141 4 (655x0) If set VRAM interface, else DRAM interface.
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142 5 (655x0) If set CPU memory write buffer is enabled.
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143 6 (655x0) If set enables 0WS capability.
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144 7 (655x0) If set allows faster 0WS cycle timing.
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146 3d6h index 5h (R/W): Sequencer Control (452/3/7 only)
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147 bit 2 (82c457) Clock Pin Polarity.
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148 If set CLK0 is defined as a common clock and CLK1/S0
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149 and CLK2/S1 are select outputs. If clear one of CLK0,
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150 CLK1 and CLK2 is selected as the display clock.
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152 3d6h index 6h (R/W): DRAM Interface (82c452 only)
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154 3d6h index 6h (R/W): Palette Control Register (655x0 only)
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155 bit 0 If set enables external DAC if 3d6h index 6 bit 0 is 0.
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156 1 If set disables the internal DAC.
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157 Causes the DAC to power down and tri-states the outputs.
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158 2 If set enables 16 bit/pixel operation.
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159 Timing to an external DAC will be SC11486 (Tseng) compatible.
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160 (Two bytes output per pixel, one on the rising edge of PCLK
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161 and one on the falling edge).
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162 3 If set 16 bit pixels are 5 red-6 green-5 blue.
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163 If clear they are 5 bits of each.
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164 4 If set the Sense Status bit (3C2h bit 4) is driven by the SENSE
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165 pin from external logic.
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166 5 If set bypasses the internal RAMDAC.
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167 This bit should always be clear.
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168 6-7 Color Reduction Select.
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169 In flat panel modes these bits determine the algorithm used to
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170 reduce 18 bit color data to 6 bits for mono panels.
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171 0: NTSC weighting, 1: Equivalent weight, 2: Green only, 3: Color.
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173 3d6h index 8h (R/W): General Purpose Output Select B Register. (451/2/5/6/7 only)
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174 bit 0 Select bit B for ERMIN/ pin.
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175 1 Select bit B for TRAP/ pin.
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176 2 (82c457) If set PNL14 pin outputs panel data bit 14,
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177 if clear PNL14 pin outputs DATEN/.
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179 3d6h index 9h (R/W): General Purpose Output Select A Register. (451/2/5/6/7 only)
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180 bit 0 Select bit A for ERMIN/ pin.
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181 1 Select bit A for TRAP/ pin.
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182 Select A and B determine the output on the pin:
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186 set clear Force low
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187 set set Force high
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189 3d6h index Ah (R/W): Cursor Address Top (82c452/3 Only)
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190 bit 0-1 Cursor Address bit 16,17
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193 3d6h index Bh (R/W): CPU Paging (82c451/5/6/7 only)
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194 bit 0-1 Bank number in 64k chunks.
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195 Note: This Bank register is used if in a 256 color mode and
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196 the chip is a 82c451/5/6/7.
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198 3d6h index Bh (R/W): Memory Paging Register (82c452/3, 655x0 only)
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199 bit 0 Enable extended paging (256 color paging) if set
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200 1 If set Dual Pages are enabled. A0000h-A7FFFh uses 3d6h
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201 index 10h, A8000h-AFFFFh uses 3d6h index 11h.
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202 2 CPU Address divide by 4 (256 color addressing)
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203 3 (655x0) If set CPU address divide by 2 is enabled.
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204 4 (65530) If set Memory is mapped as 1MB linear Memory.
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206 3d6h index Ch (R/W): Start Address Top (82c452/3, 655x0 Only)
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207 bit 0-1 Display Start Address bit 16,17.
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209 3d6h index Dh (R/W): Auxiliary Offset Register
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210 bit 0 Bit 8 of Offset field. If set each line is >255 words.
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211 1 Bit 8 of simulated Offset field.
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213 3d6h index Eh (R/W): Text Mode (82c452, 655x0 Only)
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214 bit 0 (82c452) Extended text Mode Control ??
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215 1 (82c452) Enable anti-aliased fonts if set
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216 2 (655x0) If set cursor is non-blinking.
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217 3 (655x0) If set Cursor style is Exclusive-Or.
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219 3d6h index Fh (R/W): Software Flags 2 (655x0 only)
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220 bit 0-7 Software flags.
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222 3d6h index 10h (R/W): Single/Low Map (82c452/3, 655x0 Only)
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223 bit 0-5 (82c452) Bank no in 4K/16K chunks.
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224 0-7 (82c453) Bank no in 1K/4K chunks.
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225 Note: This Bank register is used if in single-paging mode
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226 or if addressing the lower half (32 or 64Kb) of the
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227 adapters address range.
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229 3d6h index 11h (R/W): High Map (82c452/3, 655x0 Only)
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230 bit 0-5 (82c452) Bank no in 4K/16K chunks.
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231 0-7 (82c453) Bank no in 1K/4K chunks.
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232 Note: This Bank register is used if addressing the upper
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233 half (32 or 64Kb) of the adapters address range.
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235 3d6h index 14h (R/W): Emulation Mode Register
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236 bit 0-1 Emulation Mode:
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237 0=VGA/EGA, 1=CGA, 2=MDA and 3=Hercules.
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238 2 (R) Hercules Configuration (3BFh) bit 0 Readback.
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239 If set it is possible to set the Graphics Mode bit (3B8h bit 1).
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240 3 (R) Hercules Configuration (3BFh) bit 1 Readback.
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241 If set it is possible to set the Graphics Page bit (3B8h bit 7).
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242 4 Display Enable Status Mode.
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243 If set bit 0 of the Input Status Register 1 (3dAh)
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244 shows the Hsync Status (as MDA/Hercules), if clear the
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245 Display Enable is shown (as CGA/VGA).
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246 5 Vertical Retrace Status Mode.
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247 If set bit 3 of the Input Status Register 1 (3dAh)
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248 shows the Video signal (as MDA/Hercules), if clear the
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249 Vertical Retrace status is shown (as CGA/VGA).
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250 6 Vsync Status Mode.
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251 If clear bit 7 of the Input Status Register 1 (3dAh)
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252 shows the Vsync Status (as MDA/Hercules).
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253 7 Interrupt Output Function.
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254 If clear the IRQ pin will always 3-state, if set it
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255 will 3-state only when interrupts are disabled.
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257 3d6h index 15h (R/W): Write Protect Register.
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258 bit 0 Write Protect Group 1 Registers.
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259 If set the Sequencer (3C4h), Graphics Controller (3CEh)
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260 and Attribute Controller (3C0h) registers are write protected.
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261 1 Write Protect Group 2 Registers.
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262 If set the Cursor Size Register (3d4h index 9 bits 0-4)
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263 and the Character Height registers (3d4h index 0Ah and 0Bh)
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264 are write protected.
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265 2 Write Protect Group 3 Registers.
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266 If set CRT registers (3d4h) index: 7 bit 4, 8, 11h bits 4-5,
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267 13h, 14h, 17h bits 0-1 and 3-7, 18h are write protected.
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268 3 Write Protect Group 4 Registers.
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269 If set CRT registers (3d4h) index: 9 bits 5-7, 10h, 11h bits 0-3
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270 and 6-7, 12h, 15h, 16h, 17h bit 2 are write protected.
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271 4 Write Protect Group 5 Register.
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272 If set the Miscellaneous Output (3C2h) and Feature Control
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273 (3dAh) registers are write protected.
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274 5 Write Protect Group 6 Registers.
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275 If set the DAC registers (3C6h-3C9h) are write protected.
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276 6 Write Protect Group 0 Registers.
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277 If set CRT registers (3d4h) index: 0, 1, 2, 3, 4, 5, 6,
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278 7 bits 0-3 and 5-7 are write protected.
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280 3d6h index 16h (R/W): Trap Enable Register. (not 655x0)
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281 bit 0 If set accesses to registers 3B4h or 3B5h cause a Trap.
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282 1 If set accesses to registers 3B8h or 3BFh cause a Trap.
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283 2 If set accesses to registers 3C0h-3CFh cause a Trap.
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284 3 If set accesses to registers 3D4h or 3D5h cause a Trap.
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285 4 If set accesses to registers 3D8h or 3D9h cause a Trap.
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286 5 If set accesses to registers 3d4h index 0-0Bh and 10h-18h
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289 3d6h index 17h (R/W): Trap Status Register. (not 655x0)
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290 bit 0 If set a trap occurred due to access to registers 3B4h or 3B5h.
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291 1 If set a trap occurred due to access to registers 3B8h or 3BFh.
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292 2 If set a trap occurred due to access to registers 3C0h-3CFh.
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293 3 If set a trap occurred due to access to registers 3D4h or 3D5h.
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294 4 If set a trap occurred due to access to registers 3D8h or 3D9h.
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295 5 If set a trap occurred due to access to registers
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296 3d4h index 0-0Bh or 10h-18h.
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297 Note: Any bits in this register can be cleared by writing a 1 bit to them.
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299 3d6h index 18h (R/W): Alternate Horizontal Display Enable End Register
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300 bit 0-7 This register replaces the Horizontal Display Enable End Register
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301 (3d4h index 1) in low resolution CGA text and graphics modes,
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302 Hercules Graphics and all flat panel modes.
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303 Note: Probably doesn't exist in the 82c451/2/3.
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305 3d6h index 19h (R/W): Alternate Horizontal Sync Start Register
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306 bit 0-7 This register replaces the Horizontal Sync Start Register
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307 (3d4h index 4) in low resolution CGA text and graphics modes,
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308 Hercules Graphics and all flat panel modes.
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309 Note: Probably doesn't exist in the 82c451/2/3.
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311 3d6h index 1Ah (R/W): Alternate Horizontal Sync End Register
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312 bit 0-4 Alternate Horizontal Sync End. Replaces 3d4h index 5 bits 0-4.
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313 5-7 Alternate Horizontal Sync Delay.
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314 For CRTs replaces 3d4h index 5 bits 5-6.
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315 Note: This register replaces the Horizontal Sync End Register (3d4h index 5)
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316 in low resolution CGA text and graphics modes, Hercules Graphics and
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317 all flat panel modes.
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318 Note: Probably doesn't exist in the 82c451/2/3.
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320 3d6h index 1Bh (R/W): Alternate Horizontal Total Register
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321 bit 0-7 This register replaces the Horizontal Total Register
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322 (3d4h index 0) in low resolution CGA text and graphics modes,
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323 Hercules Graphics and all flat panel modes.
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324 Note: Probably doesn't exist in the 82c451/2/3.
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326 3d6h index 1Ch (R/W): Alternate Horizontal Blank Start Register (CRT)
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327 bit 0-7 Alternate Horizontal Blank Start.
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328 Note: For CRT systems this register replaces the Horizontal Blank Start
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329 Register (3d4h index 2) in low resolution CGA text and graphics
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330 modes and Hercules Graphics mode.
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331 Note: Probably doesn't exist in the 82c451/2/3.
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332 Note: This register has different meaning for CRT and Plat Panel systems.
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334 3d6h index 1Ch (R/W): Alternate Horizontal Blank End Register (Flat Panel)
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335 bit 0-7 For Flat Panel systems this value specifies the end of Horizontal
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336 Blank in terms of character clocks.
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337 Note: Probably doesn't exist in the 82c451/2/3.
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338 Note: This register has different meaning for CRT and Plat Panel systems.
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340 3d6h index 1Dh (R/W): Alternate Horizontal Blank End Register (CRT)
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341 bit 0-4 Alternate Horizontal Blank End
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342 5-6 Alternate Display Enable Skew Control.
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343 Note: For CRT systems this register replaces the Horizontal Blank End
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344 Register (3d4h index 3) in low resolution CGA text and graphics
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345 modes, and Hercules Graphics mode.
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346 Note: Probably doesn't exist in the 82c451/2/3.
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347 Note: This register has different meaning for CRT and Plat Panel systems.
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349 3d6h index 1Dh (R/W): Alternate Horizontal Blank Start Register (Flat Panel)
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350 bit 0-7 Alternate Horizontal Blank Start.
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351 Note: For Flat Panel systems this register replaces the Horizontal Blank
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352 Start Register (3d4h index 2).
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353 Note: Probably doesn't exist in the 82c451/2/3.
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354 Note: This register has different meaning for CRT and Plat Panel systems.
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356 3d6h index 1Eh (R/W): Alternate Offset Register
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357 bit 0-7 Alternate Offset.
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358 Note: This register replaces the Offset Register (3d4h index 13h) in low
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359 resolution CGA text and graphics modes and Hercules Graphics mode.
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360 Note: Probably doesn't exist in the 82c451/2/3.
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362 3d6h index 1Fh (R/W): Virtual EGA Switch Register (655x0 only)
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363 bit 0-3 If bit 7 is 1 one of these bits is read back in the Input Status
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364 Register 0 (3C2h bit 4) depending on Miscellaneous Output bits 2-3:
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365 0: bit 3, 1: bit 2, 2: bit 1, 3:bit 0.
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366 7 If set one of bits 0-3 is read back in the Input Status Register
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369 3d6h index 20h (R/W): Sliding Unit Delay (452/3 only)
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371 3d6h index 21h (R/W): Sliding Hold A (452 only)
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373 3d6h index 22h (R/W): Sliding Hold B (452 only)
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375 3d6h index 23h (R/W): Write Mask Control (452/3 Only)
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376 bit 0 Enable VRAM Write Mask function if set
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377 1-2 Write Bit Mask Select:
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378 0: Write Bit Mask Pattern Register (3d6h index 24h)
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379 1: Graphics Controller Bit Mask (3CEh index 8)
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380 2: Rotated CPU byte
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381 3 Enable Fast Read/Modify/Write function if set
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383 3d6h index 24h (R/W): Write Bit Mask Pattern (82c452/3 only)
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384 bit 0-7 Write Bit Mask (if 3d6h index 23h bit 1-2 =0)
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386 3d6h index 24h (R/W): Alternate Maximum Scanline Register (655x0 only)
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387 bit 0-4 Number of scanlines -1 per character row of TallFont.
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388 Note: Used in Flat Panel text modes when TallFont is enabled.
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390 3d6h index 25h (R/W): FP AltGrHVirtPanel Size (453, 655x0 only)
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391 bit 0-7 Should be: (9/8)*(3d6h index 1Ch +1) -1.
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393 3d6h index 26h (R/W): Configuration (82c453 Only)
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394 bit 0 PC/AT if set, PS/2 else
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396 0: 512k 16 chips of 64k x4
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397 1: 512k 4 chips of 256k x4
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398 2: 1M 8 chips of 256k x4
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399 3: 512k 8 chips of 64k x4 ?????
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402 3d6h index 27h (R/W): Force Sync State
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404 3d6h index 28h (R/W): Video Interface
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405 bit 0 BLANK/Display Enable Polarity.
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406 Positive if set, Negative if clear.
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407 1 Blank /Display Enable Select (CRT).
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408 If set the BLANK/ pin outputs DE, if clear BLANK/
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410 If set the video signal is forced to default video
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411 (3d6h index 2bh) during the blanking interval.
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413 If set the BLANK/ output is forced active
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414 during the blanking interval.
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415 (655x0) Read/writable, but has no function.
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416 4 (655x0) 256 Color Video Path.
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417 If set Video Data Path is 8 bits rather than 4 bits.
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418 5 (655x0) Interlace Video. CRT graphics modes only.
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419 If set Video is interlaced.
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420 6 (655x0) 8-bit Video Pixel Panning.
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421 If set 3C0h index 13h bits 0-2 are used to control
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422 pixel panning rather than bits 1-2.
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423 7 (655x0) Read/writable, but has no function.
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425 3d6h index 29h (R/W): External Sync Control (452 only)
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427 3d6h index 2Ah (R/W): Frame Interrupt Count (452 Only)
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428 bit 0-4 Generate Vertical Interrupt every (n+1) frames
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430 3d6h index 2Bh (R/W): Default Video Register (not 453)
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431 bit 0-7 On CRTs this is the color displayed during blank time.
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433 3d6h index 2Ch (R/W): FP Vsync (FLM) Delay Register.
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434 bit 0-7 Number of Hsync pulses between internal Vsync and the
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435 rising edge of First Line Marker (FLM).
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436 Note: Only used in Flat Panel modes when 3d6h index 2Fh bit 7 is 0..
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438 3d6h index 2Dh (R/W): FP Hsync (LP) Delay Register.
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439 bit 0-7 Number of character clocks between the FP Blank inactive
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440 edge and the rising edge of the LP.
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441 Note: Only used in Flat Panel modes when 3d6h index 2Fh bit 6 is 0 and
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442 graphics mode horizontal compression is disabled.
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444 3d6h index 2Eh (R/W): FP Hsync (LP) Delay Register.
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445 bit 0-7 Number of character clocks between the FP Blank inactive
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446 edge and the rising edge of the LP.
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447 Note: Only used in Flat Panel modes when 3d6h index 2Fh bit 6 is 0
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448 and 9 dot text mode is used.
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450 3d6h index 2Fh (R/W): FP Hsync (LP) Width Register
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451 bit 0-3 Width of the LP output pulse in number of character clocks.
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452 Only in 8 dot text modes on Flat Panels.
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453 4 Bit 8 of the FP Hsync (LP) Delay Register (3d6h index 2Eh).
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454 5 Bit 8 of the FP Hsync (LP) Delay Register (3d6h index 2Dh).
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455 6 FP Hsync (LP) Delay Disable.
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456 If set the FP Hsync (LP) active edge will coincide with the
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457 FP Blank inactive edge.
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458 7 FP Vsync (FLM) Delay Disable.
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459 If set the external FP Vsync (FLM) will coincide with
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460 the internal FP Vsync (FLM) active edge.
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462 3d6h index 30h (R/W): Graphics Cursor Start Address High
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463 bit 0-7 Bit 8-15 of the Cursor Start Address.
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465 3d6h index 31h (R/W): Graphics Cursor Start Address Low
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466 bit 0-7 Lowest 8 bits of the Cursor Start address.
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467 3d6h index 30h and index Ah forms the upper 10 bits.
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468 In 256 color modes this address has a granularity
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469 of 16 bytes and 4 bytes in 16 color modes.
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471 3d6h index 32h (R/W): Graphics Cursor End Address
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472 bit 0-7 End address of the cursor bit map.
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474 3d6h index 33h (R/W): Graphics Cursor X Position High
\r
475 bit 0-3 Bits 8-11 of the X coordinate of the cursor.
\r
477 3d6h index 34h (R/W): Graphics Cursor X Position Low
\r
478 bit 0-7 Lower 8 bits of the X coordinate of the cursor.
\r
480 3d6h index 35h (R/W): Graphics Cursor Y Position High
\r
481 bit 0-3 Bits 8-11 of the Y coordinate of the cursor.
\r
483 3d6h index 36h (R/W): Graphics Cursor Y Position Low
\r
484 bit 0-7 Lower 8 bits of the cursor Y coordinate.
\r
486 3d6h index 37h (R/W): Graphics Cursor Mode
\r
487 bit 0 Cursor Enabled if set
\r
488 1 Cursor Status enable
\r
489 2 Horizontal Zoom. Zoom to 64 pixels wide if set.
\r
490 (Normally 32 pixels wide).
\r
491 3 Cursor Blink enabled if set
\r
492 4 Cursor Blink Rate. 8 frames if clear, 16 if set
\r
494 3d6h index 38h (R/W): Graphics Cursor Plane Mask
\r
495 bit 0 Enables graphics cursor in bit plane 0 if set
\r
496 1 Enables graphics cursor in bit plane 1 if set
\r
497 2 Enables graphics cursor in bit plane 2 if set
\r
498 3 Enables graphics cursor in bit plane 3 if set
\r
500 3d6h index 39h (R/W): Graphics Cursor Color 0
\r
501 bit 0-7 Background color of Graphics Cursor.
\r
503 3d6h index 3Ah (R/W): Graphics Cursor Color 1
\r
504 bit 0-7 Foreground color of Graphics Cursor.
\r
506 3d6h index 44h (R/W): Scratch #0 Register (82c453, 655x0 Only)
\r
509 3d6h index 45h (R/W): Scratch #1/Foreground Color (82c453 Only)
\r
510 bit 0-7 Used as foreground color if in Fast Font Paint mode,
\r
511 Available as scratch else.
\r
513 3d6h index 50h (R/W): Panel Format (82c455/6/7 Only)
\r
514 bit 0-1 Frame Rate Control
\r
515 0: No gray scale simulated for mono,
\r
516 8 colors simulated for color panels.
\r
517 1: 4 simulated colors for color panels only
\r
518 (64 colors displayed).
\r
519 2: (82c455/6) 64 gray levels simulated for mono. panels only.
\r
520 (82c457) 16 levels simulated for each color output.
\r
521 4096 colors simulated.
\r
522 3: (82c457) 3 levels simulated for each color output.
\r
523 27 colors simulated.
\r
524 2-3 Pulse Width Modulation
\r
525 0: No gray scales for mono or color systems.
\r
526 1: 4 colors supported by the color panels only
\r
527 (64 colors displayed).
\r
528 2: 16 gray levels supported by the mono panels only.
\r
529 3: 256 gray levels supported by the
\r
530 color single panels only.
\r
531 (655x0) Dither Enable.
\r
533 1: Enable dither for 256 color modes.
\r
534 2: Enable dither for all modes.
\r
535 4-5 Clock Divide (CD).
\r
536 0: Shift Clock = Dot Clock
\r
537 1: Shift Clock = Dot Clock/2
\r
538 2: Shift Clock = Dot Clock/4
\r
539 3: (655x0) Shift Clock = Dot Clock/8.
\r
540 7 Shift Clock Mask.
\r
541 If set the Shift Clock stops outside the
\r
542 Display Enable interval.
\r
543 6-7 (655x0) VAM/FRC Control
\r
544 0: bit 2-3 determine the dither:
\r
545 0: 6 bpp VAM (dither bits 0-1).
\r
546 1: 4 bpp VAM (dither bits 0-1).
\r
547 2: 2 bpp VAM (dither bits 2-3).
\r
548 3: 1 bpp VAM (dither bits 4-5).
\r
549 1: 3 Bits/Pixel VAM (dither bits 1-2).
\r
550 Use with bit 2-3=0 or 1 for mono panels,
\r
551 Use with bit 2-3=0 for color panels.
\r
552 2: (65530) 2-Frame FRC
\r
553 3 level gray scale simulation without dither or
\r
554 9 level gray scale simulation with dither.
\r
555 3: (65530) 3 Bits/Pixel VAM + 2-Frame FRC.
\r
556 15-level gray scale simulation without dithering and
\r
557 56 level gray scale simulation with dithering.
\r
560 3d6h index 51h (R/W): Panel Type (82c455/6/7, 655x0 Only)
\r
561 bit 0 (82c455/6) Double drive if set, single else
\r
562 1 Double panel if set, single else
\r
563 2-3 Type of display
\r
564 0=LCD, 1=CRT, 2=Plasma or Electrolum.
\r
565 2 (655x0) Display Type. 0=CRT, 1=Flat Panel.
\r
566 3 (655x0) 8/16 bit FP Video Interface.
\r
567 If set the Flat Panel Video interface is 16 bit.
\r
568 4-5 0=Color panel 3 bit data pack
\r
569 1=Color Panel 1 bit data pack
\r
570 2=(82c455/6) Monochrome Panel
\r
571 3=(82c457) Extended 4-bit pack
\r
572 4 (655x0) Video Skew.
\r
573 If set Video data is delayed 1 shift clock cycle.
\r
574 5 (655x0) Shift Clock Mask (SM). Flat Panel mode only.
\r
575 If set the shift clock is forced low outside the display
\r
576 interval. If clear it also toggles outside the interval.
\r
577 6 Flat Panel Compatibility enabled if set
\r
578 7 Text Video output polarity
\r
580 3d6h index 52h (R/W): Panel Size (82c455/6/7 Only)
\r
581 bit 0-1 Horizontal Size of panel
\r
582 1=640 pixels, 2=720 pixels
\r
583 3-6 Vertical Size of panel
\r
584 1=200 lines, 2=350, 4=400, 8=480 lines
\r
586 3d6h index 52h (R/W): Power Down Control Register. (655x0 only)
\r
587 bit 0-2 FP Normal Refresh Count. Flat Panel modes only.
\r
588 Number of memory refresh cycles to perform per scanline.
\r
589 3 Panel Off Mode. If set the CRT/FP interface is inactive.
\r
590 4 Panel Off Control Bit 0. Only effective if bit 3 is set.
\r
591 If set the Video data, CRT and Flat Panel timing signals
\r
592 are forced inactive, rather than only the Video data.
\r
593 5 Panel Off Control bit 1. Only effective if bit 3 is set.
\r
594 If set inactive video data and/or timing pins are tri-stated
\r
595 rather than being driven.
\r
596 6 Standby Control. Only effective if the STNDBY/ is low.
\r
597 In standby mode the video output, timings and CPU interface
\r
598 are inactive. If set set the Display memory refresh is derived
\r
599 from the 32kHz input. If clear the DRAMs are self-refreshed.
\r
600 7 CRT Mode Panel Off. Only effective in CRT modes.
\r
601 If set Video data and timing signals are tri-stated.
\r
603 3d6h index 53h (R/W): Override Register (82c455/6/7, 655x0 Only)
\r
604 bit 0 Disable AR10D2. If set the ninth pixel of characters is
\r
605 controlled by this register, if clear it is controlled
\r
606 by the Mode Control Register (3C0h index 10h) bit 2.
\r
607 1 Alternate Line Graphics Character Code.
\r
608 Only effective if bit 0 is set.
\r
609 If set the ninth pixel of a character is forced to the same value
\r
610 as the 8th pixel. If clear it is forced to the background color.
\r
611 2 (655x0) FRC option 1.
\r
612 3 (655x0) FRC option 2.
\r
613 4-5 (65530) Pixel Packing. Only effective for Color STN panels.
\r
614 0: 3-bit Pack. 3d6h index 50h bits 4-5 can be 0,1 or 2.
\r
615 1: 4-bit Pack. 3d6h index 50h bits 4-5 can be 1 or 1.
\r
616 3: Extended 4-bit Pack. 3d6h index 50h bits 4-5 must be 1.
\r
617 7 (65530) High Color Mode Flat Panel Operation.
\r
618 If set Hi-Color operation is enabled in hi-res modes on
\r
619 Flat panel. If clear it is enabled in low-res modes.
\r
622 3d6h index 54h (R/W): Alternate Miscellaneous Output Register (82c455/6/7 Only)
\r
623 bit 0 Panel Video Skew
\r
624 2-3 Clock Select Bits
\r
625 6 Hsync. Negative if set, Positive if clear.
\r
626 7 Vsync. Negative if set, Positive if clear.
\r
627 Note: For Flat Panel systems this register replaces the Miscellaneous
\r
628 Output Register (3C2h).
\r
630 3d6h index 54h (R/W): FP Interface Register (655x0 Only)
\r
631 bit 0 FP Blank Polarity.
\r
632 If set the BLANK/ pin has negative polarity.
\r
633 1 If set the BLANK/ pin outputs only the FP Horizontal Blank
\r
634 signal, if clear it outputs both Vertical and Horizontal
\r
636 2-3 FP Clock Select Bits 0-1.
\r
637 In Flat Panel modes these bits replace 3C2h bits 2-3.
\r
638 4-5 FP Feature Control bits 0-1.
\r
639 In Flat Panel modes these bits replace 3dAh bits 0-1.
\r
640 6 FP HSync (LP) Polarity.
\r
641 If set the HSync (LP) pin has negative polarity.
\r
642 7 FP VSync (FLM) Polarity.
\r
643 If set the Vsync (FLM) pin has negative polarity.
\r
644 Note: This register is only effective in Flat Panel modes.
\r
646 3d6h index 55h (R/W): Text Mode 350_A (82c455/6/7 Only)
\r
647 bit 0-3 (Number of blank lines)-1 inserted between text rows
\r
648 I.e. if 5, insert 6 blank lines after a text line.
\r
649 4 If clear lines are inserted.
\r
650 Note: This register is used if in a 350 line text mode
\r
651 and fonts are larger than 8 lines.
\r
653 3d6h index 55h (R/W): Horizontal Compensation Register (655x0 Only)
\r
654 bit 0 Enable Horizontal Compensation (EHCP)
\r
655 If set Horizontal compensation is enabled.
\r
656 1 Enable Automatic Horizontal Centring (EAHC)
\r
657 If set (and bit 0 is set) EAHC is enabled.
\r
658 Horizontal left and right borders will be computed
\r
660 2 Enable Text Mode Horizontal Compression (ETHC).
\r
661 If set, bit 0 is set and we are in a Flat Panel Text
\r
662 mode ETHC is enabled.
\r
663 9-dot text modes will be forced to 8-bit.
\r
664 5 Enable Automatic Horizontal Doubling (EAHD).
\r
665 If set and bit 0 is set, EAHD is enabled.
\r
666 If Horizontal Display Width (3d4h index 1) is less
\r
667 than or equal to half the Horizontal Panel Size
\r
668 (3d6h index 18h) horizontal pixel doubling will be forced.
\r
669 6 Alternate CRT Hsync Polarity.
\r
670 Negative if set, Positive if clear.
\r
671 7 Alternate CRT Vsync Polarity.
\r
672 Negative if set, Positive if clear.
\r
674 3d6h index 56h (R/W): Text Mode 350_B (82c455/6/7 Only)
\r
675 bit 0-3 (Number of blank lines)-1 inserted between text rows
\r
676 4 If clear lines are inserted.
\r
677 Note: This register is used if in a 350 line text mode
\r
678 and fonts are smaller than or equal to 8 lines.
\r
680 3d6h index 56h (R/W): Horizontal Centring Register (655x0 Only)
\r
681 bit 0-7 Horizontal Left Border.
\r
682 Size of the left border in pixels -1.
\r
683 Only used if in a Flat Panel mode and non-automatic
\r
684 horizontal centring is enabled.
\r
686 3d6h index 57h (R/W): Text Mode 400 (82c455/6/7 Only)
\r
687 bit 0-3 (Number of blank lines)-1 inserted between text rows
\r
688 4 If clear lines are inserted.
\r
689 Note: This register is used if in a 400 line text mode.
\r
691 3d6h index 57h (R/W): Vertical Compensation Register (655x0 Only)
\r
692 bit 0 Enable Vertical Compensation if set.
\r
693 1 Enable Automatic Vertical Centring.
\r
694 If set and bit 0 set, the image will automatically
\r
695 be centred vertically.
\r
696 2 Enable Text Mode Vertical Stretching.
\r
697 If set and bit 0 set, text mode vertical
\r
698 stretching is enabled.
\r
699 3-4 Text Mode Vertical Stretching. If bit 0 & 2 set.
\r
700 0 = Double Scanning (DS) and Line Insertion (LI)
\r
701 with priority: DS+li, DS, LI.
\r
702 1 = Double Scanning (DS) and Line Insertion (LI)
\r
703 with priority: DS+LI, LI, DS.
\r
704 2 = Double Scanning (DS) and TallFont (TF)
\r
705 with priority: DS+TF, DS, TF.
\r
706 3 = Double Scanning (DS) and TallFont (TF)
\r
707 with priority: DS+TF, TF, DS.
\r
708 5 Enable Vertical Stretching if set and bit 0 set.
\r
709 6 Vertical Stretching.If bits 0 and 5 set.
\r
710 0 = Double Scanning (DS) and Line Replication (LR)
\r
711 with priority: DS+LR, DS, LR.
\r
712 1 = Double Scanning (DS) and Line Replication (LR)
\r
713 with priority: DS+LR, LR, DS.
\r
715 3d6h index 58h (R/W): Graphics Mode 350 (82c455/6/7 Only)
\r
716 bit 0-3 Number of scan lines between stretch/delete
\r
717 4 Enable vertical Stretching if set
\r
718 5 Enable vertical deletion if set
\r
719 6 If set the value in bits 0-3 is incremented every other period.
\r
720 Note: This register is used if in a 350 line graphics mode.
\r
722 3d6h index 58h (R/W): Vertical Centring Register (655x0 Only)
\r
723 bit 0-7 Vertical Top Border LSBs.
\r
724 Lower 8 bits of the Vertical Top Border.
\r
725 Bits 8-9 are in 3d6h index 59h bits 5-6.
\r
726 Note: used only in Flat panel modes when non-automatic
\r
727 vertical centring is enabled.
\r
729 3d6h index 59h (R/W): Graphics Mode 400 (82c455/6/7 Only)
\r
730 bit 0-3 Number of scan lines between stretch/delete
\r
731 4 Enable vertical Stretching if set
\r
732 5 Enable vertical deletion if set
\r
733 6 If set the value in bits 0-3 is incremented every other period.
\r
734 Note: This register is used if in a 400 line graphics mode.
\r
736 3d6h index 59h (R/W): Vertical Line Insertion Register (655x0 Only)
\r
737 bit 0-3 Vertical line Insertion Height.
\r
738 Number of lines -1 to insert between text rows.
\r
739 5-6 Bits 8-9 of the Vertical Top Border (3d6h index 58h).
\r
740 Note: This register is only used in Flat Panel text modes.
\r
742 3d6h index 5Ah (R/W): Flat Panel Vertical Display Start_400 (82c455/6/7 Only)
\r
743 bit 0-7 For 400 line Flat Panel modes these are the lower 8 bits of the
\r
744 Vertical Display Start (in scanlines). The upper 2 bits are in the
\r
745 Flat Panel Vertical Overflow 2 Register (3d6h index 6Bh) bits 2-3.
\r
747 3d6h index 5Ah (R/W): Vertical Line Replication Register. (655x0 Only)
\r
748 bit 0-3 Vertical line Replication Height.
\r
749 Number of lines-1 between replicated lines.
\r
750 Double scanned lines are also counted.
\r
751 Note: This register is only used when in Flat Panel text modes
\r
752 and Line Replication is enabled.
\r
754 3d6h index 5Bh (R/W): Flat Panel Vertical Display End_400 (82c455/6/7 Only)
\r
755 bit 0-7 For 400 line Flat Panel modes these are the lower 8 bits of the
\r
756 Vertical Display End (in scanlines). The upper 2 bits are in the
\r
757 Flat Panel Vertical Overflow 2 Register (3d6h index 6Bh) bits 6-7.
\r
759 3d6h index 5Bh (R/W): Panel Power Sequencing Delay register (65530 Only)
\r
760 bit 0-3 Panel Power Down sequencing Delay in 32ms counts. (0-480ms)
\r
761 4-7 Panel Power Up Sequencing Delay in 4ms counts. (0-60ms)
\r
762 Note: This register is used only when the Panel power Sequencing
\r
763 feature is enabled. Default to 81h for compatibility with 65520.
\r
765 3d6h index 5Ch (R/W): Weight Clock Control Register A (82c455/6 only)
\r
766 bit 0-5 This register is used in Flat Panel mode when bit 7 of the Panel
\r
767 Format Register (3d6h index 50h) is set and bits 2-3 of the same
\r
768 register is either 1 or 2.
\r
769 The time from Hsync to the first pulse on the WGTCLK is this
\r
770 value*4 dot clocks. See also 3d6h index 5Dh and 6Ch.
\r
772 3d6h index 5Dh (R/W): Weight Clock Control Register B (82c455/6 only)
\r
773 bit 0-5 This register is used in Flat Panel mode when bit 7 of the Panel
\r
774 Format Register (3d6h index 50h) is set and bits 2-3 of the same
\r
775 register is either 1 or 2.
\r
776 The time between WGTCLK pulses is this value*4 dot clocks.
\r
777 See also 3d6h index 5Ch and 6Ch.
\r
779 3d6h index 5Eh (R/W): ACDCLK Control Register (82c455/6/7, 655x0 only)
\r
780 bit 0-6 ACDCLK Count. Number of Hsync pulses between changes in ACDCLK.
\r
781 7 If set the ACDCLK phase inverts every frame, if clear the ACDCLK
\r
782 changes phase when the number of Hsynmc pulses specified in
\r
783 bits 0-6 have elapsed.
\r
785 3d6h index 5Fh (R/W): Power Down Mode Refresh Register (82c455/6/7, 655x0 only)
\r
786 bit 0-7 (82c455/6/7) Sleep Mode Refresh Frequency.
\r
787 A refresh will happen for every (4*this value)+8 dot clocks.
\r
788 0-1 (655x0) Power Down Refresh Frequency.
\r
789 Refresh happens every xx micro seconds:
\r
790 0=16usek, 1=32 usek, 2=64 usek and 3=128 usek.
\r
792 3d6h index 60h (R/W): Blink Rate Control (82c455/6/7, 655x0 Only)
\r
793 bit 0-5 Blink Rate.
\r
794 Character Blink Freq = Vertical sync Freq * (Blink rate+1)
\r
795 Cursor blink freq = Character Blink Freq *2.
\r
796 6-7 Blink Cycle 1=25%, 2=50%, 3=75%
\r
798 3d6h index 61h (R/W): Smartmap Control (82c455/6, 655x0 Only)
\r
799 bit 0 If set enables Smartmap and bypasses internal color lookup table.
\r
800 1-4 Threshold for (Foreground - Background) diff
\r
801 if diff less than the threshold the foreground and
\r
802 background colors will be spread (See 3d6h index 62h).
\r
803 5 Smartmap Saturation value.
\r
804 If set the result is calculated modulo 16,
\r
805 if clear it is rounded to min. or max. values (0 and 0Fh).
\r
806 6 (82c456, 655x0) Enhanced text if set
\r
807 (reverses attributes 7h and Fh)
\r
808 7 (655x0) Text Video Output Polarity (TVP) if set.
\r
809 Only effective in Flat Panel modes.
\r
811 3d6h index 62h (R/W): Smartmap Shift Parameter (82c455/6, 655x0 Only)
\r
812 bit 0-3 Number of levels to shift foreground color
\r
813 when too little difference (See 3d6h index 61h bit 1-4).
\r
814 4-7 Number of levels to shift background color.
\r
816 3d6h index 63h (R/W): Graphics Color Mapping Control (82c455/6 Only)
\r
817 bit 0-3 Threshold color value for mono output.
\r
818 All colors >= this value will be set to 1,
\r
820 4 Use upper 4 bits of 256 color if set, lower if not.
\r
821 5 Enable internal color lookup table if set
\r
822 6 Write protect internal color look up table if set
\r
823 7 Graphics output polarity
\r
825 3d6h index 63h (R/W): Smartmap Color Mapping Control (655x0 only)
\r
826 bit 0-5 Color Threshold. Used for mapping 6 bit color to 1 bit.
\r
827 Color values greater than or equal than this value
\r
828 are mapped to 1, and lower values are mapped to 0.
\r
829 6 Must be set to 1.
\r
830 7 Graphics Video Output Polarity
\r
831 Inverted polarity if set, normal if clear.
\r
832 Graphics video output only.
\r
834 3d6h index 64h (R/W): Alternate Vertical Total (82c455/6/7, 655x0 only)
\r
835 bit 0-7 Alternate Vertical Total
\r
836 Note: For Flat Panel modes this register replaces the Vertical
\r
837 Total Register (3d4h index 6).
\r
839 3d6h index 65h (R/W): Alternate Overflow (82c455/6/7, 655x0 only)
\r
840 bit 0 Alternate Vertical Total bit 8
\r
841 1 (455/6/7) Alternate Vertical Display End bit 8.
\r
842 (655x0) Alternate Vertical Panel Size bit 8.
\r
843 2 Alternate Vertical Sync Start bit 8.
\r
844 3 (655x0) Alternate Vertical Sync Start bit 10.
\r
845 4 (655x0) Alternate Vertical Total bit 10.
\r
846 5 Alternate Vertical Total bit 9
\r
847 6 (455/6/7) Alternate Vertical Display End bit 9.
\r
848 (655x0) Alternate Vertical Panel Size bit 9.
\r
849 7 Alternate Vertical Sync Start bit 9.
\r
851 3d6h index 66h (R/W): Alternate Vertical Sync Start (82c455/6/7, 655x0 only)
\r
852 bit 0-7 Alternate Vertical Sync Start
\r
853 Note: For Flat Panel modes this register replaces the Vertical
\r
854 Sync Start Register (3d4h index 10h).
\r
856 3d6h index 67h (R/W): Alternate Vertical Sync End (82c455/6/7, 655x0 only)
\r
857 bit 0-3 Alternate Vertical Sync End
\r
858 Note: For Flat Panel modes this register replaces the Vertical
\r
859 Sync End Register (3d4h index 11h).
\r
861 3d6h index 68h (R/W): Alternate Vertical Display Enable (82c455/6/7 only)
\r
862 bit 0-7 Alternate Vertical Display Enable
\r
863 Note: For Flat Panel modes this register replaces the Vertical
\r
864 Display Enable Register (3d4h index 12h)
\r
866 3d6h index 69h (R/W): Vertical Panel Size Register. (655x0 only)
\r
867 bit 0-7 Vertical Panel Size.
\r
868 Number of scan lines per frame.
\r
870 3d6h index 69h (R/W): Flat Panel Vertical Display Start_350 (82c455/6/7 only)
\r
871 bit 0-7 For 350 line Flat Panel modes these are the lower 8 bits of the
\r
872 Vertical Display Start (in scanlines). The upper 2 bits are in the
\r
873 Flat Panel Vertical Overflow 2 Register (3d6h index 6Bh) bits 0-1.
\r
875 3d6h index 6Ah (R/W): Flat Panel Vertical Display End_350 (82c455/6/7 only)
\r
876 bit 0-7 For 350 line Flat Panel modes these are the lower 8 bits of the
\r
877 Vertical Display End (in scanlines). The upper 2 bits are in the
\r
878 Flat Panel Vertical Overflow 2 Register (3d6h index 6Bh) bits 4-5.
\r
880 3d6h index 6Bh (R/W): Flat Panel Vertical Overflow 2 (82c455/6/7 only)
\r
881 bit 0-1 Bits 8-9 of the Vertical Display Start_350 Register
\r
883 2-3 Bits 8-9 of the Vertical Display Start_400 Register (3d6h index 5Ah
\r
884 4-5 Bits 8-9 of the Vertical Display End_350 Register (3d6h index 6Ah)
\r
885 6-7 Bits 8-9 of the Vertical Display End_400 Register (3d6h index 5Bh)
\r
887 3d6h index 6Ch (R/W): Weight Clock Control Register (82c455/6/7 only)
\r
888 bit 0-5 Weight Clock Control Pulse Count.
\r
889 Total number of pulses on the Weight Clock.
\r
890 See Also 3d6h index 5Ch and 5Dh.
\r
892 3d6h index 6Ch (R/w): Programmable Output Drive Register (655x0 only)
\r
893 bit 0 Input Level Sense Selection Mode.
\r
894 If set bit 1 is used to determine input threshold.
\r
895 If clear chip detects VCC voltage internally.
\r
896 1 Input Level Sense Selection Voltage.
\r
897 If set VCC for internal logic is 3.3V
\r
899 2 Flat Panel Interface Output Drive Select
\r
900 If set Higher drive, if clear Lower drive.
\r
901 3 Bus Interface Output Drive Select.
\r
902 If set Higher drive, if clear Lower drive.
\r
903 4 Memory Interface output Drive Select.
\r
904 If set Higher drive, if clear Lower drive.
\r
906 3d6h index 6Dh (R/W): FRC and Palette Control (82c456/7 Only)
\r
907 bit 3 Enable Frame Rate Control
\r
908 4-5 Maximum number of gray levels.
\r
910 1: 16 level FRC with dither for 256 color modes.
\r
911 2: 64 level FRC with dither for low gray levels.
\r
912 3: 16 level FRC only.
\r
913 6-7 Usage of External Palette:
\r
915 1: Bypass for 16 color modes, use for 256 color.
\r
917 3: 16 grays for 16 color modes, 64 for 256 color.
\r
919 3d6h index 6Eh (R/W): Polynomial FRC Control (82c456/7, 655x0 Only)
\r
920 bit 0-3 Polynomial N value for Frame Rate Control
\r
921 4-7 Polynomial M value.
\r
923 3d6h index 6Fh (R/W): Frame Buffer Control register (655x0 only)
\r
924 bit 0 Frame Buffer Enable.
\r
925 External Frame Buffer enabled if set.
\r
926 1 Frame Accelerator enabled if set.
\r
927 2 Frame Buffer memory Type.
\r
928 If set Frame Buffer consists of 256Kx4 VRAM.
\r
929 If clear Frame Buffer consists of 64Kx4 VRAM
\r
930 3-5 Frame Buffer Refresh Count.
\r
931 6-7 Reserved. Must be set to 0.
\r
932 Note: This register effective in Flat Panel mode only.
\r
934 3d6h index 70h (R/W): Setup/Disable Control Register. (655x0 only)
\r
935 bit 7 3C3/46E8 Register Disabled if set.
\r
937 3d6h index 7Dh (R/W): FP Compensation Diagnostic Register (655x0 only)
\r
938 bit 0-7 Reserved. returns 0.
\r
940 3d6h index 7Eh (R/W): CGA Color Select
\r
941 This is a copy of the CGA Color Select Register at 3D9h.
\r
942 The copy at 3D9h is only visible in CGA emulation mode.
\r
943 This register is always visible.
\r
945 3d6h index 7Fh (R/W): Diagnostic
\r
946 bit 0 if set 3-states pins: PALRD/, PALWR/, WR46E8/, HSYNC, VSYNC,
\r
947 ACDCLK, BLANK/, P0-7, RDY, DATEN/ AND IRQ/.
\r
948 1 If set 3-states pins: WE/, RAS/, CAS0/, CAS1/,
\r
949 CAS2/, CAS3/, AA0-7 AND BA0-7.
\r
950 2-5 Test Function Pins. Should be 0.
\r
951 6 (655x0) Test Function Enabled if set.
\r
952 7 (655x0) Special Test Function. Should be set to 0.
\r
954 46E8h (R/W): Setup Control PC/AT Register
\r
956 3 Enables Adapter VGA if set
\r
957 4 Enters Setup Mode if set
\r
959 Note: This is the same register as 94h.
\r
962 Most every index of 3d6h is used by one one or more chip.
\r
966 Bank switching is dependent on Chip version:
\r
968 16 color modes 256 color modes
\r
969 Chip #bank regs #Banks Granularity #banks Granularity
\r
970 82c451/5/6 1 4 64Kbytes
\r
971 82c452 2 64 4Kbytes 64 16Kbytes
\r
972 82c453 2 256 1Kbytes 256 4Kbytes
\r
974 For the 82c452 & 3 the window to display memory can start on
\r
975 any boundary fitting the granularity of the chip/display mode.
\r
976 When using 2 bankregisters, the address range available to the
\r
977 adapter is split equally between the two bank registers. I.e.
\r
978 A000h-A7FFh uses one bank, and A800h-AFFFh the other.
\r
979 (Or A000h-AFFFh and B000h-BFFFh respectively if using the full
\r
984 ID Chips and Technologies Chip Set:
\r
990 0:Chip&Tech 82c451 !!!
\r
991 1:Chip&Tech 82c452 !!!
\r
992 2:Chip&Tech 82c455 !!!
\r
993 3:Chip&Tech 82c453 !!!
\r
994 5:Chip&Tech 82c456 !!!
\r
995 6:Chip&Tech 82c457 !!!
\r
996 7:Chip&Tech F65520 !!!
\r
997 8:Chip&Tech F65530 !!!
\r
1004 60h T 132 25 16 (8x16)
\r
1005 61h T 132 50 16 (8x8)
\r
1006 6Ah G 800 600 16 planar
\r
1007 70h G 800 600 16 planar
\r
1008 71h G 960 720 16 planar Cardinal only!
\r
1009 72h G 1024 768 16 planar
\r
1010 78h G 640 400 256 packed Not documented/not all boards
\r
1011 79h G 640 480 256 packed
\r
1012 7Ah G 720 540 256 packed Not documented/not all boards
\r
1013 7Bh G 800 600 256 packed
\r
1014 7Ch G 800 600 256 packed (82c453 Only)
\r
1015 7Eh G 1024 768 256 packed (82c453 Only)
\r
1018 ----------105F00-----------------------------
\r
1019 INT 10 - Get Controller Information (Chips and Technologies Super VGA)
\r
1021 Return: AL = 5F If extended VGA control function supported
\r
1029 Bits 0-3: Revision Number
\r
1030 BH = Video Memory Size
\r
1034 CX = Miscellaneous Information
\r
1035 Bit 0 Dac Size. 0=6bit, 1=8bit
\r
1036 1 System Environment. 0=PC/AT, 1=PS/2
\r
1037 2 Extended text modes supported by BIOS
\r
1039 4 Extended graphics modes supported by BIOS
\r
1041 6 Graphics Cursor supported by BIOS
\r
1042 7 Anti Alias font supported by BIOS
\r
1043 8 Preprogrammed emulation supported by BIOS
\r
1044 9 Auto emulation supported by BIOS
\r
1045 10 Variable mode set at cold boot supported by BIOS
\r
1046 11 Variable mode set at warm boot supported by BIOS
\r
1047 12 Emulation mode set at cold boot supported by BIOS
\r
1048 13 Emulation mode set at warm boot supported by BIOS
\r
1050 ----------105F01-----------------------------
\r
1051 INT 10 - Set Emulation Mode (Chips and Technologies Super VGA)
\r
1053 BL = Operation Mode
\r
1055 2 Enable CGA Emulation
\r
1056 3 Enable MDA Emulation
\r
1057 4 Enable Hercules Emulation
\r
1058 5 Enable EGA Emulation
\r
1059 6 Enable VGA Emulation
\r
1060 Return: AL = 5Fh If function supported
\r
1061 AH = Return Status
\r
1062 1 If Function Successful, 0 else
\r
1063 ----------105F02-----------------------------
\r
1064 INT 10 - Auto Emulation Control (Chips and Technologies Super VGA)
\r
1065 AX = 5F02h Auto Emulation Control
\r
1067 0= Enable Auto Emulation
\r
1068 1= Disable Auto Emulation
\r
1069 Return: AL = 5Fh If function supported
\r
1070 AH = Return Status
\r
1071 1 If Function Successful, 0 else
\r
1072 ----------105F03-----------------------------
\r
1073 INT 10 - Set Power-on Video Configuration (Chips and Technologies Super VGA)
\r
1075 BL = Configuration
\r
1076 0: Set display mode as specified in the CX register
\r
1080 CH=Bits 0-1 Scanlines
\r
1085 0= Reset after next boot
\r
1086 1= Set until changed
\r
1088 1: Set Emulation mode as specified in the CX register
\r
1091 CL=Emulation Mode (See 5F01h)
\r
1092 CH=Bit 7 Performance
\r
1093 0= Reset after next boot
\r
1094 1= Set until changed
\r
1096 Return: AL = 5Fh If function supported
\r
1097 AH = Return Status
\r
1098 1 If Function Successful, 0 else
\r
1099 ----------105F90-----------------------------
\r
1100 INT 10 - Return Save/Restore buffer size (Chips and Technologies Super VGA)
\r
1103 Bit 0 Save/Restore video hardware
\r
1104 1 Save/Restore BIOS data state
\r
1105 2 Save/Restore DAC state
\r
1106 15 Save/Restore type
\r
1107 0= Save/Restore All state information
\r
1108 1= Save/Restore super state information
\r
1110 Return: AL = 5Fh If function supported
\r
1111 BX = Number of 64byte blocks required
\r
1112 ----------105F91-----------------------------
\r
1113 INT 10 - Save State (Chips and Technologies Super VGA)
\r
1116 Bit 0 Save video hardware
\r
1117 1 Save BIOS data state
\r
1120 0= Save All state information
\r
1121 1= Save super state information
\r
1122 ES:BX -> Buffer to save in.
\r
1123 Return: AL = 5Fh If function supported
\r
1124 ----------105F92-----------------------------
\r
1125 INT 10 - Restore State (Chips and Technologies Super VGA)
\r
1128 Bit 0 Restore video hardware
\r
1129 1 Restore BIOS data state
\r
1130 2 Restore DAC state
\r
1132 0= Restore All state information
\r
1133 1= Restore super state information
\r
1134 ES:BX -> Buffer to restore from.
\r
1135 Return: AL = 5Fh If function supported
\r
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