16/tweak16/REGISTER.CPP

   1 /*\r
   2         Register.CPP version 1.0\r
   3         by Robert Schmidt of Ztiff Zox Softwear 1993\r
   4 \r
   5         Defines the member functions of the Register class declared in\r
   6                 Register.hpp.\r
   7         Defines the stream operators >> and << to read and write register\r
   8                 info from istreams/to ostreams in *binary* format.\r
   9 */\r
  10 \r
  11 #include <dos.h>\r
  12 #include <iostream.h>\r
  13 #include "Register.hpp"\r
  14 \r
  15 \r
  16 /*\r
  17         Register::out()\r
  18                 Outputs the Register.value to the correct port/index.\r
  19                 It takes care of handling recognized special cases, like some\r
  20                 VGA ports, correctly.\r
  21 */\r
  22 \r
  23 void Register::out()\r
  24         {\r
  25         switch (port)\r
  26                 {\r
  27                 // First handle special cases:\r
  28 \r
  29                 case ATTRCON_ADDR:\r
  30                         inportb(STATUS_ADDR);           // reset read/write flip-flop\r
  31                         outportb(ATTRCON_ADDR, index);\r
  32                         outportb(ATTRCON_ADDR, value);\r
  33                         break;\r
  34 \r
  35                 case SEQ_ADDR:\r
  36                         if (index == 1)\r
  37                                 {\r
  38                                 // Reset the sequencer if the clock polarity settings\r
  39                                 //  are being accessed.\r
  40                                 outport(SEQ_ADDR, 0x0100);\r
  41                                 outport(SEQ_ADDR, value<<8 | 1);\r
  42                                 outport(SEQ_ADDR, 0x0300);\r
  43                                 break;\r
  44                                 }\r
  45                 case GRACON_ADDR:\r
  46                 case CRTC_ADDR:\r
  47                 case CHIPSTECH:\r
  48                         outport(port, index | value<<8);\r
  49                         break;\r
  50 \r
  51                 case MISC_ADDR:\r
  52                 case VGAENABLE_ADDR:\r
  53                 default:                                                // Default is to write the byte\r
  54                         outportb(port, value);          //      directly to the port\r
  55                         break;\r
  56                 }\r
  57         }\r
  58 \r
  59 /*\r
  60         Register::in()\r
  61                 Inputs Register.value to the associated hardware register.\r
  62                 It takes care of handling recognized special cases,\r
  63                 like some VGA ports, correctly.\r
  64 */\r
  65 \r
  66 unsigned char Register::in()\r
  67         {\r
  68         switch (port)\r
  69                 {\r
  70                 // First handle special cases:\r
  71 \r
  72                 case MISC_ADDR:\r
  73                         value = inportb(0x3cc);         // 0x3c2 is write-only, reading\r
  74                                                                                 // must be mapped to 0x3cc\r
  75                         break;\r
  76 \r
  77                 case ATTRCON_ADDR:                              // This 1 is odd.  First do a read to\r
  78                         inportb(STATUS_ADDR);           //      reset the index/data flip-flop.\r
  79                                                                                 //      Then give it the index, but:\r
  80                                                                                 //      set bit 5!  If cleared, VGA\r
  81                                                                                 //      output is disabled!\r
  82                         outportb(ATTRCON_ADDR, index);\r
  83                         value = inportb(ATTRCON_ADDR+1);\r
  84                         break;\r
  85 \r
  86                 case SEQ_ADDR:                                  // These 3 are similar.  Give it the\r
  87                 case GRACON_ADDR:                               //      register index, then read the\r
  88                 case CRTC_ADDR:                                 //      byte from port+1.\r
  89                 case CHIPSTECH:\r
  90                         outportb(port, index);\r
  91                         value = inportb(port+1);\r
  92                         break;\r
  93 \r
  94                 case VGAENABLE_ADDR:\r
  95                 default:                        // Default is to read the byte\r
  96                         value = inportb(port);          //      directly from the port\r
  97                         break;\r
  98                 }\r
  99 \r
 100         return value;                                                   // Return value of first reg.\r
 101         }\r
 102 \r
 103 /*\r
 104         The following stream operators operate on Registers in *binary*\r
 105         format, i.e. they are not suitable for communicating with text streams\r
 106         like the keyboard or the screen (cin/cout).\r
 107 */\r
 108 \r
 109 istream& operator>> (istream &in, Register &r)\r
 110         {\r
 111         r.port = unsigned(in.get()) | (unsigned(in.get()) << 8);\r
 112         r.index = in.get();\r
 113         r.value = in.get();\r
 114 \r
 115         return in;\r
 116         }\r
 117 \r
 118 ostream& operator<< (ostream &out, Register &r)\r
 119         {\r
 120         out.put(char(r.port));\r
 121         out.put(char(r.port>>8));\r
 122         out.put(r.index);\r
 123         out.put(r.value);\r
 124 \r
 125         return out;\r
 126         }\r
 127 \r
 128 \r
 129 \r