7 #define ATTRCON_ADDR 0x3C0
\r
8 #define MISC_ADDR 0x3C2
\r
9 #define VGAENABLE_ADDR 0x3C3
\r
10 #define SEQU_ADDR 0x3C4
\r
11 #define GRACON_ADDR 0x3CE
\r
12 #define CRTC_ADDR 0x3D4
\r
13 #define STATUS_ADDR 0x3DA
\r
15 unsigned short width, height, widthBytes, num_pages;
\r
16 unsigned short pageSize, activeStart, visibleStart;
\r
17 unsigned char write_plane, read_plane;
\r
18 unsigned char *RowsX[600];
\r
19 unsigned char line_head[4] = { 0xFF, 0x0E, 0x0C, 0x08 };
\r
20 unsigned char line_tail[4] = { 0x00, 0x01, 0x03, 0x07 };
\r
21 unsigned short plane_mask[4] = { PLANE_0, PLANE_1, PLANE_2, PLANE_3 };
\r
22 unsigned short read_mask[4] = { READ_PLANE_0, READ_PLANE_1,
\r
23 READ_PLANE_2, READ_PLANE_3 };
\r
24 unsigned short text_mask[16] = { 0x0002, 0x0102, 0x0202, 0x0302,
\r
25 0x0402, 0x0502, 0x0602, 0x0702,
\r
26 0x0802, 0x0902, 0x0A02, 0x0B02,
\r
27 0x0C02, 0x0D02, 0x0E02, 0x0F02 };
\r
28 unsigned short page_offset[5];
\r
29 unsigned short page_mask_high[5];
\r
30 unsigned short page_mask_low[5];
\r
33 unsigned short ModeX_256x224regs[75] =
\r
62 unsigned short ModeX_256x240regs[75] =
\r
91 unsigned short ModeX_256x256regs[75] =
\r
120 unsigned short ModeX_256x480regs[75] =
\r
149 unsigned short ModeX_320x200regs[75] =
\r
178 unsigned short ModeX_320x240regs[75] =
\r
207 unsigned short ModeX_320x400regs[75] =
\r
236 unsigned short ModeX_320x480regs[75] =
\r
265 unsigned short ModeX_360x200regs[75] =
\r
294 unsigned short ModeX_360x240regs[75] =
\r
323 unsigned short ModeX_360x270regs[75] =
\r
352 unsigned short ModeX_360x360regs[75] =
\r
381 unsigned short ModeX_360x400regs[75] =
\r
410 unsigned short ModeX_360x480regs[75] =
\r
439 unsigned short ModeX_376x282regs[75] =
\r
468 unsigned short ModeX_376x564regs[75] =
\r
497 unsigned short ModeX_400x300regs[78] =
\r
527 unsigned short ModeX_400x600regs[78] =
\r
563 // Each byte addresses four pixels, so the width of a scan line
\r
564 // in *bytes* is one fourth of the number of pixels on a line.
\r
565 widthBytes = width / 4;
\r
567 pageSize = (widthBytes * height);
\r
569 for (i=0; i < height; i++) {
\r
570 RowsX[i] = (unsigned char *)((0xA000 << 4) + (widthBytes * i));
\r
573 // Clear entire video memory, by selecting all four planes, then
\r
574 // writing 0 to entire segment.
\r
575 outpw(SEQU_ADDR, ALL_PLANES);
\r
576 memset((unsigned char *)(0xA000 << 4), 0x00, 0x00010000);
\r
578 // By default we want screen refreshing and drawing operations
\r
579 // to be based at offset 0 in the video segment.
\r
580 activeStart = visibleStart = 0;
\r
582 // Set current plane to invalid value
\r
586 // How many pages fit in 256K VGA Card?
\r
587 num_pages = ((64 * 1024) / pageSize);
\r
589 for (i=0; i < num_pages; i++) {
\r
590 page_offset[i] = (pageSize * i);
\r
591 page_mask_high[i] = (0x0C | (page_offset[i] & 0xFF00));
\r
592 page_mask_low[i] = (0x0D | ((page_offset[i] & 0x00FF) << 8));
\r
597 // setBaseXMode() does the initialization to make the VGA ready to
\r
598 // accept any combination of configuration register settings. This
\r
599 // involves enabling writes to index 0 to 7 of the CRT controller (port
\r
600 // 0x3D4), by clearing the most significant bit (bit 7) of index 0x11.
\r
608 int386(0x10, &r, &r);
\r
611 temp = inp(0x3D5) & 0x7F;
\r
618 outReg(unsigned short *r)
\r
621 // First handle special cases:
\r
624 // reset read/write flip-flop
\r
626 outp(ATTRCON_ADDR, r[1] | 0x20);
\r
627 // ensure VGA output is enabled
\r
628 outp(ATTRCON_ADDR, r[2]);
\r
632 case VGAENABLE_ADDR:
\r
633 // Copy directly to port
\r
644 outp(r[0] + 1, r[2]);
\r
650 outRegArray(unsigned short *r, int n)
\r
665 int386(0x10, &r, &r);
\r
669 set256x224x256_X(void)
\r
672 outRegArray(ModeX_256x224regs, 25);
\r
681 set256x240x256_X(void)
\r
684 outRegArray(ModeX_256x240regs, 25);
\r
693 set256x256x256_X(void)
\r
696 outRegArray(ModeX_256x256regs, 25);
\r
705 set256x480x256_X(void)
\r
708 outRegArray(ModeX_256x480regs, 25);
\r
717 set320x200x256_X(void)
\r
720 outRegArray(ModeX_320x200regs, 25);
\r
729 set320x240x256_X(void)
\r
732 outRegArray(ModeX_320x240regs, 25);
\r
741 set320x400x256_X(void)
\r
744 outRegArray(ModeX_320x400regs, 25);
\r
753 set320x480x256_X(void)
\r
756 outRegArray(ModeX_320x480regs, 25);
\r
765 set360x200x256_X(void)
\r
768 outRegArray(ModeX_360x200regs, 25);
\r
777 set360x240x256_X(void)
\r
780 outRegArray(ModeX_360x240regs, 25);
\r
789 set360x270x256_X(void)
\r
792 outRegArray(ModeX_360x270regs, 25);
\r
801 set360x360x256_X(void)
\r
804 outRegArray(ModeX_360x360regs, 25);
\r
813 set360x400x256_X(void)
\r
816 outRegArray(ModeX_360x400regs, 25);
\r
825 set360x480x256_X(void)
\r
828 outRegArray(ModeX_360x480regs, 25);
\r
837 set376x282x256_X(void)
\r
840 outRegArray(ModeX_376x282regs, 25);
\r
849 set376x564x256_X(void)
\r
852 outRegArray(ModeX_376x564regs, 25);
\r
861 set400x300x256_X(void)
\r
864 outRegArray(ModeX_400x300regs, 26);
\r
873 set400x600x256_X(void)
\r
876 outRegArray(ModeX_400x600regs, 26);
\r
900 set_write_plane(unsigned short int plane_mask)
\r
903 outpw(SEQU_ADDR, plane_mask);
\r
908 set_read_plane(unsigned short int plane_mask)
\r
911 outpw(GRACON_ADDR, plane_mask);
\r