- gv->video.page[0].sw=120;\r
- gv->video.page[0].sh=160;\r
-\r
- /* send the CRTParms */\r
- for(i=0; i<CRTParmCount; i++) {\r
- outpw(CRTC_INDEX, ModeX_160x120regs[i]);\r
- }\r
-\r
- /* clear video memory */\r
- outpw(SC_INDEX, 0x0f02);\r
- for(i=0; i<0x8000; i++) {\r
- ptr[i] = 0x0000;\r
- }\r
- break;\r
- case 3:\r
- CRTParmCount = sizeof(ModeX_320x200regs) / sizeof(ModeX_320x200regs[0]);\r
- /* width and height */\r
- gv->video.page[0].sw=320;\r
- gv->video.page[0].sh=200;\r
-\r
- /* send the CRTParms */\r
- for(i=0; i<CRTParmCount; i++) {\r
- outpw(CRTC_INDEX, ModeX_320x200regs[i]);\r
- }\r
-\r
- /* clear video memory */\r
- outpw(SC_INDEX, 0x0f02);\r
- for(i=0; i<0x8000; i++) {\r
- ptr[i] = 0x0000;\r
- }\r
- break;\r
- case 4:\r
- CRTParmCount = sizeof(ModeX_192x144regs) / sizeof(ModeX_192x144regs[0]);\r
- /* width and height */\r
- gv->video.page[0].sw=192;\r
- gv->video.page[0].sh=144;\r
-\r
- /* send the CRTParms */\r
- for(i=0; i<CRTParmCount; i++) {\r
- outpw(CRTC_INDEX, ModeX_192x144regs[i]);\r
- }\r
-\r
- /* clear video memory */\r
- outpw(SC_INDEX, 0x0f02);\r
- for(i=0; i<0x8000; i++) {\r
- ptr[i] = 0x0000;\r
- }\r
- break;\r
- case 5:\r
- CRTParmCount = sizeof(ModeX_256x192regs) / sizeof(ModeX_256x192regs[0]);\r
- /* width and height */\r
- gv->video.page[0].sw=256;\r
- gv->video.page[0].sh=192;\r
+ gv->video.page[0].sw = vga_state.vga_width = 320; // VGA lib currently does not update this\r
+ gv->video.page[0].sh = vga_state.vga_height = 240; // VGA lib currently does not update this\r
+\r
+ // mode X BYTE mode\r
+ cm.word_mode = 0;\r
+ cm.dword_mode = 0;\r
+ // 320x240 mode 60Hz\r
+ cm.horizontal_total=0x5f + 5; /* CRTC[0] -5 */\r
+ cm.horizontal_display_end=0x4f + 1; /* CRTC[1] -1 */\r
+ cm.horizontal_blank_start=0x50 + 1; /* CRTC[2] */\r
+ cm.horizontal_blank_end=0x82 + 1; /* CRTC[3] bit 0-4 & CRTC[5] bit 7 */\r
+ cm.horizontal_start_retrace=0x54;/* CRTC[4] */\r
+ cm.horizontal_end_retrace=0x80; /* CRTC[5] bit 0-4 */\r
+ //cm.horizontal_start_delay_after_total=0x3e; /* CRTC[3] bit 5-6 */\r
+ //cm.horizontal_start_delay_after_retrace=0x41; /* CRTC[5] bit 5-6 */\r
+ cm.vertical_total = 0x20D + 2;\r
+ cm.vertical_start_retrace = 0x1EA;\r
+ cm.vertical_end_retrace = 0x1EC;\r
+ cm.vertical_display_end = 480;\r
+ cm.vertical_blank_start = 0x1E7 + 1;\r
+ cm.vertical_blank_end = 0x206 + 1;\r
+ cm.clock_select = 0; /* misc register = 0xE3 25MHz */\r
+ cm.vsync_neg = 1;\r
+ cm.hsync_neg = 1;\r
+ cm.offset = (vga_state.vga_width / (4 * 2)); // 320 wide (40 x 4 pixel groups x 2)\r
+ break;\r
+ case 2: // TODO: 160x120 according to ModeX_160x120regs\r
+ return;\r
+ case 3: // TODO: 160x120 according to ModeX_320x200regs\r
+ return;\r
+ case 4: // TODO: 160x120 according to ModeX_192x144regs\r
+ return;\r
+ case 5: // TODO: 160x120 according to ModeX_256x192regs\r
+ return;\r
+ default:\r
+ return;\r
+ }\r