+ /* clear video memory */\r
+ outpw(SC_INDEX, 0x0f02);\r
+ for(i=0; i<0x8000; i++) {\r
+ ptr[i] = 0x0000;\r
+ }\r
+ break;\r
+ case 2:\r
+ CRTParmCount = sizeof(ModeX_192x144regs) / sizeof(ModeX_192x144regs[0]);\r
+ /* width and height */\r
+ gv->video.page[0].sw=192;\r
+ gv->video.page[0].sh=144;\r
+\r
+ /* send the CRTParms */\r
+ for(i=0; i<CRTParmCount; i++) {\r
+ outpw(CRTC_INDEX, ModeX_192x144regs[i]);\r
+ }\r
+\r
+ /* clear video memory */\r
+ outpw(SC_INDEX, 0x0f02);\r
+ for(i=0; i<0x8000; i++) {\r
+ ptr[i] = 0x0000;\r
+ }\r
+ break;\r
+ case 3:\r
+ CRTParmCount = sizeof(ModeX_320x200regs) / sizeof(ModeX_320x200regs[0]);\r
+ /* width and height */\r
+ gv->video.page[0].sw=320;\r
+ gv->video.page[0].sh=200;\r
+\r
+ /* send the CRTParms */\r
+ for(i=0; i<CRTParmCount; i++) {\r
+ outpw(CRTC_INDEX, ModeX_320x200regs[i]);\r
+ }\r
+\r
+ /* clear video memory */\r
+ outpw(SC_INDEX, 0x0f02);\r
+ for(i=0; i<0x8000; i++) {\r
+ ptr[i] = 0x0000;\r
+ }\r
+ break;\r
+ case 5:\r
+ CRTParmCount = sizeof(ModeX_256x192regs) / sizeof(ModeX_256x192regs[0]);\r
+ /* width and height */\r
+ gv->video.page[0].sw=256;\r
+ gv->video.page[0].sh=192;\r
+\r
+ /* send the CRTParms */\r
+ for(i=0; i<CRTParmCount; i++) {\r
+ outpw(CRTC_INDEX, ModeX_256x192regs[i]);\r
+ }\r
+\r
+ /* clear video memory */\r
+ outpw(SC_INDEX, 0x0f02);\r
+ for(i=0; i<0x8000; i++) {\r
+ ptr[i] = 0x0000;\r
+ }\r
+ break;\r
+ }\r
+ gv->video.page[0].tilesw = gv->video.page[0].sw/TILEWH;\r
+ gv->video.page[0].tilesh = gv->video.page[0].sh/TILEWH;\r
+ //TODO MAKE FLEXIBLE~\r
+ gv->video.page[0].tilemidposscreenx = gv->video.page[0].tilesw;\r
+ gv->video.page[0].tilemidposscreeny = (gv->video.page[0].tilesh/2)+1;\r
+ #define PAGE_SIZE (word)(gv->video.page[0].sw/4 * gv->video.page[0].sh)\r
+}\r
+\r
+void\r
+modexLeave() {\r
+ /* TODO restore original mode and palette */\r
+ vgaSetMode(TEXT_MODE);\r
+}\r
+\r
+// setBaseXMode() does the initialization to make the VGA ready to\r
+// accept any combination of configuration register settings. This\r
+// involves enabling writes to index 0 to 7 of the CRT controller (port\r
+// 0x3D4), by clearing the most significant bit (bit 7) of index 0x11.\r
+void\r
+modexsetBaseXMode(page_t *page)\r
+{\r
+ word temp;\r