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[16.git] / 16 / intro / MXORG.ASC

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+Figure 2: Memory organization in unchained 256-color modes (like\r
+          Mode X) (ASCII version)\r
+         by Robert Schmidt\r
+          (C) 1993 Ztiff Zox Softwear\r
+\r
+\r
+Imagine that the screen looks the same as in figure 1a.  A screen width\r
+of 320 pixels is still assumed.\r
+\r
+In VGA memory, the screen will be represented as follows:\r
+\r
+   Plane 0:\r
+\r
+    address:  0         10                70       79 (NOT 319!)\r
+             ----------------------------------------\r
+             |0482604826048260    .....   0482604826|\r
+             |                                      |\r
+             |                                      |\r
+\r
+   Plane 1:\r
+\r
+    address:  0         10                70       79\r
+             ----------------------------------------\r
+             |1593715937159371    .....   1593715937|\r
+             |                                      |\r
+             |                                      |\r
+\r
+   Plane 2:\r
+\r
+    address:  0         10                70       79\r
+             ----------------------------------------\r
+             |2604826048260482    .....   2604826048|\r
+             |                                      |\r
+             |                                      |\r
+\r
+   Plane 3:\r
+\r
+    address:  0         10                70       79\r
+             ----------------------------------------\r
+             |3715937159371593    .....   3715937159|\r
+             |                                      |\r
+             |                                      |\r
+\r
+Note that if pixel i is in plane p, pixel i+1 is in plane (p+1)%4.\r
+When the planes are unchained, we need to set the Write Plane Enable\r
+register to select which planes should receive the data when writing,\r
+or the Read Plane Select register when reading.  As is evident, one \r
+address in the video segment provides access to no less than FOUR\r
+different pixels.\r