// setvideo() - This function Manages the video modes //\r
// //\r
/////////////////////////////////////////////////////////////////////////////\r
-void VGAmodeX(sword vq, boolean cm, global_game_variables_t *gv)\r
+void VGAmodeX(sword vq, boolean cmem, global_game_variables_t *gv)\r
{\r
union REGS in, out;\r
\r
//int86(0x10, &in, &out);\r
gv->video.old_mode = vgaGetMode();//out.h.al;\r
// enter mode\r
- modexEnter(vq, cm, gv);\r
+ modexEnter(vq, cmem, gv);\r
break;\r
}\r
}\r
}\r
\r
/* -========================= Entry Points ==========================- */\r
-void modexEnter(sword vq, boolean cm, global_game_variables_t *gv)\r
+void modexEnter(sword vq, boolean cmem, global_game_variables_t *gv)\r
{\r
word i;\r
dword far*ptr=(dword far*)VGA; /* used for faster screen clearing */\r
+ struct vga_mode_params cm;\r
int CRTParmCount;\r
- /* common mode X initiation stuff~ */\r
- modexsetBaseXMode(gv->video.page);\r
+\r
+ vgaSetMode(VGA_256_COLOR_MODE);\r
+ vga_enable_256color_modex();\r
+ update_state_from_vga();\r
+ vga_read_crtc_mode(&cm);\r
\r
switch(vq)\r
{\r
case 1:\r
- CRTParmCount = sizeof(ModeX_320x240regs) / sizeof(ModeX_320x240regs[0]);\r
- /* width and height */\r
- gv->video.page[0].sw=320;\r
- gv->video.page[0].sh=240;\r
-\r
- /* send the CRTParms */\r
- for(i=0; i<CRTParmCount; i++) {\r
- outpw(CRTC_INDEX, ModeX_320x240regs[i]);\r
- }\r
- break;\r
- case 2:\r
- CRTParmCount = sizeof(ModeX_160x120regs) / sizeof(ModeX_160x120regs[0]);\r
- /* width and height */\r
- gv->video.page[0].sw=120;\r
- gv->video.page[0].sh=160;\r
-\r
- /* send the CRTParms */\r
- for(i=0; i<CRTParmCount; i++) {\r
- outpw(CRTC_INDEX, ModeX_160x120regs[i]);\r
- }\r
- break;\r
- case 3:\r
- CRTParmCount = sizeof(ModeX_320x200regs) / sizeof(ModeX_320x200regs[0]);\r
- /* width and height */\r
- gv->video.page[0].sw=320;\r
- gv->video.page[0].sh=200;\r
-\r
- /* send the CRTParms */\r
- for(i=0; i<CRTParmCount; i++) {\r
- outpw(CRTC_INDEX, ModeX_320x200regs[i]);\r
- }\r
- break;\r
- case 4:\r
- CRTParmCount = sizeof(ModeX_192x144regs) / sizeof(ModeX_192x144regs[0]);\r
- /* width and height */\r
- gv->video.page[0].sw=192;\r
- gv->video.page[0].sh=144;\r
-\r
- /* send the CRTParms */\r
- for(i=0; i<CRTParmCount; i++) {\r
- outpw(CRTC_INDEX, ModeX_192x144regs[i]);\r
- }\r
- break;\r
- case 5:\r
- CRTParmCount = sizeof(ModeX_256x192regs) / sizeof(ModeX_256x192regs[0]);\r
+ //CRTParmCount = sizeof(ModeX_320x240regs) / sizeof(ModeX_320x240regs[0]);\r
/* width and height */\r
- gv->video.page[0].sw=256;\r
- gv->video.page[0].sh=192;\r
-\r
- /* send the CRTParms */\r
- for(i=0; i<CRTParmCount; i++) {\r
- outpw(CRTC_INDEX, ModeX_256x192regs[i]);\r
- }\r
- break;\r
+ gv->video.page[0].sw=vga_state.vga_width = 320; // VGA lib currently does not update this\r
+ gv->video.page[0].sh=vga_state.vga_height = 240; // VGA lib currently does not update this\r
+\r
+ // 320x240 mode 60Hz\r
+ cm.horizontal_total=0x5f + 5; /* CRTC[0] -5 */\r
+ cm.horizontal_display_end=0x4f + 1; /* CRTC[1] -1 */\r
+ cm.horizontal_blank_start=0x50 + 1; /* CRTC[2] */\r
+ cm.horizontal_blank_end=0x82 + 1; /* CRTC[3] bit 0-4 & CRTC[5] bit 7 */\r
+ cm.horizontal_start_retrace=0x54;/* CRTC[4] */\r
+ cm.horizontal_end_retrace=0x80; /* CRTC[5] bit 0-4 */\r
+ //cm.horizontal_start_delay_after_total=0x3e; /* CRTC[3] bit 5-6 */\r
+ //cm.horizontal_start_delay_after_retrace=0x41; /* CRTC[5] bit 5-6 */\r
+ cm.vertical_total = 0x20D + 2;\r
+ cm.vertical_start_retrace = 0x1EA;\r
+ cm.vertical_end_retrace = 0x1EC;\r
+ cm.vertical_display_end = 480;\r
+ cm.vertical_blank_start = 0x1E7 + 1;\r
+ cm.vertical_blank_end = 0x206 + 1;\r
+ cm.clock_select = 0; /* misc register = 0xE3 25MHz */\r
+ cm.vsync_neg = 1;\r
+ cm.hsync_neg = 1;\r
+ break;\r
+ case 2: // TODO: 160x120 according to ModeX_160x120regs\r
+ return;\r
+ case 3: // TODO: 160x120 according to ModeX_320x200regs\r
+ return;\r
+ case 4: // TODO: 160x120 according to ModeX_192x144regs\r
+ return;\r
+ case 5: // TODO: 160x120 according to ModeX_256x192regs\r
+ return;\r
+ default:\r
+ return;\r
}\r
\r
+ vga_write_crtc_mode(&cm,0);\r
+\r
/* clear video memory */\r
- switch (cm)\r
+ switch (cmem)\r
{\r
case 1:\r
/* clear video memory */\r
- outpw(SC_INDEX, 0x0f02);\r
- for(i=0; i<0x8000; i++) {\r
- ptr[i] = 0x0000;\r
- }\r
+ vga_write_sequencer(2/*map mask register*/,0xf/*all 4 planes*/);\r
+ for(i=0; i<0x8000; i++) ptr[i] = 0x0000;\r
break;\r
}\r
gv->video.page[0].tilesw = gv->video.page[0].sw/TILEWH;\r
\r
void\r
modexLeave() {\r
- /* TODO restore original mode and palette */\r
- vgaSetMode(TEXT_MODE);\r
-}\r
-\r
-// setBaseXMode() does the initialization to make the VGA ready to\r
-// accept any combination of configuration register settings. This\r
-// involves enabling writes to index 0 to 7 of the CRT controller (port\r
-// 0x3D4), by clearing the most significant bit (bit 7) of index 0x11.\r
-void\r
-modexsetBaseXMode(page_t *page)\r
-{\r
- word temp;\r
- /* TODO save current video mode and palette */\r
- vgaSetMode(VGA_256_COLOR_MODE);\r
-\r
- /* disable chain4 mode */\r
- outpw(SC_INDEX, 0x0604);\r
-\r
- /* synchronous reset while setting Misc Output */\r
- outpw(SC_INDEX, 0x0100);\r
-\r
- /* select 25 MHz dot clock & 60 Hz scanning rate */\r
- outp(MISC_OUTPUT, 0xe3);\r
-\r
- /* undo reset (restart sequencer) */\r
- outpw(SC_INDEX, 0x0300);\r
-\r
- /* reprogram the CRT controller */\r
- outp(CRTC_INDEX, 0x11); /* VSync End reg contains register write prot */\r
-// temp = inp(CRTC_DATA) & 0x7F;\r
-// outp(CRTC_INDEX, 0x11);\r
- outp(CRTC_DATA, 0x7f); /* get current write protect on varios regs */\r
-// outp(CRTC_DATA, temp); /* get current write protect on varios regs */\r
+ /* TODO restore original mode and palette */\r
+ vgaSetMode(TEXT_MODE);\r
}\r
\r
page_t\r
projects / 16.git / blobdiff