{\r
union REGS in, out;\r
\r
- if(!vq)\r
- { // deinit the video\r
- // change to the video mode we were in before we switched to mode 13h\r
- modexLeave();\r
- in.h.ah = 0x00;\r
- in.h.al = gv->old_mode;\r
- int86(0x10, &in, &out);\r
-\r
- }\r
- else if(vq==1)\r
- { // init the video\r
- // get old video mode\r
- in.h.ah = 0xf;\r
- int86(0x10, &in, &out);\r
- gv->old_mode = out.h.al;\r
- // enter mode\r
- modex__320x240_256__Enter(gv);\r
+ switch (vq)\r
+ {\r
+ case 0: // deinit the video\r
+ // change to the video mode we were in before we switched to mode 13h\r
+ modexLeave();\r
+ in.h.ah = 0x00;\r
+ in.h.al = gv->old_mode;\r
+ int86(0x10, &in, &out);\r
+ break;\r
+ case 1: // init the video\r
+ // get old video mode\r
+ in.h.ah = 0xf;\r
+ int86(0x10, &in, &out);\r
+ gv->old_mode = out.h.al;\r
+ // enter mode\r
+ modex__320x240_256__Enter(gv);\r
+ break;\r
+ case 2: // init the video\r
+ // get old video mode\r
+ in.h.ah = 0xf;\r
+ int86(0x10, &in, &out);\r
+ gv->old_mode = out.h.al;\r
+ // enter mode\r
+ modex__256x192_256__Enter(gv);\r
+ break;\r
}\r
}\r
\r
{\r
word i;\r
dword far*ptr=(dword far*)VGA; /* used for faster screen clearing */\r
- word CRTParms[] = {\r
-// 0xe300, /* horizontal total */\r
-// 0x4f01, /* horizontal display enable end */\r
- 0x5002, /* */\r
- 0x5404, /* */\r
- 0x8005, /* */\r
- 0x0d06, /* vertical total */\r
- 0x3e07, /* overflow (bit 8 of vertical counts) */\r
- 0x4109, /* cell height (2 to double-scan */\r
- 0xea10, /* v sync start */\r
- 0xac11, /* v sync end and protect cr0-cr7 */\r
- 0xdf12, /* vertical displayed */\r
- 0x2813, /* offset/logical width */\r
- 0x0014, /* turn off dword mode */\r
- 0xe715, /* v blank start */\r
- 0x0616, /* v blank end */\r
- 0xe317 /* turn on byte mode */\r
- };\r
-\r
- int CRTParmCount = sizeof(CRTParms) / sizeof(CRTParms[0]);\r
+\r
+ int CRTParmCount = sizeof(ModeX_320x240regs) / sizeof(ModeX_320x240regs[0]);\r
/* width and height */\r
//TODO WWWW\r
\r
- /* disable chain4 mode */\r
- outpw(SC_INDEX, 0x0604);\r
+ /* common mode X initiation stuff~ */\r
+ modexsetBaseXMode();\r
\r
- /* synchronous reset while setting Misc Output */\r
- outpw(SC_INDEX, 0x0100);\r
+ /* send the CRTParms */\r
+ for(i=0; i<CRTParmCount; i++) {\r
+ outpw(CRTC_INDEX, ModeX_320x240regs[i]);\r
+ }\r
\r
- /* select 25 MHz dot clock & 60 Hz scanning rate */\r
- outp(MISC_OUTPUT, 0xe3);\r
+ /* clear video memory */\r
+ outpw(SC_INDEX, 0x0f02);\r
+ for(i=0; i<0x8000; i++) {\r
+ ptr[i] = 0x0000;\r
+ }\r
+}\r
\r
- /* undo reset (restart sequencer) */\r
- outpw(SC_INDEX, 0x0300);\r
+void\r
+modex__256x192_256__Enter(global_game_variables_t *gv)\r
+{\r
+ word i;\r
+ dword far*ptr=(dword far*)VGA; /* used for faster screen clearing */\r
\r
- /* reprogram the CRT controller */\r
- outp(CRTC_INDEX, 0x11); /* VSync End reg contains register write prot */\r
- outp(CRTC_DATA, 0x7f); /* get current write protect on varios regs */\r
+ int CRTParmCount = sizeof(ModeX_256x192regs) / sizeof(ModeX_256x192regs[0]);\r
+ /* width and height */\r
+ //TODO WWWW\r
+\r
+ /* common mode X initiation stuff~ */\r
+ modexsetBaseXMode();\r
\r
/* send the CRTParms */\r
for(i=0; i<CRTParmCount; i++) {\r
- outpw(CRTC_INDEX, CRTParms[i]);\r
+ outpw(CRTC_INDEX, ModeX_256x192regs[i]);\r
}\r
\r
/* clear video memory */\r
}\r
}\r
\r
+void\r
+modexLeave() {\r
+ /* TODO restore original mode and palette */\r
+ vgaSetMode(TEXT_MODE);\r
+}\r
+\r
// setBaseXMode() does the initialization to make the VGA ready to\r
// accept any combination of configuration register settings. This\r
// involves enabling writes to index 0 to 7 of the CRT controller (port\r
void\r
modexsetBaseXMode(void)\r
{\r
- int temp;\r
-\r
+ word temp;\r
/* TODO save current video mode and palette */\r
vgaSetMode(VGA_256_COLOR_MODE);\r
\r
- outp(CRTC_INDEX, 0x11);\r
- temp = inp(CRTC_DATA) & 0x7F;\r
- outp(CRTC_INDEX, 0x11);\r
- outp(CRTC_DATA, temp);\r
-}\r
+ /* disable chain4 mode */\r
+ outpw(SC_INDEX, 0x0604);\r
\r
-void\r
-modexLeave() {\r
- /* TODO restore original mode and palette */\r
- vgaSetMode(TEXT_MODE);\r
-}\r
+ /* synchronous reset while setting Misc Output */\r
+ outpw(SC_INDEX, 0x0100);\r
+\r
+ /* select 25 MHz dot clock & 60 Hz scanning rate */\r
+ outp(MISC_OUTPUT, 0xe3);\r
\r
+ /* undo reset (restart sequencer) */\r
+ outpw(SC_INDEX, 0x0300);\r
+\r
+ /* reprogram the CRT controller */\r
+ outp(CRTC_INDEX, 0x11); /* VSync End reg contains register write prot */\r
+// temp = inp(CRTC_DATA) & 0x7F;\r
+// outp(CRTC_INDEX, 0x11);\r
+ outp(CRTC_DATA, 0x7f); /* get current write protect on varios regs */\r
+// outp(CRTC_DATA, temp); /* get current write protect on varios regs */\r
+}\r
\r
page_t\r
modexDefaultPage() {\r
projects / 16.git / blobdiff