1 3C0h: Attribute Controller: Address register
\r
2 bit 0-4 Address of data register to write to port 3C0h
\r
3 or read from port 3C1h (Reads only on VGA).
\r
4 5 If set screen output is enabled and the palette can not be
\r
5 modified, if clear screen output is disabled and the palette
\r
9 Port 3C0h is special in that it is both address and data-write
\r
10 register. Data reads happen from port 3C1h. An internal
\r
11 flip-flop remembers whether it is currently acting as
\r
12 address or data register.
\r
13 Accesses to the attribute controller must be separated by
\r
15 Reading port 3dAh will reset the flip-flop to address mode.
\r
18 3C0h index 0-Fh (r/W): Attribute: Palette
\r
19 bit 0 (EGA) Primary Blue
\r
20 1 (EGA) Primary Green
\r
22 3 (EGA) Secondary Blue
\r
23 4 (EGA) Secondary Green
\r
24 5 (EGA) Secondary Red
\r
25 0-5 (VGA) Index into the 256 color DAC table.
\r
26 May be modified by 3C0h index 10h and 14h.
\r
28 3C0h index 10h (r/W): Attribute: Mode Control Register
\r
29 bit 0 Graphics mode if set, Alphanumeric mode else.
\r
30 1 Monochrome mode if set, color mode else.
\r
31 2 9-bit wide characters if set.
\r
32 The 9th bit of characters C0h-DFh will be the same as
\r
33 the 8th bit. Otherwise it will be the background color.
\r
34 3 If set Attribute bit 7 is blinking, else high intensity.
\r
35 5 (VGA Only) If set the PEL panning register (3C0h index 13h)
\r
36 is temporarily set to 0 from when the line
\r
37 compare causes a wrap around until the next
\r
38 vertical retrace when the register is automatically
\r
39 reloaded with the old value, else the PEL
\r
40 panning register ignores line compares.
\r
41 6 (VGA Only) If set pixels are 8 bits wide.
\r
42 Used in 256 color modes.
\r
43 7 (VGA Only) If set bit 4-5 of the index into the DAC table
\r
44 are taken from port 3C0h index 14h bit 0-1,
\r
45 else the bits in the palette register are used.
\r
47 3C0h index 11h (r/W): Attribute: Overscan Color Register.
\r
48 bit 0-5 Color of screen border. Color is defined as in the
\r
50 Note: The EGA requires the Overscan color to be 0 in high resolution
\r
53 3C0h index 12h (r/W): Attribute: Color Plane Enable Register
\r
54 bit 0 Bit plane 0 is enabled if set.
\r
55 1 Bit plane 1 is enabled if set.
\r
56 2 Bit plane 2 is enabled if set.
\r
57 3 Bit plane 3 is enabled if set.
\r
58 4-5 Video Status MUX. Diagnostics use only.
\r
59 Two attribute bits appear on bits 4 and 5 of the Input
\r
60 Status Register 1 (3dAh).
\r
62 0 Red/Blue Bit 2/Bit 0
\r
63 1 Blue'/Green Bit 5/Bit 4
\r
64 2 Red'/Green' Bit 3/Bit 1
\r
67 3C0h index 13h (r/W): Attribute: Horizontal PEL Panning Register
\r
68 bit 0-3 Indicates number of pixels to shift the display left
\r
69 Value 9bit textmode 256color mode Other modes
\r
80 3C0h index 14h (r/W): Attribute: Color Select Register (VGA Only)
\r
81 bit 0-1 If 3C0h index 10h bit 7 is set these 2 bits are used
\r
82 as bits 4-5 of the index into the DAC table.
\r
83 2-3 These 2 bits are used as bit 6-7 of the index into the
\r
84 DAC table except in 256 color mode.
\r
86 Note: this register does not affect 256 color modes.
\r
89 3C2h (R): Input Status #0 Register
\r
90 bit 4 Status of the switch selected by the Miscellaneous Output
\r
91 Register 3C2h bit 2-3. Switch high if set.
\r
92 5 (EGA Only) Pin 19 of the Feature Connector (FEAT0)
\r
94 6 (EGA Only) Pin 17 of the Feature Connector (FEAT1)
\r
96 7 (EGA Only ??) If set IRQ 2 has happened due to Vertical
\r
97 Retrace. Should be cleared by IRQ 2 interrupt routine
\r
98 by clearing port 3d4h index 11h bit 4.
\r
101 3C2h (W): Miscellaneous Output Register
\r
102 bit 0 If set Color Emulation. Base Address=3Dxh
\r
103 else Mono Emulation. Base Address=3Bxh.
\r
104 1 Enable CPU Access to video memory if set
\r
106 0: 14MHz(EGA) 25MHz(VGA)
\r
107 1: 16MHz(EGA) 28MHz(VGA)
\r
108 2: External(EGA) Reserved(VGA)
\r
109 4 (EGA Only) Disable internal video drivers if set
\r
110 5 When in Odd/Even modes Select High 64k bank if set
\r
111 6 Horizontal Sync Polarity. Negative if set
\r
112 7 Vertical Sync Polarity. Negative if set
\r
113 Bit 6-7 indicates the number of lines on the display:
\r
114 0=200(EGA) Reserved(VGA)
\r
116 2=350(EGA) 350(VGA)
\r
119 Note: Set to all zero on a hardware reset.
\r
120 Note: On the VGA this register can be read from port 3CCh.
\r
123 3C3h (W): Video Subsystem Enable Register
\r
124 bit 0 Enables the VGA display if set
\r
127 3C4h index 0 (r/W): Sequencer: Reset
\r
128 bit 0 (EGA) Asynchronous Reset if clear
\r
129 0 (VGA) Synchronous Reset just as bit 1
\r
130 1 Synchronous Reset if clear
\r
132 3C4h index 1 (r/W): Sequencer: Clocking Mode
\r
133 bit 0 If set character clocks are 8 dots wide, else 9.
\r
134 1 (EGA Only) If set the CRTC uses 2/5 of the clock cycles, else 4/5.
\r
135 2 If set loads video serializers every other character
\r
136 clock cycle, else every one.
\r
137 3 If set the Dot Clock is Master Clock/2, else same as
\r
138 Master Clock (See 3C2h bit 2-3). (Doubles pixels).
\r
139 4 (VGA Only) If set loads video serializers every fourth
\r
140 character clock cycle, else every one.
\r
141 5 (VGA Only) if set turns off screen and gives all memory
\r
142 cycles to the CPU interface.
\r
144 3C4h index 2 (r/W): Sequencer: Map Mask Register
\r
145 bit 0 Enable writes to plane 0 if set
\r
146 1 Enable writes to plane 1 if set
\r
147 2 Enable writes to plane 2 if set
\r
148 3 Enable writes to plane 3 if set
\r
150 3C4h index 3 (r/W): Sequencer: Character Map Select Register
\r
151 bit 0-1 (EGA) Selects EGA Character Map (0..3) if bit 3 of
\r
152 the character attribute is clear.
\r
153 2-3 (EGA) Selects EGA Character Map (0..3) if bit 3 of
\r
154 the character attribute is set.
\r
155 0,1,4 (VGA) Selects VGA Character Map (0..7) if bit 3 of
\r
156 the character attribute is clear.
\r
157 2,3,5 (VGA) Selects VGA Character Map (0..7) if bit 3 of
\r
158 the character attribute is set.
\r
160 Character Maps are placed at:
\r
161 Map no. (EGA/VGA) Map no. (VGA)
\r
167 3C4h index 4 (r/W): Sequencer: Memory Mode Register
\r
168 bit 0 Set if in an alphanumeric mode, clear in graphics modes.
\r
169 1 Set if more than 64kbytes on the adapter.
\r
170 2 Enables Odd/Even addressing mode if set.
\r
171 Odd/Even mode places all odd bytes in plane 1&3, and
\r
172 all even bytes in plane 0&2.
\r
173 3 (VGA Only) If set address bit 0-1 selects video memory
\r
174 planes (256 color mode), rather than the
\r
175 Map Mask and Read Map Select Registers.
\r
177 3C4h index 7 (R/W): Sequencer Horizontal Character Counter Reset Register.
\r
179 Note: Undocumented by IBM. May not be available in all clones.
\r
180 Note: A write to this register will cause the Horizontal Character Counter
\r
181 to be held reset (=0) until a write happens to any of the Sequencer
\r
182 registers index 0..6.
\r
183 The Vertical Line counter is clocked by a signal derived from the
\r
184 Horizontal Display Enable (which does not occur if the Horizontal
\r
185 Character Counter is held reset).
\r
186 Thus a write to index 7 during Vertical Retrace can stop the display
\r
187 timing and allow software to start the next frame reasonably
\r
188 synchronous to an external event.
\r
190 3C6h (R/W): PEL Mask (VGA Only)
\r
191 bit 0-7 This register is anded with the palette index sent
\r
192 for each dot. Should be set to FFh.
\r
194 3C7h (R): DAC State Register (VGA Only)
\r
195 bit 0-1 0 indicates the DAC is in Read Mode and 3 indicates
\r
198 3C7h (W): PEL Address Read Mode (VGA Only)
\r
199 bit 0-7 The PEL data register (0..255) to be read from 3C9h.
\r
201 Note: After reading the 3 bytes at 3C9h this register will
\r
202 increment, pointing to the next data register.
\r
204 3C8h (R/W): PEL Address Write Mode (VGA Only)
\r
205 bit 0-7 The PEL data register (0..255) to be written to 3C9h.
\r
206 Note: After writing the 3 bytes at 3C9h this register will
\r
207 increment, pointing to the next data register.
\r
209 3C9h (R/W): PEL Data Register (VGA Only)
\r
210 bit 0-5 Color value
\r
211 Note: Each read or write of this register will cycle through first
\r
212 the registers for Red, Blue and Green, then increment the
\r
213 appropriate address register, thus the entire palette can be
\r
214 loaded by writing 0 to the PEL Address Write Mode register 3C8h
\r
215 and then writing all 768 bytes of the palette to this register.
\r
217 3CAh (R): Feature Control Register (VGA Only)
\r
218 Bit 3 (VGA Only) Vertical Sync Select
\r
219 If set Vertical Sync to the monitor is the logical OR
\r
220 of the vertical sync and the vertical display enable.
\r
221 Note: This register is written to port 3dAh and read from 3CAh.
\r
224 3CAh (W): Graphics 2 Position (EGA Only)
\r
225 bit 0-1 Select which bit planes should be controlled by
\r
226 Graphics Controller #2. Always set to 1.
\r
228 3CCh (R): Miscellaneous Output Register (VGA Only)
\r
229 bit 0 If set Color Emulation. Base Address=3Dxh
\r
230 else Mono Emulation. Base Address=3Bxh.
\r
231 1 Enable CPU Access to video memory if set
\r
233 0= 25MHz, 1= 28MHz, 2= Reserved
\r
234 5 When in Odd/Even modes Select High 64k bank if set
\r
235 6 Horizontal Sync Polarity. Negative if set
\r
236 7 Vertical Sync Polarity. Negative if set
\r
237 Bit 6-7 indicates the number of lines on the display:
\r
238 0=Reserved, 1=400, 2=350, 3=480.
\r
239 Note: This register is written to port 3C2h and read from port 3CCh.
\r
242 3CCh (W): Graphics 1 Position (EGA Only)
\r
243 bit 0-1 Select which bit planes should be controlled by
\r
244 Graphics Controller #1. Always set to 0.
\r
246 3CEh index 0 (r/W): Graphics: Set/Reset Register
\r
247 bit 0 If in Write Mode 0 and bit 0 of 3CEh index 1 is set
\r
248 a write to display memory will set all the bits in
\r
249 plane 0 of the byte to this bit, if the corresponding
\r
250 bit is set in the Map Mask Register (3CEh index 8).
\r
251 1 Same for plane 1 and bit 1 of 3CEh index 1.
\r
252 2 Same for plane 2 and bit 2 of 3CEh index 1.
\r
253 3 Same for plane 3 and bit 3 of 3CEh index 1.
\r
255 3CEh index 1 (r/W): Graphics: Enable Set/Reset Register
\r
256 bit 0 If set enables Set/reset of plane 0 in Write Mode 0.
\r
257 1 Same for plane 1.
\r
258 2 Same for plane 2.
\r
259 3 Same for plane 3.
\r
261 3CEh index 2 (r/W): Graphics: Color Compare Register
\r
262 bit 0-3 In Read Mode 1 each pixel at the address of the byte read
\r
263 is compared to this color and the corresponding bit in
\r
264 the output set to 1 if they match, 0 if not.
\r
265 The Color Don't Care Register (3CEh index 7) can exclude
\r
266 bitplanes from the comparison.
\r
268 3CEh index 3 (r/W): Graphics: Data Rotate
\r
269 bit 0-2 Number of positions to rotate data right before it is
\r
270 written to display memory. Only active in Write Mode 0.
\r
271 3-4 In Write Mode 2 this field controls the relation between
\r
272 the data written from the CPU, the data latched from the
\r
273 previous read and the data written to display memory:
\r
274 0: CPU Data is written unmodified
\r
275 1: CPU data is ANDed with the latched data
\r
276 2: CPU data is ORed with the latch data.
\r
277 3: CPU data is XORed with the latched data.
\r
280 3CEh index 4 (r/W): Graphics: Read Map Select Register
\r
281 bit 0-1 Number of the plane Read Mode 0 will read from.
\r
283 3CEh index 5 (r/W): Graphics: Mode Register
\r
284 bit 0-1 Write Mode: Controls how data from the CPU is
\r
285 transformed before being written to display memory:
\r
286 0: Mode 0 works as a Read-Modify-Write operation.
\r
287 First a read access loads the data latches of the EGA/VGA
\r
288 with the value in video memory at the addressed location.
\r
289 Then a write access will provide the destination address
\r
290 and the CPU data byte. The data written is modified by the
\r
291 function code in the Data Rotate register (3CEh index 3) as
\r
292 a function of the CPU data and the latches, then data
\r
293 is rotated as specified by the same register.
\r
294 1: Mode 1 is used for video to video transfers.
\r
295 A read access will load the data latches with the contents
\r
296 of the addressed byte of video memory. A write access will
\r
297 write the contents of the latches to the addressed byte.
\r
298 Thus a single MOVSB instruction can copy all pixels in the
\r
299 source address byte to the destination address.
\r
300 2: Mode 2 writes a color to all pixels in the addressed byte
\r
301 of video memory. Bit 0 of the CPU data is written to plane 0
\r
302 et cetera. Individual bits can be enabled or disabled through
\r
303 the Bit Mask register (3CEh index 8).
\r
304 3: (VGA Only) Mode 3 can be used to fill an area with a color and
\r
305 pattern. The CPU data is rotated according to 3CEh index 3
\r
306 bits 0-2 and anded with the Bit Mask Register (3CEh index 8).
\r
307 For each bit in the result the corresponding pixel is set to
\r
308 the color in the Set/Reset Register (3CEh index 0 bits 0-3)
\r
309 if the bit is set and to the contents of the processor latch
\r
310 if the bit is clear.
\r
311 2 (EGA Only) Forces all outputs to a high impedance state if set.
\r
313 0: Data is read from one of 4 bit planes depending
\r
314 on the Read Map Select Register (3CEh index 4).
\r
315 1: Data returned is a comparison between the 8 pixels
\r
316 occupying the read byte and the color in the
\r
317 Color Compare Register (3CEh index 2).
\r
318 A bit is set if the color of the corresponding
\r
319 pixel matches the register.
\r
320 4 Enables Odd/Even mode if set (See 3C4h index 4 bit 2).
\r
321 5 Enables CGA style 4 color pixels using even/odd bit pairs
\r
323 6 (VGA Only) Enables 256 color mode if set.
\r
325 3CEh index 6 (r/W): Graphics: Miscellaneous Register
\r
326 bit 0 Indicates Graphics Mode if set, Alphanumeric mode else.
\r
327 1 Enables Odd/Even mode if set.
\r
328 2-3 Memory Mapping:
\r
330 1: use A000h-AFFFh EGA/VGA Graphics modes
\r
331 2: use B000h-B7FFh Monochrome modes
\r
332 3: use B800h-BFFFh CGA modes
\r
334 3CEh index 7 (r/W): Graphics: Color Don't Care Register
\r
335 bit 0 Ignore bit plane 0 in Read mode 1 if clear.
\r
336 1 Ignore bit plane 1 in Read mode 1 if clear.
\r
337 2 Ignore bit plane 2 in Read mode 1 if clear.
\r
338 3 Ignore bit plane 3 in Read mode 1 if clear.
\r
340 3CEh index 8 (r/W): Graphics: Bit Mask Register
\r
341 bit 0-7 Each bit if set enables writing to the corresponding
\r
342 bit of a byte in display memory.
\r
345 3d4h index 0 (r/W): CRTC: Horizontal Total Register
\r
346 bit 0-7 (EGA) Horizontal Total Character Clocks-2
\r
347 0-7 (VGA) Horizontal Total Character Clocks-5
\r
349 3d4h index 1 (r/W): CRTC: Horizontal Display End Register
\r
350 bit 0-7 Number of Character Clocks Displayed -1
\r
352 3d4h index 2 (r/W): CRTC: Start Horizontal Blanking Register
\r
353 bit 0-7 The count at which Horizontal Blanking starts
\r
355 3d4h index 3 (r/W): CRTC: End Horizontal Blanking Register
\r
356 bit 0-4 Horizontal Blanking ends when the last 5 (6 for VGA)
\r
357 bits of the character counter equals this field.
\r
358 (VGA) The sixth bit is found in port 3d4h index 5 bit 7.
\r
359 5-6 Number of character clocks to delay start of display
\r
360 after Horizontal Total has been reached.
\r
361 7 (VGA Only) Access to Vertical Retrace registers if set
\r
362 If clear reads to 3d4h index 10h and 11h
\r
363 access the Lightpen readback registers ??
\r
365 3d4h index 4 (r/W): CRTC: Start Horizontal Retrace Register
\r
366 bit 0-7 Horizontal Retrace starts when the Character Counter
\r
367 reaches this value.
\r
369 3d4h index 5 (r/W): CRTC: End Horizontal Retrace Register
\r
370 bit 0-4 Horizontal Retrace ends when the last 5 bits of the
\r
371 character counter equals this value.
\r
372 5-6 Number of character clocks to delay start of display
\r
373 after Horizontal Retrace.
\r
374 7 (EGA) Provides Smooth Scrolling in Odd/Even mode.
\r
375 When set display starts from an odd byte.
\r
376 7 (VGA) bit 5 of the End Horizontal Blanking count
\r
377 (See 3d4h index 3 bit 0-4).
\r
379 3d4h index 6 (r/W): CRTC: Vertical Total Register
\r
380 bit 0-7 Lower 8 bits of the Vertical Total
\r
381 Bit 8 is found in 3d4h index 7 bit 0.
\r
382 (VGA) Bit 9 is found in 3d4h index 7 bit 5.
\r
383 Note: For the VGA this value is the number of scan lines in the display -2.
\r
385 3d4h index 7 (r/W): CRTC: Overflow Register
\r
386 bit 0 Bit 8 of Vertical Total (3d4h index 6)
\r
387 1 Bit 8 of Vertical Display End (3d4h index 12h)
\r
388 2 Bit 8 of Vertical Retrace Start (3d4h index 10h)
\r
389 3 Bit 8 of Start Vertical Blanking (3d4h index 15h)
\r
390 4 Bit 8 of Line Compare Register (3d4h index 18h)
\r
391 5 (VGA) Bit 9 of Vertical Total (3d4h index 6)
\r
392 6 (VGA) Bit 9 of Vertical Display End (3d4h index 12h)
\r
393 7 (VGA) Bit 9 of Vertical Retrace Start (3d4h index 10h)
\r
395 3d4h index 8 (r/W): CRTC: Preset Row Scan Register
\r
396 bit 0-4 Number of lines we have scrolled down in the first
\r
397 character row. Provides Smooth Vertical Scrolling.
\r
398 5-6 (VGA Only) Number of bytes to skip at the start of
\r
399 scanline. Provides Smooth Horizontal Scrolling
\r
400 together with the Horizontal Panning Register
\r
403 3d4h index 9 (r/W): CRTC: Maximum Scan Line Register
\r
404 bit 0-4 Number of scan lines in a character row -1
\r
405 5 (VGA) Bit 9 of Start Vertical Blanking
\r
406 6 (VGA) Bit 9 of Line Compare Register
\r
407 7 (VGA) Doubles each scan line if set.
\r
408 I.e displays 200 lines on a 400 display.
\r
410 3d4h index Ah (r/W): CRTC: Cursor Start Register
\r
411 bit 0-4 First scanline of cursor within character.
\r
412 5 (VGA) Turns Cursor off if set
\r
414 3d4h index Bh (r/W): CRTC: Cursor End Register
\r
415 bit 0-4 Last scanline of cursor within character
\r
416 5-6 Delay of cursor data in character clocks.
\r
418 3d4h index Ch (r/W): CRTC: Start Address High Register
\r
419 bit 0-7 Upper 8 bits of the start address of the display buffer
\r
421 3d4h index Dh (r/W): CRTC: Start Address Low Register
\r
422 bit 0-7 Lower 8 bits of the start address of the display buffer
\r
424 3d4h index Eh (r/W): CRTC: Cursor Location High Register
\r
425 bit 0-7 Upper 8 bits of the address of the cursor
\r
427 3d4h index Fh (r/W): CRTC: Cursor Location Low Register
\r
428 bit 0-7 Lower 8 bits of the address of the cursor
\r
430 3d4h index 10h (R): CRTC: Light Pen High Register (EGA Only)
\r
431 bit 0-7 (EGA Only) Upper 8 bits of the address of the
\r
434 3d4h index 10h (r/W): CRTC: Vertical Retrace Start Register
\r
435 bit 0-7 Lower 8 bits of Vertical Retrace Start. Vertical Retrace
\r
436 starts when the line counter reaches this value.
\r
437 Bit 8 is found in 3d4h index 7 bit 2.
\r
438 (VGA Only) Bit 9 is found in 3d4h index 7 bit 7.
\r
440 3d4h index 11h (R): CRTC: Light Pen Low Register (EGA Only)
\r
441 bit 0-7 (EGA Only) Lower 8 bits of the address of the
\r
444 3d4h index 11h (r/W): CRTC: Vertical Retrace End Register
\r
445 bit 0-3 Vertical Retrace ends when the last 4 bits of the
\r
446 line counter equals this value.
\r
447 4 if clear Clears pending Vertical Interrupts.
\r
448 5 Vertical Interrupts (IRQ 2) disabled if set.
\r
449 Can usually be left disabled, but some systems
\r
450 (including PS/2) require it to be enabled.
\r
451 6 (VGA Only) If set selects 5 refresh cycles per
\r
452 scanline rather than 3.
\r
453 7 (VGA Only) Disables writing to registers 0-7 if set
\r
454 3d4h index 7 bit 4 is not affected by this bit.
\r
456 3d4h index 12h (r/W): CRTC: Vertical Display End Register
\r
457 bit 0-7 Lower 8 bits of Vertical Display End. The display
\r
458 ends when the line counter reaches this value.
\r
459 Bit 8 is found in 3d4h index 7 bit 1.
\r
460 (VGA Only) Bit 9 is found in 3d4h index 7 bit 6.
\r
462 3d4h index 13h (r/W): CRTC: Offset register
\r
463 bit 0-7 Number of bytes in a scanline / K. Where K is 2 for
\r
464 byte mode, 4 for word mode and 8 for Double Word mode.
\r
466 3d4h index 14h (r/W): CRTC: Underline Location Register
\r
467 bit 0-4 Position of underline within Character cell.
\r
468 5 (VGA Only) If set memory address is only changed
\r
469 every fourth character clock.
\r
470 6 (VGA Only) Double Word mode addressing if set
\r
472 3d4h index 15h (r/W): CRTC: Start Vertical Blank Register
\r
473 bit 0-7 Lower 8 bits of Vertical Blank Start. Vertical blanking
\r
474 starts when the line counter reaches this value.
\r
475 Bit 8 is found in 3d4h index 7 bit 3.
\r
477 3d4h index 16h (r/W): CRTC: End Vertical Blank Register
\r
478 bit 0-4 (EGA) Vertical blanking stops when the lower 5 bits
\r
479 of the line counter equals this field.
\r
480 0-6 (VGA) Vertical blanking stops when the lower 7 bits
\r
481 of the line counter equals this field.
\r
483 3d4h index 17h (r/W): CRTC: Mode Control Register
\r
484 bit 0 If clear use CGA compatible memory addressing system
\r
485 by substituting character row scan counter bit 0 for
\r
486 address bit 13, thus creating 2 banks for even and
\r
488 1 If clear use Hercules compatible memory addressing
\r
489 system by substituting character row scan counter bit 1 for
\r
490 address bit 14, thus creating 4 banks.
\r
491 2 If set increase scan line counter only every second line.
\r
492 3 If set increase memory address counter only every other
\r
494 4 (EGA Only) If set disable the EGA output drivers. This bit
\r
495 is used for other purposes in some Super VGA chips.
\r
496 5 When in Word Mode bit 15 is rotated to bit 0 if this bit
\r
497 is set else bit 13 is rotated into bit 0.
\r
498 6 If clear system is in word mode. Addresses are rotated
\r
499 1 position up bringing either bit 13 or 15 into bit 0.
\r
500 7 Clearing this bit will reset the display system
\r
501 until the bit is set again.
\r
503 3d4h index 18h (r/W): CRTC: Line Compare Register
\r
504 bit 0-7 Lower 8 bits of the Line Compare. When the Line counter
\r
505 reaches this value, the display address wraps to 0.
\r
506 Provides Split Screen facilities.
\r
507 Bit 8 is found in 3d4h index 7 bit 4.
\r
508 (VGA Only) Bit 9 is found in 3d4h index 9 bit 6.
\r
510 3d4h index 22h (R): Memory Latch Register (VGA - Undocumented).
\r
511 bit 0-7 Reads the contents of the Graphics Controller Memory Data Latch
\r
512 for the plane selected by 3C0h index 4 bit 0-1 (Read Map Select).
\r
513 Note: This register is not documented by IBM and may not be available
\r
516 3d4h index 24h (R): Attribute Controller Toggle Register.
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517 (VGA - Undocumented).
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518 bit 0-4 Attribute Controller Index.
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519 The current value of the Attribute Index Register.
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520 5 Palette Address Source. Same as 3C0h bit 5.
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521 7 If set next read or write to 3C0h will access the data register.
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522 Note: This register is not documented by IBM and may not be available
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525 3d4h index 30h-3Fh (W): Clear Vertical Display Enable. (VGA - Undocumented).
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526 bit 0 Setting this bit will clear the Vertical Display Enable thus
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527 blanking the display for the rest of the frame and giving the CPU
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528 total access to display memory until the start of the next frame.
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529 Note: This register is not documented by IBM and may not be available
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532 3dAh (R): Input Status #1 Register
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533 bit 0 Either Vertical or Horizontal Retrace active if set
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534 1 (EGA Only) Light Pen has triggered if set
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535 2 (EGA Only) Light Pen switch is open if set
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536 3 Vertical Retrace in progress if set
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537 4-5 (EGA Only) Shows two of the 6 color outputs,
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538 depending on 3C0h index 12h bit 4-5:
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539 Attr: Bit 4-5: Out bit 4 Out bit 5
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544 3dAh (W): Feature Control Register
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545 bit 0 (EGA Only) Output to pin 21 of the Feature Connector.
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546 1 (EGA Only) Output to pin 20 of the Feature Connector.
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547 3 (VGA Only) Vertical Sync Select
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548 If set Vertical Sync to the monitor is the logical OR
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549 of the vertical sync and the vertical display enable.
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551 Note: On the VGA this register can be read from port 3CAh.
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