+ Chips and Technologies Super VGA Chip Sets:\r
+\r
+\r
+ 82c450\r
+ 82c451 256k DRAM max 800x600 16col\r
+ 82c452 1M DRAM max 640x480 256col, 1024x768 16col\r
+ 82c453 1M VRAM max 800x600 256 col\r
+ 82c455 256k DRAM Flat Panel version\r
+ 82c456 256k DRAM do\r
+ 82c457 do. Full color. \r
+ F65520 1M D/VRAM do. Full color. max 1280x1024 16 col & 800x600 256 col\r
+ F65530 1M D/VRAM do. Full color. max 1280x1024 16 col & 800x600 256 col\r
+ Supports Local Bus. \r
+\r
+\r
+ 94h (R/W): Setup Control Register for Microchannel boards\r
+ bit 0-2 Reserved\r
+ 3 Enables Adapter VGA if set\r
+ 4 Enters Setup Mode if set\r
+ 5-7 Reserved\r
+ Note: This is the same register as 46E8h.\r
+\r
+ 100h (R): Microchannel ID low\r
+ bit 0-7 Bit 0-7 of Microchannel Card ID\r
+\r
+ 101h (R): Microchannel ID high\r
+ bit 0-7 Bit 8-15 of Microchannel Card ID\r
+\r
+ 102h (R/W): Global Enable\r
+ bit 0 VGA is enabled if set.\r
+\r
+ 103h (R/W): Multiple Enable\r
+ bit 0-3 Multiple VGA Enable\r
+ 4 Must be 0 for propper operation of 82c455/6/7.\r
+ 6 Extension registers at 3B6h/7h if set,\r
+ 3D6h/7h if not.\r
+ 7 Extension Registers Access Enable.\r
+ VGA Extension registers at 3d7h can only be\r
+ accessed if this bit is set.\r
+ Note: This register only available in Setup Mode. \r
+\r
+ 104h (R): Global ID (Setup) (Only in Setup Mode)\r
+ bit 0-7 Chip I/D. 0A5h if Chips and Tech Chip set.\r
+\r
+ 3C3h (R/W): Setup Control PS/2\r
+ bit 0 Enables motherboard VGA if set\r
+ 4 Enters Setup mode if set\r
+\r
+ 3d4h index 22h (R/W): CPU Data Latch or Color Compare from last read\r
+\r
+ 3d4h index 24h (R/W): Attribute Controller flip/flop\r
+\r
+ 3d6h index 0 (R): Chip Version\r
+ bit 0-3 Revision number\r
+ 4-7 Chipcode:\r
+ 0: 451 1:452 2:455 3:453 5:456 6:457\r
+ 7: 65520, 8:65530\r
+\r
+ 3d6h index 1 (R): DIP Switch Register\r
+ bit 0-6 State of the DIP switches.\r
+ 0-7 (655x0) Read from Memory Address bus A on Reset.\r
+ Bit 0-1: CPU Bus type \r
+ 0=PI bus, 1=MC bus, 2=Local bus (65530 only), 3=ISA bus.\r
+ 2: Pixel Clock Source (OSC/)\r
+ 0: CLK0-CLK3 are pixel clock inputs. \r
+ CLK0 or CLK1 is MCLK input.\r
+ 1: CLK0 is MCLK input.\r
+ CLK1 is pixel clock input.\r
+ CLK2 is CLKSEL0 output.\r
+ CLK3 is CLKSEL1 output. \r
+ 3: Memory Clock Source (56M/)\r
+ 0: MCLK = 56.644 MHz (80ns RAM)\r
+ If bit 2 is 0:\r
+ CLK0 is 50.350 MHz\r
+ CLK1 is 56.644 MHz (MCLK source)\r
+ CLK2 is 40.000 MHz\r
+ CLK3 is 44.900 MHz\r
+ If bit 2 is 1:\r
+ MCLK (CLK0) is 56.644 MHz\r
+ Clock Select 0 is 40.000 MHz\r
+ Clock Select 1 is 50.350 MHz\r
+ Clock Select 2 is user defined\r
+ Clock Select 3 is 44.900 MHz\r
+ 1: MCLK = 50.350 MHz (100ns RAM)\r
+ If bit 2 is 0:\r
+ CLK0 is 50.350 MHz\r
+ CLK1 is 28.322 MHz (MCLK source)\r
+ CLK2 is 40.000 MHz\r
+ CLK3 is 44.900 MHz\r
+ If bit 2 is 1:\r
+ MCLK (CLK0) is 50.350 MHz\r
+ Clock Select 0 is 40.000 MHz\r
+ Clock Select 1 is 28.322 MHz\r
+ Clock Select 2 is user defined\r
+ Clock Select 3 is 44.900 MHz\r
+ 4: Transceiver Control\r
+ If set there are no external transceivers (pin 69 is\r
+ VGARD output), if clear there are external transceivers\r
+ (pin 69 is ENAVEE/ output).\r
+\r
+ 3d6h index 2 (R/W): CPU Interface\r
+ bit 0 16bit memory enabled if set\r
+ 1 (82c451-453) 16 bit I/O if set\r
+ (82c453 Only) Fast Font Enable ???\r
+ The byte written to memory is used as a mask\r
+ for painting foreground color to the pixels\r
+ with the corresponding bit set and background\r
+ color to the rest.\r
+ (655x0 Only) Digital Monitor Clock Mode\r
+ 0: CLK0 = 25 MHz, CLK1 = 28 MHz\r
+ 1: CLK0 = 14 MHz (56MHz /4 or 28MHz /2)\r
+ CLK1 = 16 MHz (50MHz /3)\r
+ 2 (82c451/2/3/5) Fast MCA buscycle decoding if set\r
+ 3-4 (82c453 and 455-457) Attribute port pairing\r
+ 0: Normal Attribute addressing\r
+ 1: 3C1h is both read and write, 8 and 16 bit.\r
+ 2: 3C1h is both read and write, 8 bit only.\r
+ 5 (Not 82c451/2) 10 bit I/O decoding if set, 16 bit else\r
+ 6 (82c453 Only) Pel Panning Control\r
+ (655x0 Only) If set external palette registers can be addressed\r
+ at 83C6h-83C9h. (Brooktree/Sierra type DACs).\r
+ 7 (Read Only) Attribute flip-flop status. If set the Attribute\r
+ register (3C0h) is currently in Data mode.\r
+\r
+ 3d6h index 3 (R/W): ROM Interface (not 655x0)\r
+ bit 0 Disable on-card ROM if set.\r
+ Enable ROM at C0000h-C7FFFh if clear.\r
+\r
+ 3d6h index 4 (R/W): Memory Mapping \r
+ bit 0-1 (82c452/3) Display Memory Size:\r
+ 0: 256Kb, 1: 512Kb, 2: 1Mb.\r
+ (655x0) Memory Configuration\r
+ 0: 2 x 256Kx4 D/VRAM 256K tot 8 bit datapath\r
+ 1: 4 x 256Kx4 D/VRAM 512K tot 16 bit datapath\r
+ 3: 2 x 512Kx8 DRAM 1M tot 16 bit datapath\r
+ 2 (82c451/5/6/7) Enable bank access if set\r
+ (82c452/3, 655x0) If set CRTC Address can cross bank boundaries.\r
+ 3 (82c457) If set DRAM timing is for 64Kx16 (4 WE, 1 CAS)\r
+ if clear for 64Kx4 (4 CAS, 1 WE).\r
+ (655x0) Enables bank addressing if set.\r
+ 4 (655x0) If set VRAM interface, else DRAM interface.\r
+ 5 (655x0) If set CPU memory write buffer is enabled.\r
+ 6 (655x0) If set enables 0WS capability.\r
+ 7 (655x0) If set allows faster 0WS cycle timing.\r
+ \r
+ 3d6h index 5h (R/W): Sequencer Control (452/3/7 only)\r
+ bit 2 (82c457) Clock Pin Polarity.\r
+ If set CLK0 is defined as a common clock and CLK1/S0\r
+ and CLK2/S1 are select outputs. If clear one of CLK0,\r
+ CLK1 and CLK2 is selected as the display clock.\r
+\r
+ 3d6h index 6h (R/W): DRAM Interface (82c452 only)\r
+\r
+ 3d6h index 6h (R/W): Palette Control Register (655x0 only)\r
+ bit 0 If set enables external DAC if 3d6h index 6 bit 0 is 0.\r
+ 1 If set disables the internal DAC.\r
+ Causes the DAC to power down and tri-states the outputs. \r
+ 2 If set enables 16 bit/pixel operation.\r
+ Timing to an external DAC will be SC11486 (Tseng) compatible.\r
+ (Two bytes output per pixel, one on the rising edge of PCLK\r
+ and one on the falling edge).\r
+ 3 If set 16 bit pixels are 5 red-6 green-5 blue.\r
+ If clear they are 5 bits of each.\r
+ 4 If set the Sense Status bit (3C2h bit 4) is driven by the SENSE\r
+ pin from external logic.\r
+ 5 If set bypasses the internal RAMDAC.\r
+ This bit should always be clear.\r
+ 6-7 Color Reduction Select. \r
+ In flat panel modes these bits determine the algorithm used to\r
+ reduce 18 bit color data to 6 bits for mono panels.\r
+ 0: NTSC weighting, 1: Equivalent weight, 2: Green only, 3: Color.\r
+\r
+ 3d6h index 8h (R/W): General Purpose Output Select B Register. (451/2/5/6/7 only)\r
+ bit 0 Select bit B for ERMIN/ pin.\r
+ 1 Select bit B for TRAP/ pin.\r
+ 2 (82c457) If set PNL14 pin outputs panel data bit 14,\r
+ if clear PNL14 pin outputs DATEN/. \r
+\r
+ 3d6h index 9h (R/W): General Purpose Output Select A Register. (451/2/5/6/7 only)\r
+ bit 0 Select bit A for ERMIN/ pin.\r
+ 1 Select bit A for TRAP/ pin.\r
+ Select A and B determine the output on the pin:\r
+ B A Output\r
+ clear clear Normal\r
+ clear set 3-State\r
+ set clear Force low\r
+ set set Force high \r
+ \r
+ 3d6h index Ah (R/W): Cursor Address Top (82c452/3 Only)\r
+ bit 0-1 Cursor Address bit 16,17\r
+ 2-7 Reserved\r
+\r
+ 3d6h index Bh (R/W): CPU Paging (82c451/5/6/7 only)\r
+ bit 0-1 Bank number in 64k chunks.\r
+ Note: This Bank register is used if in a 256 color mode and\r
+ the chip is a 82c451/5/6/7.\r
+\r
+ 3d6h index Bh (R/W): Memory Paging Register (82c452/3, 655x0 only)\r
+ bit 0 Enable extended paging (256 color paging) if set\r
+ 1 If set Dual Pages are enabled. A0000h-A7FFFh uses 3d6h \r
+ index 10h, A8000h-AFFFFh uses 3d6h index 11h.\r
+ 2 CPU Address divide by 4 (256 color addressing)\r
+ 3 (655x0) If set CPU address divide by 2 is enabled.\r
+ 4 (65530) If set Memory is mapped as 1MB linear Memory.\r
+\r
+ 3d6h index Ch (R/W): Start Address Top (82c452/3, 655x0 Only)\r
+ bit 0-1 Display Start Address bit 16,17.\r
+\r
+ 3d6h index Dh (R/W): Auxiliary Offset Register\r
+ bit 0 Bit 8 of Offset field. If set each line is >255 words.\r
+ 1 Bit 8 of simulated Offset field.\r
+\r
+ 3d6h index Eh (R/W): Text Mode (82c452, 655x0 Only)\r
+ bit 0 (82c452) Extended text Mode Control ??\r
+ 1 (82c452) Enable anti-aliased fonts if set\r
+ 2 (655x0) If set cursor is non-blinking.\r
+ 3 (655x0) If set Cursor style is Exclusive-Or.\r
+\r
+ 3d6h index Fh (R/W): Software Flags 2 (655x0 only)\r
+ bit 0-7 Software flags. \r
+\r
+ 3d6h index 10h (R/W): Single/Low Map (82c452/3, 655x0 Only)\r
+ bit 0-5 (82c452) Bank no in 4K/16K chunks.\r
+ 0-7 (82c453) Bank no in 1K/4K chunks.\r
+ Note: This Bank register is used if in single-paging mode\r
+ or if addressing the lower half (32 or 64Kb) of the\r
+ adapters address range.\r
+\r
+ 3d6h index 11h (R/W): High Map (82c452/3, 655x0 Only)\r
+ bit 0-5 (82c452) Bank no in 4K/16K chunks.\r
+ 0-7 (82c453) Bank no in 1K/4K chunks.\r
+ Note: This Bank register is used if addressing the upper\r
+ half (32 or 64Kb) of the adapters address range.\r
+\r
+ 3d6h index 14h (R/W): Emulation Mode Register\r
+ bit 0-1 Emulation Mode:\r
+ 0=VGA/EGA, 1=CGA, 2=MDA and 3=Hercules.\r
+ 2 (R) Hercules Configuration (3BFh) bit 0 Readback.\r
+ If set it is possible to set the Graphics Mode bit (3B8h bit 1).\r
+ 3 (R) Hercules Configuration (3BFh) bit 1 Readback.\r
+ If set it is possible to set the Graphics Page bit (3B8h bit 7).\r
+ 4 Display Enable Status Mode.\r
+ If set bit 0 of the Input Status Register 1 (3dAh)\r
+ shows the Hsync Status (as MDA/Hercules), if clear the\r
+ Display Enable is shown (as CGA/VGA). \r
+ 5 Vertical Retrace Status Mode.\r
+ If set bit 3 of the Input Status Register 1 (3dAh)\r
+ shows the Video signal (as MDA/Hercules), if clear the\r
+ Vertical Retrace status is shown (as CGA/VGA). \r
+ 6 Vsync Status Mode.\r
+ If clear bit 7 of the Input Status Register 1 (3dAh)\r
+ shows the Vsync Status (as MDA/Hercules).\r
+ 7 Interrupt Output Function.\r
+ If clear the IRQ pin will always 3-state, if set it\r
+ will 3-state only when interrupts are disabled. \r
+\r
+ 3d6h index 15h (R/W): Write Protect Register.\r
+ bit 0 Write Protect Group 1 Registers.\r
+ If set the Sequencer (3C4h), Graphics Controller (3CEh)\r
+ and Attribute Controller (3C0h) registers are write protected.\r
+ 1 Write Protect Group 2 Registers.\r
+ If set the Cursor Size Register (3d4h index 9 bits 0-4) \r
+ and the Character Height registers (3d4h index 0Ah and 0Bh)\r
+ are write protected.\r
+ 2 Write Protect Group 3 Registers.\r
+ If set CRT registers (3d4h) index: 7 bit 4, 8, 11h bits 4-5,\r
+ 13h, 14h, 17h bits 0-1 and 3-7, 18h are write protected.\r
+ 3 Write Protect Group 4 Registers.\r
+ If set CRT registers (3d4h) index: 9 bits 5-7, 10h, 11h bits 0-3\r
+ and 6-7, 12h, 15h, 16h, 17h bit 2 are write protected.\r
+ 4 Write Protect Group 5 Register.\r
+ If set the Miscellaneous Output (3C2h) and Feature Control\r
+ (3dAh) registers are write protected.\r
+ 5 Write Protect Group 6 Registers.\r
+ If set the DAC registers (3C6h-3C9h) are write protected.\r
+ 6 Write Protect Group 0 Registers.\r
+ If set CRT registers (3d4h) index: 0, 1, 2, 3, 4, 5, 6,\r
+ 7 bits 0-3 and 5-7 are write protected.\r
+\r
+ 3d6h index 16h (R/W): Trap Enable Register. (not 655x0)\r
+ bit 0 If set accesses to registers 3B4h or 3B5h cause a Trap.\r
+ 1 If set accesses to registers 3B8h or 3BFh cause a Trap.\r
+ 2 If set accesses to registers 3C0h-3CFh cause a Trap.\r
+ 3 If set accesses to registers 3D4h or 3D5h cause a Trap.\r
+ 4 If set accesses to registers 3D8h or 3D9h cause a Trap.\r
+ 5 If set accesses to registers 3d4h index 0-0Bh and 10h-18h\r
+ cause a Trap.\r
+\r
+ 3d6h index 17h (R/W): Trap Status Register. (not 655x0)\r
+ bit 0 If set a trap occurred due to access to registers 3B4h or 3B5h.\r
+ 1 If set a trap occurred due to access to registers 3B8h or 3BFh.\r
+ 2 If set a trap occurred due to access to registers 3C0h-3CFh.\r
+ 3 If set a trap occurred due to access to registers 3D4h or 3D5h.\r
+ 4 If set a trap occurred due to access to registers 3D8h or 3D9h.\r
+ 5 If set a trap occurred due to access to registers \r
+ 3d4h index 0-0Bh or 10h-18h.\r
+ Note: Any bits in this register can be cleared by writing a 1 bit to them. \r
+\r
+ 3d6h index 18h (R/W): Alternate Horizontal Display Enable End Register\r
+ bit 0-7 This register replaces the Horizontal Display Enable End Register\r
+ (3d4h index 1) in low resolution CGA text and graphics modes,\r
+ Hercules Graphics and all flat panel modes.\r
+ Note: Probably doesn't exist in the 82c451/2/3.\r
+\r
+ 3d6h index 19h (R/W): Alternate Horizontal Sync Start Register\r
+ bit 0-7 This register replaces the Horizontal Sync Start Register\r
+ (3d4h index 4) in low resolution CGA text and graphics modes,\r
+ Hercules Graphics and all flat panel modes.\r
+ Note: Probably doesn't exist in the 82c451/2/3.\r
+\r
+ 3d6h index 1Ah (R/W): Alternate Horizontal Sync End Register\r
+ bit 0-4 Alternate Horizontal Sync End. Replaces 3d4h index 5 bits 0-4.\r
+ 5-7 Alternate Horizontal Sync Delay. \r
+ For CRTs replaces 3d4h index 5 bits 5-6.\r
+ Note: This register replaces the Horizontal Sync End Register (3d4h index 5)\r
+ in low resolution CGA text and graphics modes, Hercules Graphics and\r
+ all flat panel modes.\r
+ Note: Probably doesn't exist in the 82c451/2/3.\r
+ \r
+ 3d6h index 1Bh (R/W): Alternate Horizontal Total Register\r
+ bit 0-7 This register replaces the Horizontal Total Register\r
+ (3d4h index 0) in low resolution CGA text and graphics modes,\r
+ Hercules Graphics and all flat panel modes.\r
+ Note: Probably doesn't exist in the 82c451/2/3.\r
+\r
+ 3d6h index 1Ch (R/W): Alternate Horizontal Blank Start Register (CRT)\r
+ bit 0-7 Alternate Horizontal Blank Start.\r
+ Note: For CRT systems this register replaces the Horizontal Blank Start\r
+ Register (3d4h index 2) in low resolution CGA text and graphics\r
+ modes and Hercules Graphics mode.\r
+ Note: Probably doesn't exist in the 82c451/2/3.\r
+ Note: This register has different meaning for CRT and Plat Panel systems.\r
+\r
+ 3d6h index 1Ch (R/W): Alternate Horizontal Blank End Register (Flat Panel)\r
+ bit 0-7 For Flat Panel systems this value specifies the end of Horizontal\r
+ Blank in terms of character clocks.\r
+ Note: Probably doesn't exist in the 82c451/2/3.\r
+ Note: This register has different meaning for CRT and Plat Panel systems.\r
+\r
+ 3d6h index 1Dh (R/W): Alternate Horizontal Blank End Register (CRT)\r
+ bit 0-4 Alternate Horizontal Blank End\r
+ 5-6 Alternate Display Enable Skew Control. \r
+ Note: For CRT systems this register replaces the Horizontal Blank End\r
+ Register (3d4h index 3) in low resolution CGA text and graphics\r
+ modes, and Hercules Graphics mode.\r
+ Note: Probably doesn't exist in the 82c451/2/3.\r
+ Note: This register has different meaning for CRT and Plat Panel systems.\r
+\r
+ 3d6h index 1Dh (R/W): Alternate Horizontal Blank Start Register (Flat Panel)\r
+ bit 0-7 Alternate Horizontal Blank Start.\r
+ Note: For Flat Panel systems this register replaces the Horizontal Blank\r
+ Start Register (3d4h index 2).\r
+ Note: Probably doesn't exist in the 82c451/2/3.\r
+ Note: This register has different meaning for CRT and Plat Panel systems.\r
+\r
+ 3d6h index 1Eh (R/W): Alternate Offset Register\r
+ bit 0-7 Alternate Offset.\r
+ Note: This register replaces the Offset Register (3d4h index 13h) in low\r
+ resolution CGA text and graphics modes and Hercules Graphics mode.\r
+ Note: Probably doesn't exist in the 82c451/2/3.\r
+\r
+ 3d6h index 1Fh (R/W): Virtual EGA Switch Register (655x0 only)\r
+ bit 0-3 If bit 7 is 1 one of these bits is read back in the Input Status\r
+ Register 0 (3C2h bit 4) depending on Miscellaneous Output bits 2-3:\r
+ 0: bit 3, 1: bit 2, 2: bit 1, 3:bit 0.\r
+ 7 If set one of bits 0-3 is read back in the Input Status Register\r
+ (3C2h) bit 4.\r
+\r
+ 3d6h index 20h (R/W): Sliding Unit Delay (452/3 only)\r
+\r
+ 3d6h index 21h (R/W): Sliding Hold A (452 only)\r
+\r
+ 3d6h index 22h (R/W): Sliding Hold B (452 only)\r
+\r
+ 3d6h index 23h (R/W): Write Mask Control (452/3 Only)\r
+ bit 0 Enable VRAM Write Mask function if set\r
+ 1-2 Write Bit Mask Select:\r
+ 0: Write Bit Mask Pattern Register (3d6h index 24h)\r
+ 1: Graphics Controller Bit Mask (3CEh index 8)\r
+ 2: Rotated CPU byte\r
+ 3 Enable Fast Read/Modify/Write function if set\r
+\r
+ 3d6h index 24h (R/W): Write Bit Mask Pattern (82c452/3 only)\r
+ bit 0-7 Write Bit Mask (if 3d6h index 23h bit 1-2 =0)\r
+\r
+ 3d6h index 24h (R/W): Alternate Maximum Scanline Register (655x0 only)\r
+ bit 0-4 Number of scanlines -1 per character row of TallFont.\r
+ Note: Used in Flat Panel text modes when TallFont is enabled.\r
+\r
+ 3d6h index 25h (R/W): FP AltGrHVirtPanel Size (453, 655x0 only)\r
+ bit 0-7 Should be: (9/8)*(3d6h index 1Ch +1) -1.\r
+\r
+ 3d6h index 26h (R/W): Configuration (82c453 Only)\r
+ bit 0 PC/AT if set, PS/2 else\r
+ 1-2 VRAM memory\r
+ 0: 512k 16 chips of 64k x4\r
+ 1: 512k 4 chips of 256k x4\r
+ 2: 1M 8 chips of 256k x4\r
+ 3: 512k 8 chips of 64k x4 ?????\r
+ maybe 256k ??\r
+\r
+ 3d6h index 27h (R/W): Force Sync State\r
+\r
+ 3d6h index 28h (R/W): Video Interface\r
+ bit 0 BLANK/Display Enable Polarity.\r
+ Positive if set, Negative if clear.\r
+ 1 Blank /Display Enable Select (CRT).\r
+ If set the BLANK/ pin outputs DE, if clear BLANK/\r
+ 2 Shut Off Video.\r
+ If set the video signal is forced to default video\r
+ (3d6h index 2bh) during the blanking interval. \r
+ 3 Shut Off Blank.\r
+ If set the BLANK/ output is forced active\r
+ during the blanking interval.\r
+ (655x0) Read/writable, but has no function.\r
+ 4 (655x0) 256 Color Video Path. \r
+ If set Video Data Path is 8 bits rather than 4 bits.\r
+ 5 (655x0) Interlace Video. CRT graphics modes only.\r
+ If set Video is interlaced.\r
+ 6 (655x0) 8-bit Video Pixel Panning.\r
+ If set 3C0h index 13h bits 0-2 are used to control\r
+ pixel panning rather than bits 1-2.\r
+ 7 (655x0) Read/writable, but has no function.\r
+ \r
+ 3d6h index 29h (R/W): External Sync Control (452 only)\r
+\r
+ 3d6h index 2Ah (R/W): Frame Interrupt Count (452 Only)\r
+ bit 0-4 Generate Vertical Interrupt every (n+1) frames\r
+\r
+ 3d6h index 2Bh (R/W): Default Video Register (not 453)\r
+ bit 0-7 On CRTs this is the color displayed during blank time.\r
+\r
+ 3d6h index 2Ch (R/W): FP Vsync (FLM) Delay Register.\r
+ bit 0-7 Number of Hsync pulses between internal Vsync and the\r
+ rising edge of First Line Marker (FLM).\r
+ Note: Only used in Flat Panel modes when 3d6h index 2Fh bit 7 is 0..\r
+\r
+ 3d6h index 2Dh (R/W): FP Hsync (LP) Delay Register.\r
+ bit 0-7 Number of character clocks between the FP Blank inactive\r
+ edge and the rising edge of the LP.\r
+ Note: Only used in Flat Panel modes when 3d6h index 2Fh bit 6 is 0 and\r
+ graphics mode horizontal compression is disabled.\r
+\r
+ 3d6h index 2Eh (R/W): FP Hsync (LP) Delay Register.\r
+ bit 0-7 Number of character clocks between the FP Blank inactive\r
+ edge and the rising edge of the LP.\r
+ Note: Only used in Flat Panel modes when 3d6h index 2Fh bit 6 is 0\r
+ and 9 dot text mode is used.\r
+\r
+ 3d6h index 2Fh (R/W): FP Hsync (LP) Width Register\r
+ bit 0-3 Width of the LP output pulse in number of character clocks.\r
+ Only in 8 dot text modes on Flat Panels.\r
+ 4 Bit 8 of the FP Hsync (LP) Delay Register (3d6h index 2Eh).\r
+ 5 Bit 8 of the FP Hsync (LP) Delay Register (3d6h index 2Dh).\r
+ 6 FP Hsync (LP) Delay Disable.\r
+ If set the FP Hsync (LP) active edge will coincide with the\r
+ FP Blank inactive edge.\r
+ 7 FP Vsync (FLM) Delay Disable.\r
+ If set the external FP Vsync (FLM) will coincide with \r
+ the internal FP Vsync (FLM) active edge.\r
+\r
+ 3d6h index 30h (R/W): Graphics Cursor Start Address High\r
+ bit 0-7 Bit 8-15 of the Cursor Start Address.\r
+\r
+ 3d6h index 31h (R/W): Graphics Cursor Start Address Low\r
+ bit 0-7 Lowest 8 bits of the Cursor Start address.\r
+ 3d6h index 30h and index Ah forms the upper 10 bits.\r
+ In 256 color modes this address has a granularity\r
+ of 16 bytes and 4 bytes in 16 color modes.\r
+\r
+ 3d6h index 32h (R/W): Graphics Cursor End Address\r
+ bit 0-7 End address of the cursor bit map.\r
+\r
+ 3d6h index 33h (R/W): Graphics Cursor X Position High\r
+ bit 0-3 Bits 8-11 of the X coordinate of the cursor.\r
+\r
+ 3d6h index 34h (R/W): Graphics Cursor X Position Low\r
+ bit 0-7 Lower 8 bits of the X coordinate of the cursor.\r
+\r
+ 3d6h index 35h (R/W): Graphics Cursor Y Position High\r
+ bit 0-3 Bits 8-11 of the Y coordinate of the cursor.\r
+\r
+ 3d6h index 36h (R/W): Graphics Cursor Y Position Low\r
+ bit 0-7 Lower 8 bits of the cursor Y coordinate.\r
+\r
+ 3d6h index 37h (R/W): Graphics Cursor Mode\r
+ bit 0 Cursor Enabled if set\r
+ 1 Cursor Status enable\r
+ 2 Horizontal Zoom. Zoom to 64 pixels wide if set.\r
+ (Normally 32 pixels wide).\r
+ 3 Cursor Blink enabled if set\r
+ 4 Cursor Blink Rate. 8 frames if clear, 16 if set\r
+\r
+ 3d6h index 38h (R/W): Graphics Cursor Plane Mask\r
+ bit 0 Enables graphics cursor in bit plane 0 if set\r
+ 1 Enables graphics cursor in bit plane 1 if set\r
+ 2 Enables graphics cursor in bit plane 2 if set\r
+ 3 Enables graphics cursor in bit plane 3 if set\r
+\r
+ 3d6h index 39h (R/W): Graphics Cursor Color 0\r
+ bit 0-7 Background color of Graphics Cursor.\r
+\r
+ 3d6h index 3Ah (R/W): Graphics Cursor Color 1\r
+ bit 0-7 Foreground color of Graphics Cursor.\r
+\r
+ 3d6h index 44h (R/W): Scratch #0 Register (82c453, 655x0 Only)\r
+ bit 0-7 Available\r
+\r
+ 3d6h index 45h (R/W): Scratch #1/Foreground Color (82c453 Only)\r
+ bit 0-7 Used as foreground color if in Fast Font Paint mode,\r
+ Available as scratch else.\r
+\r
+ 3d6h index 50h (R/W): Panel Format (82c455/6/7 Only)\r
+ bit 0-1 Frame Rate Control\r
+ 0: No gray scale simulated for mono,\r
+ 8 colors simulated for color panels.\r
+ 1: 4 simulated colors for color panels only\r
+ (64 colors displayed).\r
+ 2: (82c455/6) 64 gray levels simulated for mono. panels only.\r
+ (82c457) 16 levels simulated for each color output.\r
+ 4096 colors simulated.\r
+ 3: (82c457) 3 levels simulated for each color output.\r
+ 27 colors simulated.\r
+ 2-3 Pulse Width Modulation\r
+ 0: No gray scales for mono or color systems.\r
+ 1: 4 colors supported by the color panels only\r
+ (64 colors displayed).\r
+ 2: 16 gray levels supported by the mono panels only.\r
+ 3: 256 gray levels supported by the\r
+ color single panels only.\r
+ (655x0) Dither Enable.\r
+ 0: Disable Dither.\r
+ 1: Enable dither for 256 color modes.\r
+ 2: Enable dither for all modes. \r
+ 4-5 Clock Divide (CD).\r
+ 0: Shift Clock = Dot Clock\r
+ 1: Shift Clock = Dot Clock/2\r
+ 2: Shift Clock = Dot Clock/4\r
+ 3: (655x0) Shift Clock = Dot Clock/8.\r
+ 7 Shift Clock Mask.\r
+ If set the Shift Clock stops outside the\r
+ Display Enable interval.\r
+ 6-7 (655x0) VAM/FRC Control\r
+ 0: bit 2-3 determine the dither:\r
+ 0: 6 bpp VAM (dither bits 0-1).\r
+ 1: 4 bpp VAM (dither bits 0-1).\r
+ 2: 2 bpp VAM (dither bits 2-3).\r
+ 3: 1 bpp VAM (dither bits 4-5).\r
+ 1: 3 Bits/Pixel VAM (dither bits 1-2).\r
+ Use with bit 2-3=0 or 1 for mono panels,\r
+ Use with bit 2-3=0 for color panels.\r
+ 2: (65530) 2-Frame FRC\r
+ 3 level gray scale simulation without dither or\r
+ 9 level gray scale simulation with dither.\r
+ 3: (65530) 3 Bits/Pixel VAM + 2-Frame FRC.\r
+ 15-level gray scale simulation without dithering and\r
+ 56 level gray scale simulation with dithering.\r
+\r
+\r
+ 3d6h index 51h (R/W): Panel Type (82c455/6/7, 655x0 Only)\r
+ bit 0 (82c455/6) Double drive if set, single else\r
+ 1 Double panel if set, single else\r
+ 2-3 Type of display\r
+ 0=LCD, 1=CRT, 2=Plasma or Electrolum.\r
+ 2 (655x0) Display Type. 0=CRT, 1=Flat Panel.\r
+ 3 (655x0) 8/16 bit FP Video Interface.\r
+ If set the Flat Panel Video interface is 16 bit.\r
+ 4-5 0=Color panel 3 bit data pack\r
+ 1=Color Panel 1 bit data pack\r
+ 2=(82c455/6) Monochrome Panel\r
+ 3=(82c457) Extended 4-bit pack\r
+ 4 (655x0) Video Skew. \r
+ If set Video data is delayed 1 shift clock cycle.\r
+ 5 (655x0) Shift Clock Mask (SM). Flat Panel mode only.\r
+ If set the shift clock is forced low outside the display\r
+ interval. If clear it also toggles outside the interval.\r
+ 6 Flat Panel Compatibility enabled if set\r
+ 7 Text Video output polarity\r
+\r
+ 3d6h index 52h (R/W): Panel Size (82c455/6/7 Only)\r
+ bit 0-1 Horizontal Size of panel\r
+ 1=640 pixels, 2=720 pixels\r
+ 3-6 Vertical Size of panel\r
+ 1=200 lines, 2=350, 4=400, 8=480 lines\r
+\r
+ 3d6h index 52h (R/W): Power Down Control Register. (655x0 only)\r
+ bit 0-2 FP Normal Refresh Count. Flat Panel modes only.\r
+ Number of memory refresh cycles to perform per scanline.\r
+ 3 Panel Off Mode. If set the CRT/FP interface is inactive.\r
+ 4 Panel Off Control Bit 0. Only effective if bit 3 is set.\r
+ If set the Video data, CRT and Flat Panel timing signals\r
+ are forced inactive, rather than only the Video data.\r
+ 5 Panel Off Control bit 1. Only effective if bit 3 is set.\r
+ If set inactive video data and/or timing pins are tri-stated\r
+ rather than being driven.\r
+ 6 Standby Control. Only effective if the STNDBY/ is low.\r
+ In standby mode the video output, timings and CPU interface\r
+ are inactive. If set set the Display memory refresh is derived\r
+ from the 32kHz input. If clear the DRAMs are self-refreshed.\r
+ 7 CRT Mode Panel Off. Only effective in CRT modes.\r
+ If set Video data and timing signals are tri-stated. \r
+\r
+ 3d6h index 53h (R/W): Override Register (82c455/6/7, 655x0 Only) \r
+ bit 0 Disable AR10D2. If set the ninth pixel of characters is\r
+ controlled by this register, if clear it is controlled \r
+ by the Mode Control Register (3C0h index 10h) bit 2.\r
+ 1 Alternate Line Graphics Character Code.\r
+ Only effective if bit 0 is set.\r
+ If set the ninth pixel of a character is forced to the same value\r
+ as the 8th pixel. If clear it is forced to the background color.\r
+ 2 (655x0) FRC option 1.\r
+ 3 (655x0) FRC option 2.\r
+ 4-5 (65530) Pixel Packing. Only effective for Color STN panels.\r
+ 0: 3-bit Pack. 3d6h index 50h bits 4-5 can be 0,1 or 2.\r
+ 1: 4-bit Pack. 3d6h index 50h bits 4-5 can be 1 or 1.\r
+ 3: Extended 4-bit Pack. 3d6h index 50h bits 4-5 must be 1.\r
+ 7 (65530) High Color Mode Flat Panel Operation.\r
+ If set Hi-Color operation is enabled in hi-res modes on\r
+ Flat panel. If clear it is enabled in low-res modes.\r
+\r
+\r
+ 3d6h index 54h (R/W): Alternate Miscellaneous Output Register (82c455/6/7 Only)\r
+ bit 0 Panel Video Skew\r
+ 2-3 Clock Select Bits\r
+ 6 Hsync. Negative if set, Positive if clear. \r
+ 7 Vsync. Negative if set, Positive if clear. \r
+ Note: For Flat Panel systems this register replaces the Miscellaneous\r
+ Output Register (3C2h).\r
+\r
+ 3d6h index 54h (R/W): FP Interface Register (655x0 Only) \r
+ bit 0 FP Blank Polarity.\r
+ If set the BLANK/ pin has negative polarity.\r
+ 1 If set the BLANK/ pin outputs only the FP Horizontal Blank\r
+ signal, if clear it outputs both Vertical and Horizontal\r
+ Blank signals.\r
+ 2-3 FP Clock Select Bits 0-1.\r
+ In Flat Panel modes these bits replace 3C2h bits 2-3.\r
+ 4-5 FP Feature Control bits 0-1.\r
+ In Flat Panel modes these bits replace 3dAh bits 0-1.\r
+ 6 FP HSync (LP) Polarity.\r
+ If set the HSync (LP) pin has negative polarity.\r
+ 7 FP VSync (FLM) Polarity.\r
+ If set the Vsync (FLM) pin has negative polarity. \r
+ Note: This register is only effective in Flat Panel modes.\r
+\r
+ 3d6h index 55h (R/W): Text Mode 350_A (82c455/6/7 Only)\r
+ bit 0-3 (Number of blank lines)-1 inserted between text rows\r
+ I.e. if 5, insert 6 blank lines after a text line.\r
+ 4 If clear lines are inserted.\r
+ Note: This register is used if in a 350 line text mode\r
+ and fonts are larger than 8 lines.\r
+\r
+ 3d6h index 55h (R/W): Horizontal Compensation Register (655x0 Only)\r
+ bit 0 Enable Horizontal Compensation (EHCP)\r
+ If set Horizontal compensation is enabled.\r
+ 1 Enable Automatic Horizontal Centring (EAHC)\r
+ If set (and bit 0 is set) EAHC is enabled.\r
+ Horizontal left and right borders will be computed\r
+ automatically.\r
+ 2 Enable Text Mode Horizontal Compression (ETHC).\r
+ If set, bit 0 is set and we are in a Flat Panel Text\r
+ mode ETHC is enabled.\r
+ 9-dot text modes will be forced to 8-bit.\r
+ 5 Enable Automatic Horizontal Doubling (EAHD).\r
+ If set and bit 0 is set, EAHD is enabled.\r
+ If Horizontal Display Width (3d4h index 1) is less\r
+ than or equal to half the Horizontal Panel Size\r
+ (3d6h index 18h) horizontal pixel doubling will be forced.\r
+ 6 Alternate CRT Hsync Polarity.\r
+ Negative if set, Positive if clear.\r
+ 7 Alternate CRT Vsync Polarity.\r
+ Negative if set, Positive if clear. \r
+\r
+ 3d6h index 56h (R/W): Text Mode 350_B (82c455/6/7 Only)\r
+ bit 0-3 (Number of blank lines)-1 inserted between text rows\r
+ 4 If clear lines are inserted.\r
+ Note: This register is used if in a 350 line text mode\r
+ and fonts are smaller than or equal to 8 lines.\r
+\r
+ 3d6h index 56h (R/W): Horizontal Centring Register (655x0 Only)\r
+ bit 0-7 Horizontal Left Border.\r
+ Size of the left border in pixels -1.\r
+ Only used if in a Flat Panel mode and non-automatic\r
+ horizontal centring is enabled.\r
+\r
+ 3d6h index 57h (R/W): Text Mode 400 (82c455/6/7 Only)\r
+ bit 0-3 (Number of blank lines)-1 inserted between text rows\r
+ 4 If clear lines are inserted.\r
+ Note: This register is used if in a 400 line text mode.\r
+\r
+ 3d6h index 57h (R/W): Vertical Compensation Register (655x0 Only)\r
+ bit 0 Enable Vertical Compensation if set.\r
+ 1 Enable Automatic Vertical Centring.\r
+ If set and bit 0 set, the image will automatically\r
+ be centred vertically.\r
+ 2 Enable Text Mode Vertical Stretching.\r
+ If set and bit 0 set, text mode vertical\r
+ stretching is enabled. \r
+ 3-4 Text Mode Vertical Stretching. If bit 0 & 2 set.\r
+ 0 = Double Scanning (DS) and Line Insertion (LI)\r
+ with priority: DS+li, DS, LI.\r
+ 1 = Double Scanning (DS) and Line Insertion (LI)\r
+ with priority: DS+LI, LI, DS.\r
+ 2 = Double Scanning (DS) and TallFont (TF)\r
+ with priority: DS+TF, DS, TF.\r
+ 3 = Double Scanning (DS) and TallFont (TF)\r
+ with priority: DS+TF, TF, DS.\r
+ 5 Enable Vertical Stretching if set and bit 0 set.\r
+ 6 Vertical Stretching.If bits 0 and 5 set.\r
+ 0 = Double Scanning (DS) and Line Replication (LR)\r
+ with priority: DS+LR, DS, LR.\r
+ 1 = Double Scanning (DS) and Line Replication (LR)\r
+ with priority: DS+LR, LR, DS.\r
+\r
+ 3d6h index 58h (R/W): Graphics Mode 350 (82c455/6/7 Only)\r
+ bit 0-3 Number of scan lines between stretch/delete\r
+ 4 Enable vertical Stretching if set\r
+ 5 Enable vertical deletion if set\r
+ 6 If set the value in bits 0-3 is incremented every other period.\r
+ Note: This register is used if in a 350 line graphics mode.\r
+\r
+ 3d6h index 58h (R/W): Vertical Centring Register (655x0 Only) \r
+ bit 0-7 Vertical Top Border LSBs.\r
+ Lower 8 bits of the Vertical Top Border.\r
+ Bits 8-9 are in 3d6h index 59h bits 5-6.\r
+ Note: used only in Flat panel modes when non-automatic\r
+ vertical centring is enabled.\r
+\r
+ 3d6h index 59h (R/W): Graphics Mode 400 (82c455/6/7 Only)\r
+ bit 0-3 Number of scan lines between stretch/delete\r
+ 4 Enable vertical Stretching if set\r
+ 5 Enable vertical deletion if set\r
+ 6 If set the value in bits 0-3 is incremented every other period.\r
+ Note: This register is used if in a 400 line graphics mode.\r
+\r
+ 3d6h index 59h (R/W): Vertical Line Insertion Register (655x0 Only)\r
+ bit 0-3 Vertical line Insertion Height.\r
+ Number of lines -1 to insert between text rows.\r
+ 5-6 Bits 8-9 of the Vertical Top Border (3d6h index 58h).\r
+ Note: This register is only used in Flat Panel text modes.\r
+ \r
+ 3d6h index 5Ah (R/W): Flat Panel Vertical Display Start_400 (82c455/6/7 Only)\r
+ bit 0-7 For 400 line Flat Panel modes these are the lower 8 bits of the \r
+ Vertical Display Start (in scanlines). The upper 2 bits are in the\r
+ Flat Panel Vertical Overflow 2 Register (3d6h index 6Bh) bits 2-3.\r
+\r
+ 3d6h index 5Ah (R/W): Vertical Line Replication Register. (655x0 Only)\r
+ bit 0-3 Vertical line Replication Height.\r
+ Number of lines-1 between replicated lines. \r
+ Double scanned lines are also counted.\r
+ Note: This register is only used when in Flat Panel text modes\r
+ and Line Replication is enabled.\r
+\r
+ 3d6h index 5Bh (R/W): Flat Panel Vertical Display End_400 (82c455/6/7 Only)\r
+ bit 0-7 For 400 line Flat Panel modes these are the lower 8 bits of the \r
+ Vertical Display End (in scanlines). The upper 2 bits are in the\r
+ Flat Panel Vertical Overflow 2 Register (3d6h index 6Bh) bits 6-7.\r
+\r
+ 3d6h index 5Bh (R/W): Panel Power Sequencing Delay register (65530 Only)\r
+ bit 0-3 Panel Power Down sequencing Delay in 32ms counts. (0-480ms)\r
+ 4-7 Panel Power Up Sequencing Delay in 4ms counts. (0-60ms)\r
+ Note: This register is used only when the Panel power Sequencing\r
+ feature is enabled. Default to 81h for compatibility with 65520.\r
+\r
+ 3d6h index 5Ch (R/W): Weight Clock Control Register A (82c455/6 only)\r
+ bit 0-5 This register is used in Flat Panel mode when bit 7 of the Panel\r
+ Format Register (3d6h index 50h) is set and bits 2-3 of the same\r
+ register is either 1 or 2.\r
+ The time from Hsync to the first pulse on the WGTCLK is this\r
+ value*4 dot clocks. See also 3d6h index 5Dh and 6Ch.\r
+\r
+ 3d6h index 5Dh (R/W): Weight Clock Control Register B (82c455/6 only)\r
+ bit 0-5 This register is used in Flat Panel mode when bit 7 of the Panel\r
+ Format Register (3d6h index 50h) is set and bits 2-3 of the same\r
+ register is either 1 or 2.\r
+ The time between WGTCLK pulses is this value*4 dot clocks.\r
+ See also 3d6h index 5Ch and 6Ch.\r
+\r
+ 3d6h index 5Eh (R/W): ACDCLK Control Register (82c455/6/7, 655x0 only)\r
+ bit 0-6 ACDCLK Count. Number of Hsync pulses between changes in ACDCLK.\r
+ 7 If set the ACDCLK phase inverts every frame, if clear the ACDCLK\r
+ changes phase when the number of Hsynmc pulses specified in \r
+ bits 0-6 have elapsed.\r
+ \r
+ 3d6h index 5Fh (R/W): Power Down Mode Refresh Register (82c455/6/7, 655x0 only)\r
+ bit 0-7 (82c455/6/7) Sleep Mode Refresh Frequency.\r
+ A refresh will happen for every (4*this value)+8 dot clocks.\r
+ 0-1 (655x0) Power Down Refresh Frequency.\r
+ Refresh happens every xx micro seconds: \r
+ 0=16usek, 1=32 usek, 2=64 usek and 3=128 usek.\r
+ \r
+ 3d6h index 60h (R/W): Blink Rate Control (82c455/6/7, 655x0 Only)\r
+ bit 0-5 Blink Rate.\r
+ Character Blink Freq = Vertical sync Freq * (Blink rate+1)\r
+ Cursor blink freq = Character Blink Freq *2.\r
+ 6-7 Blink Cycle 1=25%, 2=50%, 3=75%\r
+\r
+ 3d6h index 61h (R/W): Smartmap Control (82c455/6, 655x0 Only)\r
+ bit 0 If set enables Smartmap and bypasses internal color lookup table.\r
+ 1-4 Threshold for (Foreground - Background) diff\r
+ if diff less than the threshold the foreground and\r
+ background colors will be spread (See 3d6h index 62h).\r
+ 5 Smartmap Saturation value.\r
+ If set the result is calculated modulo 16, \r
+ if clear it is rounded to min. or max. values (0 and 0Fh).\r
+ 6 (82c456, 655x0) Enhanced text if set\r
+ (reverses attributes 7h and Fh)\r
+ 7 (655x0) Text Video Output Polarity (TVP) if set.\r
+ Only effective in Flat Panel modes. \r
+\r
+ 3d6h index 62h (R/W): Smartmap Shift Parameter (82c455/6, 655x0 Only)\r
+ bit 0-3 Number of levels to shift foreground color\r
+ when too little difference (See 3d6h index 61h bit 1-4).\r
+ 4-7 Number of levels to shift background color.\r
+\r
+ 3d6h index 63h (R/W): Graphics Color Mapping Control (82c455/6 Only)\r
+ bit 0-3 Threshold color value for mono output.\r
+ All colors >= this value will be set to 1,\r
+ all lower to 0.\r
+ 4 Use upper 4 bits of 256 color if set, lower if not.\r
+ 5 Enable internal color lookup table if set\r
+ 6 Write protect internal color look up table if set\r
+ 7 Graphics output polarity\r
+\r
+ 3d6h index 63h (R/W): Smartmap Color Mapping Control (655x0 only)\r
+ bit 0-5 Color Threshold. Used for mapping 6 bit color to 1 bit.\r
+ Color values greater than or equal than this value\r
+ are mapped to 1, and lower values are mapped to 0.\r
+ 6 Must be set to 1.\r
+ 7 Graphics Video Output Polarity\r
+ Inverted polarity if set, normal if clear.\r
+ Graphics video output only.\r
+\r
+ 3d6h index 64h (R/W): Alternate Vertical Total (82c455/6/7, 655x0 only) \r
+ bit 0-7 Alternate Vertical Total\r
+ Note: For Flat Panel modes this register replaces the Vertical\r
+ Total Register (3d4h index 6).\r
+\r
+ 3d6h index 65h (R/W): Alternate Overflow (82c455/6/7, 655x0 only) \r
+ bit 0 Alternate Vertical Total bit 8\r
+ 1 (455/6/7) Alternate Vertical Display End bit 8.\r
+ (655x0) Alternate Vertical Panel Size bit 8.\r
+ 2 Alternate Vertical Sync Start bit 8.\r
+ 3 (655x0) Alternate Vertical Sync Start bit 10.\r
+ 4 (655x0) Alternate Vertical Total bit 10.\r
+ 5 Alternate Vertical Total bit 9\r
+ 6 (455/6/7) Alternate Vertical Display End bit 9.\r
+ (655x0) Alternate Vertical Panel Size bit 9.\r
+ 7 Alternate Vertical Sync Start bit 9.\r
+\r
+ 3d6h index 66h (R/W): Alternate Vertical Sync Start (82c455/6/7, 655x0 only) \r
+ bit 0-7 Alternate Vertical Sync Start\r
+ Note: For Flat Panel modes this register replaces the Vertical\r
+ Sync Start Register (3d4h index 10h).\r
+\r
+ 3d6h index 67h (R/W): Alternate Vertical Sync End (82c455/6/7, 655x0 only) \r
+ bit 0-3 Alternate Vertical Sync End\r
+ Note: For Flat Panel modes this register replaces the Vertical\r
+ Sync End Register (3d4h index 11h).\r
+\r
+ 3d6h index 68h (R/W): Alternate Vertical Display Enable (82c455/6/7 only) \r
+ bit 0-7 Alternate Vertical Display Enable\r
+ Note: For Flat Panel modes this register replaces the Vertical\r
+ Display Enable Register (3d4h index 12h)\r
+\r
+ 3d6h index 69h (R/W): Vertical Panel Size Register. (655x0 only)\r
+ bit 0-7 Vertical Panel Size. \r
+ Number of scan lines per frame.\r
+\r
+ 3d6h index 69h (R/W): Flat Panel Vertical Display Start_350 (82c455/6/7 only) \r
+ bit 0-7 For 350 line Flat Panel modes these are the lower 8 bits of the \r
+ Vertical Display Start (in scanlines). The upper 2 bits are in the\r
+ Flat Panel Vertical Overflow 2 Register (3d6h index 6Bh) bits 0-1.\r
+\r
+ 3d6h index 6Ah (R/W): Flat Panel Vertical Display End_350 (82c455/6/7 only) \r
+ bit 0-7 For 350 line Flat Panel modes these are the lower 8 bits of the \r
+ Vertical Display End (in scanlines). The upper 2 bits are in the\r
+ Flat Panel Vertical Overflow 2 Register (3d6h index 6Bh) bits 4-5.\r
+\r
+ 3d6h index 6Bh (R/W): Flat Panel Vertical Overflow 2 (82c455/6/7 only)\r
+ bit 0-1 Bits 8-9 of the Vertical Display Start_350 Register\r
+ (3d6h index 69h)\r
+ 2-3 Bits 8-9 of the Vertical Display Start_400 Register (3d6h index 5Ah\r
+ 4-5 Bits 8-9 of the Vertical Display End_350 Register (3d6h index 6Ah)\r
+ 6-7 Bits 8-9 of the Vertical Display End_400 Register (3d6h index 5Bh)\r
+\r
+ 3d6h index 6Ch (R/W): Weight Clock Control Register (82c455/6/7 only)\r
+ bit 0-5 Weight Clock Control Pulse Count.\r
+ Total number of pulses on the Weight Clock.\r
+ See Also 3d6h index 5Ch and 5Dh.\r
+\r
+ 3d6h index 6Ch (R/w): Programmable Output Drive Register (655x0 only)\r
+ bit 0 Input Level Sense Selection Mode.\r
+ If set bit 1 is used to determine input threshold.\r
+ If clear chip detects VCC voltage internally.\r
+ 1 Input Level Sense Selection Voltage.\r
+ If set VCC for internal logic is 3.3V\r
+ if clear it is 5V.\r
+ 2 Flat Panel Interface Output Drive Select\r
+ If set Higher drive, if clear Lower drive.\r
+ 3 Bus Interface Output Drive Select.\r
+ If set Higher drive, if clear Lower drive.\r
+ 4 Memory Interface output Drive Select.\r
+ If set Higher drive, if clear Lower drive.\r
+ \r
+ 3d6h index 6Dh (R/W): FRC and Palette Control (82c456/7 Only)\r
+ bit 3 Enable Frame Rate Control\r
+ 4-5 Maximum number of gray levels.\r
+ 0: 64 level FRC\r
+ 1: 16 level FRC with dither for 256 color modes.\r
+ 2: 64 level FRC with dither for low gray levels.\r
+ 3: 16 level FRC only.\r
+ 6-7 Usage of External Palette:\r
+ 0: Bypass\r
+ 1: Bypass for 16 color modes, use for 256 color.\r
+ 2: Always use\r
+ 3: 16 grays for 16 color modes, 64 for 256 color.\r
+\r
+ 3d6h index 6Eh (R/W): Polynomial FRC Control (82c456/7, 655x0 Only)\r
+ bit 0-3 Polynomial N value for Frame Rate Control\r
+ 4-7 Polynomial M value.\r
+\r
+ 3d6h index 6Fh (R/W): Frame Buffer Control register (655x0 only)\r
+ bit 0 Frame Buffer Enable.\r
+ External Frame Buffer enabled if set.\r
+ 1 Frame Accelerator enabled if set.\r
+ 2 Frame Buffer memory Type.\r
+ If set Frame Buffer consists of 256Kx4 VRAM.\r
+ If clear Frame Buffer consists of 64Kx4 VRAM\r
+ 3-5 Frame Buffer Refresh Count.\r
+ 6-7 Reserved. Must be set to 0. \r
+ Note: This register effective in Flat Panel mode only.\r
+\r
+ 3d6h index 70h (R/W): Setup/Disable Control Register. (655x0 only)\r
+ bit 7 3C3/46E8 Register Disabled if set.\r
+ \r
+ 3d6h index 7Dh (R/W): FP Compensation Diagnostic Register (655x0 only)\r
+ bit 0-7 Reserved. returns 0.\r
+\r
+ 3d6h index 7Eh (R/W): CGA Color Select \r
+ This is a copy of the CGA Color Select Register at 3D9h.\r
+ The copy at 3D9h is only visible in CGA emulation mode.\r
+ This register is always visible. \r
+\r
+ 3d6h index 7Fh (R/W): Diagnostic \r
+ bit 0 if set 3-states pins: PALRD/, PALWR/, WR46E8/, HSYNC, VSYNC,\r
+ ACDCLK, BLANK/, P0-7, RDY, DATEN/ AND IRQ/.\r
+ 1 If set 3-states pins: WE/, RAS/, CAS0/, CAS1/,\r
+ CAS2/, CAS3/, AA0-7 AND BA0-7.\r
+ 2-5 Test Function Pins. Should be 0.\r
+ 6 (655x0) Test Function Enabled if set.\r
+ 7 (655x0) Special Test Function. Should be set to 0.\r
+ \r
+ 46E8h (R/W): Setup Control PC/AT Register\r
+ bit 0-2 Reserved\r
+ 3 Enables Adapter VGA if set\r
+ 4 Enters Setup Mode if set\r
+ 5-7 Reserved\r
+Note: This is the same register as 94h.\r
+\r
+\r
+ Most every index of 3d6h is used by one one or more chip.\r
+\r
+ Bank Switching:\r
+\r
+ Bank switching is dependent on Chip version:\r
+\r
+ 16 color modes 256 color modes\r
+ Chip #bank regs #Banks Granularity #banks Granularity\r
+ 82c451/5/6 1 4 64Kbytes\r
+ 82c452 2 64 4Kbytes 64 16Kbytes\r
+ 82c453 2 256 1Kbytes 256 4Kbytes\r
+\r
+ For the 82c452 & 3 the window to display memory can start on\r
+ any boundary fitting the granularity of the chip/display mode.\r
+ When using 2 bankregisters, the address range available to the\r
+ adapter is split equally between the two bank registers. I.e.\r
+ A000h-A7FFh uses one bank, and A800h-AFFFh the other.\r
+ (Or A000h-AFFFh and B000h-BFFFh respectively if using the full\r
+ 128 Kbytes range).\r
+\r
+\r
+\r
+ ID Chips and Technologies Chip Set:\r
+\r
+\r
+ vio($6F00);\r
+ if rp.al=$5F then\r
+ case rp.bl of\r
+ 0:Chip&Tech 82c451 !!!\r
+ 1:Chip&Tech 82c452 !!! \r
+ 2:Chip&Tech 82c455 !!!\r
+ 3:Chip&Tech 82c453 !!!\r
+ 5:Chip&Tech 82c456 !!!\r
+ 6:Chip&Tech 82c457 !!!\r
+ 7:Chip&Tech F65520 !!!\r
+ 8:Chip&Tech F65530 !!!\r
+ end;\r
+\r
+\r
+\r
+ Video Modes:\r
+\r
+ 60h T 132 25 16 (8x16)\r
+ 61h T 132 50 16 (8x8)\r
+ 6Ah G 800 600 16 planar\r
+ 70h G 800 600 16 planar\r
+ 71h G 960 720 16 planar Cardinal only!\r
+ 72h G 1024 768 16 planar\r
+ 78h G 640 400 256 packed Not documented/not all boards\r
+ 79h G 640 480 256 packed\r
+ 7Ah G 720 540 256 packed Not documented/not all boards\r
+ 7Bh G 800 600 256 packed\r
+ 7Ch G 800 600 256 packed (82c453 Only)\r
+ 7Eh G 1024 768 256 packed (82c453 Only) \r
+\r
+ Bios Extensions:\r
+----------105F00-----------------------------\r
+INT 10 - Get Controller Information (Chips and Technologies Super VGA)\r
+ AX = 5F00h\r
+Return: AL = 5F If extended VGA control function supported\r
+ BL = CHIP Type:\r
+ Bits 4-7:\r
+ 0=82c451\r
+ 1=82c452\r
+ 2=82c455\r
+ 3=82c453\r
+ 5=82c456 \r
+ Bits 0-3: Revision Number\r
+ BH = Video Memory Size\r
+ 0=256 Kbytes\r
+ 1=512 Kbytes\r
+ 2=1 Megabyte\r
+ CX = Miscellaneous Information\r
+ Bit 0 Dac Size. 0=6bit, 1=8bit\r
+ 1 System Environment. 0=PC/AT, 1=PS/2\r
+ 2 Extended text modes supported by BIOS\r
+ 3 Reserved\r
+ 4 Extended graphics modes supported by BIOS\r
+ 5 Reserved\r
+ 6 Graphics Cursor supported by BIOS\r
+ 7 Anti Alias font supported by BIOS\r
+ 8 Preprogrammed emulation supported by BIOS\r
+ 9 Auto emulation supported by BIOS\r
+ 10 Variable mode set at cold boot supported by BIOS\r
+ 11 Variable mode set at warm boot supported by BIOS\r
+ 12 Emulation mode set at cold boot supported by BIOS\r
+ 13 Emulation mode set at warm boot supported by BIOS\r
+ 14-15 Reserved\r
+----------105F01-----------------------------\r
+INT 10 - Set Emulation Mode (Chips and Technologies Super VGA)\r
+ AX = 5F01h\r
+ BL = Operation Mode\r
+ 0-1 Reserved\r
+ 2 Enable CGA Emulation\r
+ 3 Enable MDA Emulation\r
+ 4 Enable Hercules Emulation\r
+ 5 Enable EGA Emulation\r
+ 6 Enable VGA Emulation\r
+Return: AL = 5Fh If function supported\r
+ AH = Return Status\r
+ 1 If Function Successful, 0 else\r
+----------105F02-----------------------------\r
+INT 10 - Auto Emulation Control (Chips and Technologies Super VGA)\r
+ AX = 5F02h Auto Emulation Control\r
+ BL = Selection\r
+ 0= Enable Auto Emulation\r
+ 1= Disable Auto Emulation\r
+Return: AL = 5Fh If function supported\r
+ AH = Return Status\r
+ 1 If Function Successful, 0 else\r
+----------105F03-----------------------------\r
+INT 10 - Set Power-on Video Configuration (Chips and Technologies Super VGA)\r
+ AX = 5F03h\r
+ BL = Configuration\r
+ 0: Set display mode as specified in the CX register\r
+ at power-up.\r
+\r
+ CL=Display Mode\r
+ CH=Bits 0-1 Scanlines\r
+ 0=200 Lines\r
+ 1=350 Lines\r
+ 2=400 Lines\r
+ Bit 7 Performance\r
+ 0= Reset after next boot\r
+ 1= Set until changed\r
+\r
+ 1: Set Emulation mode as specified in the CX register\r
+ at power-up.\r
+\r
+ CL=Emulation Mode (See 5F01h)\r
+ CH=Bit 7 Performance\r
+ 0= Reset after next boot\r
+ 1= Set until changed\r
+\r
+Return: AL = 5Fh If function supported\r
+ AH = Return Status\r
+ 1 If Function Successful, 0 else\r
+----------105F90-----------------------------\r
+INT 10 - Return Save/Restore buffer size (Chips and Technologies Super VGA)\r
+ AX = 5F90h\r
+ CX = Mask State\r
+ Bit 0 Save/Restore video hardware\r
+ 1 Save/Restore BIOS data state\r
+ 2 Save/Restore DAC state\r
+ 15 Save/Restore type\r
+ 0= Save/Restore All state information\r
+ 1= Save/Restore super state information\r
+\r
+Return: AL = 5Fh If function supported\r
+ BX = Number of 64byte blocks required\r
+----------105F91-----------------------------\r
+INT 10 - Save State (Chips and Technologies Super VGA)\r
+ AX = 5F91h\r
+ CX = Mask State\r
+ Bit 0 Save video hardware\r
+ 1 Save BIOS data state\r
+ 2 Save DAC state\r
+ 15 Save type\r
+ 0= Save All state information\r
+ 1= Save super state information\r
+ ES:BX -> Buffer to save in.\r
+Return: AL = 5Fh If function supported\r
+----------105F92-----------------------------\r
+INT 10 - Restore State (Chips and Technologies Super VGA)\r
+ AX = 5F92h\r
+ CX = Mask State\r
+ Bit 0 Restore video hardware\r
+ 1 Restore BIOS data state\r
+ 2 Restore DAC state\r
+ 15 Restore type\r
+ 0= Restore All state information\r
+ 1= Restore super state information\r
+ ES:BX -> Buffer to restore from.\r
+Return: AL = 5Fh If function supported\r