use doslib to change HSYNC/VSYNC polarity and ensure 25MHz clock.

diff --git a/16/doslib b/16/doslib
deleted file mode 160000 (submodule)
index 9756904..0000000
--- a/16/doslib
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 975690444b74e8f28ad288412c0b0c754fab2342

diff --git a/git_con.fig b/git_con.fig
index 9c560e3025b45c8ffb8733f1dd3c0dffd6cbf06b..927bd4df91ff632c75c4dc1200c5e0fb3ccc9d97 100755 (executable)
--- a/git_con.fig
+++ b/git_con.fig
@@ -3,21 +3,13 @@
        filemode = true
        bare = false
        logallrefupdates = true
-[remote "x4"]
-       url = ssh://sparky4@4ch.mooo.com:26/var/www/16/16.git
-       fetch = +refs/heads/*:refs/remotes/x4/*
+[remote "origin"]
+       url = https://github.com/sparky4/16
+       fetch = +refs/heads/*:refs/remotes/origin/*
 [branch "master"]
        remote = origin
        merge = refs/heads/master
-[remote "origin"]
-       url = git@github.com:sparky4/16.git
-       fetch = +refs/heads/*:refs/remotes/origin/*
-[remote "sf"]
-       url = ssh://sparky4q@git.code.sf.net/p/project16/code
-       fetch = +refs/heads/*:refs/remotes/sf/*
-[remote "jp"]
-       url = ssh://sparky4@git.pf.osdn.jp:/gitroot/s/sp/sparky4/project16.git
-       fetch = +refs/heads/*:refs/remotes/jp/*
-[remote "bb"]
-       url = git@bitbucket.org:sparky4/16.git
-       fetch = +refs/heads/*:refs/remotes/bb/*
+[submodule "src/lib/doslib"]
+       url = https://github.com/joncampbell123/doslib.git
+[submodule "src/lib/jsmn"]
+       url = https://github.com/zserge/jsmn.git

diff --git a/src/lib/doslib b/src/lib/doslib
index b84bf02ac8fffdfc6ff569a36efe57ed3a450ef0..59167c4e8f584f452ff5c822b4d535f5d622d0a0 160000 (submodule)
--- a/src/lib/doslib
+++ b/src/lib/doslib
@@ -1 +1 @@
-Subproject commit b84bf02ac8fffdfc6ff569a36efe57ed3a450ef0
+Subproject commit 59167c4e8f584f452ff5c822b4d535f5d622d0a0

diff --git a/src/lib/modex16.c b/src/lib/modex16.c
index 1328ac59caaa3077136aba5b817587258cb2907e..d5e17a9862221debe792e7ec35a6c8cf6bd13004 100755 (executable)
--- a/src/lib/modex16.c
+++ b/src/lib/modex16.c
@@ -143,6 +143,9 @@ void modexEnter(sword vq, boolean cmem, global_game_variables_t *gv)
                        cm.vertical_display_end = 480;\r
                        cm.vertical_blank_start = 0x1E7 + 1;\r
                        cm.vertical_blank_end = 0x206 + 1;\r
+                       cm.clock_select = 0; /* misc register = 0xE3  25MHz */\r
+                       cm.vsync_neg = 1;\r
+                       cm.hsync_neg = 1;\r
 \r
                        vga_write_crtc_mode(&cm,0);\r
                        }\r
@@ -227,27 +230,7 @@ modexsetBaseXMode()
 {\r
        /* TODO save current video mode and palette */\r
        vgaSetMode(VGA_256_COLOR_MODE);\r
-\r
        vga_enable_256color_modex();\r
-\r
-       /* disable chain4 mode */\r
-       //outpw(SC_INDEX, 0x0604);\r
-\r
-       /* synchronous reset while setting Misc Output */\r
-       //outpw(SC_INDEX, 0x0100);\r
-\r
-       /* select 25 MHz dot clock & 60 Hz scanning rate */\r
-       outp(MISC_OUTPUT, 0xe3);\r
-\r
-       /* undo reset (restart sequencer) */\r
-       //outpw(SC_INDEX, 0x0300);\r
-\r
-       /* reprogram the CRT controller */\r
-       outp(CRTC_INDEX, 0x11); /* VSync End reg contains register write prot */\r
-//     temp = inp(CRTC_DATA) & 0x7F;\r
-//     outp(CRTC_INDEX, 0x11);\r
-       outp(CRTC_DATA, 0x7f);  /* get current write protect on varios regs */\r
-//     outp(CRTC_DATA, temp);  /* get current write protect on varios regs */\r
        update_state_from_vga();\r
 }\r
 \r